CN104332446A - Dbc substrate - Google Patents
Dbc substrate Download PDFInfo
- Publication number
- CN104332446A CN104332446A CN201310309527.8A CN201310309527A CN104332446A CN 104332446 A CN104332446 A CN 104332446A CN 201310309527 A CN201310309527 A CN 201310309527A CN 104332446 A CN104332446 A CN 104332446A
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- Prior art keywords
- igbt chip
- bonding region
- dbc substrate
- chip weld
- weld zone
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a DBC substrate which comprises an insulating layer and a metal layer that forms on the insulating layer. The metal layer comprises two first IGBT chip weld zones, two second IGBT chip weld zones, two FRD chip weld zones and a bonding zone. The IGBT chip weld zones and the FRD chip weld zones are symmetrically distributed at two sides of the bonding zone. The IGBT chip weld zones and the FRD chip weld zone at one side of the bonding zone are arranged in a longitudinal direction. The bonding zone comprises an emitter electrode lead bonding zone and a gate electrode lead bonding zone. The top end of the gate electrode lead bonding zone is crossed or tangential with the horizontal line with the centers of the first IGBT chip weld zones. The bottom end of the gate electrode bonding area is crossed or tangential with the horizontal line with the centers of the second IGBT chip weld zones. The DBC substrate of the invention is compatible with two chips in which the gate electrode are respectively arranged at the middle position and one corner position at the four corners of the IGBT chip.
Description
Technical field
The invention belongs to electronic manufacturing field, particularly a kind of DBC substrate and apply the electronic device of this DBC substrate.
Background technology
For power-type electron device package, substrate, except possessing basic wiring (electrical interconnection) function, also requires to have higher heat conduction, insulation, heat-resisting, voltage endurance capability and thermal matching energy.Therefore, conventional MCPCB(metal core printed circuit board (PCB)) be difficult to the package cooling requirement meeting power-type device; And for LTCC and HTCC substrate (low temperature or High Temperature Co Fired Ceramic substrate), because interior metal circuit layer adopts silk-screen printing technique to make, easily produce the problems such as circuit is coarse, contraposition is not accurate.With DBC(Direct Bonding copper-ceramic substrate) and DPC(direct copper plating-ceramic substrate) for representative metallized ceramic substrate heat conduction, insulation, withstand voltage and heat-resisting etc. in superior performance, become the preferred material of power-type device package, and obtain the accreditation in market gradually.
Direct copper technology utilizes directly being applied by copper containing oxygen eutectic liquid of copper to be connected on pottery, its general principle is exactly between copper and pottery, introduce appropriate oxygen element before deposited termination process or in process, within the scope of 1065 DEG C ~ 1083 DEG C, copper and oxygen form Cu-O eutectic liquid, and DBC technology utilizes this eutectic liquid to generate CuAlO with ceramic substrate generation chemical reaction on the one hand
2or CuAl
2o
4phase, infiltrates the combination that Copper Foil realizes ceramic substrate and copper coin on the other hand.Direct copper ceramic substrate owing to possessing the advantage of the high and low dielectric loss of mechanical strength of the excellent conductive of copper, heat conductivility and pottery simultaneously, so be widely used.In the past few decades, bonded copper base has made very large contribution in power electronics package, and this mainly has following performance characteristics owing to direct copper substrate: thermal coefficient of expansion, superior electrical property and current capacity that good in thermal property, capacitive property, high insulation property, Si match are strong.
DBC(Direct Bonded Copper) insulating heat-conductive substrate, have that thermal resistance is low, bond strength is high, be convenient to printing figures, the advantages such as solderability is good, have been widely used in the electric power electronic modules such as such as GTR, IGBT, MCT nearly ten years.DBC substrate is convenient to Controlled by micro computer chip and high-voltage great-current to perform chip package among same module, thus shorten and reduce inner lead, improve the reliability of module and create process conditions for power model intellectuality (Smart Power), the remarkable reduction of thermal resistance is simultaneously convenient to module to larger power development.
The design of DBC substrate surface copper clad layers domain, directly affects the reliability that the heat dissipation characteristics of device, insulation characterisitic, the stability of electrical characteristics, the simplification of packaging technology and device use.Therefore, how carrying out DBC substrate surface copper clad layers layout design, is one of key technology of IGBT device package design.
The factor impact restrictions such as in IGBT device encapsulation, DBC substrate layout design is mainly subject to IGBT device encapsulation volume, comprises igbt chip quantity, the size of igbt chip and domain structure, the electrical connection form of IGBT device and the electric current and voltage capacity of IGBT device.
Existing meet four igbt chips, two panels FRD chip needs in parallel DBC layout design as shown in Figure 1, the arrangement of its chips and being interconnected as shown in Figure 2.This domain, for the chip structure design of grid in igbt chip corner, meets four igbt chips, two panels FRD chips and is connected in parallel needs, can meet the heat radiation of device package, conduction, insulation, electromagnetic compatibility parameter request.But deficiency is this layout design only for the chip structure design of grid in igbt chip corner, and for the chip structure of grid in igbt chip centre position, mainly there are the following problems to adopt this domain:
(1) length of grid lead bonding region is shorter, occur in bonding process that gate bond line and emitter bonding line intersect, line-spacing is between the two nearer, be difficult to meet grid and emitter bonding line pitch requirements, easily occurring grid Problem of Failure in using, there is potential risk in the dependability of device.
(2) chip emission pole wire bonding district layers of copper area is too small, makes bonding line seriously stacking, and it is large that bonding connects difficulty, shown in ginseng Fig. 3.
In view of this, be necessary to provide a kind of novel DBC substrate.
Summary of the invention
For the deficiencies in the prior art, the technical problem that the present invention solves is to provide a kind of DBC substrate and applies the electronic device of this DBC substrate, the compatible grid of this DBC substrate is at igbt chip centre position and corner location two kinds of chips, can not only meet the heat radiation of device package, conduction, electromagnetic compatibility parameter request, and bonding technology is simple.
For solving above-mentioned technical problem, technical scheme of the present invention is achieved in that
A kind of DBC substrate, comprise insulating barrier and be formed at the metal level on this insulating barrier, described metal level comprises 2 the first igbt chip weld zones, 2 the second igbt chip weld zones, 2 FRD chips welding districts and bonding region, the first described igbt chip weld zone, second igbt chip weld zone and FRD chips welding district are symmetrically distributed in the both sides of described bonding region, be positioned at the first igbt chip weld zone of side, described bonding region, second igbt chip weld zone and FRD chip longitudinally arrange, and the second igbt chip weld zone is between the first igbt chip weld zone and FRD chip, wherein, described bonding region comprises emitter terminal bonding region and grid lead bonding region, the top of described grid lead bonding region is crossing or tangent with the horizontal line at the place, center of described first igbt chip weld zone, the bottom of described grid lead bonding region is crossing or tangent with the horizontal line at the place, center of the second igbt chip weld zone.
As a further improvement on the present invention, the described grid lead bonding region side relative with emitter terminal bonding region is parallel and be all set to L shape.
As a further improvement on the present invention, described metal level is layers of copper.
As a further improvement on the present invention, described metal level is copper alloy.
As a further improvement on the present invention, described copper alloy is cupromanganese, ormolu, albronze, copper magnesium alloy, copper zirconium alloy or Cu-Ni-Mg alloy.
As a further improvement on the present invention, described insulating barrier is potsherd.
As a further improvement on the present invention, described potsherd is aluminium oxide, aluminium nitride, beryllium oxide or carborundum.
The invention also discloses a kind of electronic device, the chip that this electronic device comprises above-mentioned arbitrary described DBC substrate and is welded on this DBC substrate.
Compared with prior art, DBC substrate of the present invention has the following advantages:
(1) DBC substrate of the present invention does not have to change (as: welding positions of the welding position of 2 grid pins, the welding position of 2 main electrodes, six chips) on macro-size, can continue to use a current welding tooling to weld, avoid causing unnecessary waste.
(2) length of DBC substrate near the layers of copper (bonding position of grid lead wire) of grid pin is added, the gate location of igbt chip is made to reach parallel with the position of layers of copper gate bond point, reduce the span of bonding line and the angle of bonding point, the intersection of two chips grid lead wire and the emitter lead-out wire in bonding process that can also avoid.
(3) add the length of DBC substrate emitter bonding point layers of copper, the wire spacing of chip emission pole lead-out wire can be increased.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Figure 1 shows that the structural representation of DBC substrate in prior art;
Figure 2 shows that the arrangement schematic diagram (grid is in igbt chip corner) of DBC base chip on board and bonding line in prior art;
Figure 3 shows that the arrangement schematic diagram (grid is at igbt chip center) of DBC base chip on board and bonding line in prior art;
Figure 4 shows that the structural representation of DBC substrate in the specific embodiment of the invention;
Figure 5 shows that the arrangement schematic diagram of DBC base chip on board and bonding line in the specific embodiment of the invention;
To Figure 6 shows that in the specific embodiment of the invention that on DBC substrate, metal level is relative to the improved confinement (dash area) of prior art.
Embodiment
The present invention is not suitable for the chip structure of grid in igbt chip centre position mainly for existing DBC layout design and uses problem, propose the DBC layout design of a kind of compatible grid at igbt chip centre position and corner location two kinds of chip structures, can not only meet the heat radiation of device package, conduction, electromagnetic compatibility parameter request, and bonding technology is simple.
Particularly, the embodiment of the invention discloses a kind of DBC substrate, comprise insulating barrier and be formed at the metal level on this insulating barrier, described metal level comprises 2 the first igbt chip weld zones, 2 the second igbt chip weld zones, 2 FRD chips welding districts and bonding region, the first described igbt chip weld zone, second igbt chip weld zone and FRD chips welding district are symmetrically distributed in the both sides of described bonding region, be positioned at the first igbt chip weld zone of side, described bonding region, second igbt chip weld zone and FRD chip longitudinally arrange, and the second igbt chip weld zone is between the first igbt chip weld zone and FRD chip, wherein, described bonding region comprises emitter terminal bonding region and grid lead bonding region, the top of described grid lead bonding region is crossing or tangent with the horizontal line at the place, center of described first igbt chip weld zone, the bottom of described grid lead bonding region is crossing or tangent with the horizontal line at the place, center of the second igbt chip weld zone.
Preferably, in above-mentioned DBC substrate, metal level is layers of copper or copper alloy, and described copper alloy is cupromanganese, ormolu, albronze, copper magnesium alloy, copper zirconium alloy or Cu-Ni-Mg alloy; Described insulating barrier is potsherd, and described potsherd is aluminium oxide, aluminium nitride, beryllium oxide or carborundum.
The embodiment of the invention also discloses a kind of electronic device, the chip that this electronic device comprises above-mentioned DBC substrate and is welded on this DBC substrate.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be described in detail the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belongs to the scope of protection of the invention.
Shown in ginseng Fig. 4 and Fig. 5, DBC substrate comprises insulating barrier 11 and is formed in metal level 12 on insulating barrier 11.
Insulating barrier 11 is potsherd, and potsherd can be selected from aluminium oxide, aluminium nitride, beryllium oxide or carborundum.
The material of metal level 12 is preferably copper, can be also copper alloy, when for copper alloy, is preferably cupromanganese, ormolu, albronze, copper magnesium alloy, copper zirconium alloy or Cu-Ni-Mg alloy.
Metal level 12 comprises FRD chips welding district 123,122,2, the second igbt chip weld zone, 121,2,2 the first igbt chip weld zones and bonding region 124, first igbt chip weld zone 122, igbt chip weld zone 121, second and FRD chips welding district 123 are symmetrically distributed in the both sides of bonding region 124, the the first igbt chip weld zone 122, igbt chip weld zone 121, second and the FRD chip 123 that are positioned at side, bonding region 124 longitudinally arrange, and the second igbt chip weld zone 122 is between the first igbt chip weld zone 121 and FRD chip 123.
Bonding region 124 comprises emitter terminal bonding region 1241 and grid lead bonding region 1242, the top of grid lead bonding region 1242 is crossing or tangent with the horizontal line A at the place, center of the first igbt chip weld zone 121, and the bottom of grid lead bonding region 1242 is crossing or tangent with the horizontal line B at the place, center of the second igbt chip weld zone 122.Shown in ginseng Fig. 5, the position that gate location and the position of layers of copper gate bond point of igbt chip reach parallel even layers of copper gate bond point is positioned at the horizontal top, gate location place of igbt chip, reduce the span of bonding line and the angle of bonding point, the intersection of two chips grid lead wire and the emitter lead-out wire in bonding process that can also avoid
Grid lead bonding region 1242 side relative with emitter terminal bonding region 1241 is parallel and be all set to L shape.Particularly, emitter terminal bonding region 1241 extends longitudinally, and its side adjacent with grid lead bonding region 1242 is L shape, and the first half width of emitter terminal bonding region 1241 is less than the width of the latter half.Grid lead bonding region 1242 extends longitudinally, and its side adjacent with emitter terminal bonding region 1241 is set to L shape, and parallel with the L shape side of emitter terminal bonding region 1241.Owing to adding the width of DBC substrate emitter terminal bonding region 1241 the latter half, the wire spacing of chip emission pole lead-out wire can be increased.
The IGBT module DBC substrate that the embodiment of the present invention designs, when meeting the heat radiation of device package, conduction, insulation, electromagnetic compatibility parameter request, the basis of former DBC substrate has been carried out the improvement of some process aspects.Shown in the area composition graphs 6 improved, concrete improvement is as follows:
(1) under the prerequisite not affecting the welding of grid pin, reduce the area of DBC substrate surface grid pin weld copper clad layers.
(2) add the length of the copper clad layers of DBC substrate and igbt chip grid junction and optimal design has been done to it.
(3) area of the copper clad layers of DBC substrate and igbt chip emitter and FRD chip positive pole junction is added.
In sum, DBC substrate of the present invention has following advantage:
(1) this DBC substrate does not have to change (as: welding positions of the welding position of 2 grid pins, the welding position of 2 main electrodes, six chips) on macro-size, can continue to use a current welding tooling to weld, avoid causing unnecessary waste.
(2) length of DBC substrate near the layers of copper (bonding position of grid lead wire) of grid pin is added, the position making the gate location of igbt chip and the position of layers of copper gate bond point reach parallel even layers of copper gate bond point is positioned at the horizontal top, gate location place of igbt chip, reduce the span of bonding line and the angle of bonding point, the intersection of two chips grid lead wire and the emitter lead-out wire in bonding process that can also avoid.
(3) add the length of DBC substrate emitter bonding point layers of copper, the wire spacing of chip emission pole lead-out wire can be increased.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present invention or essential characteristic, the present invention can be realized in other specific forms.Therefore, no matter from which point, all should embodiment be regarded as exemplary, and be nonrestrictive, scope of the present invention is limited by claims instead of above-mentioned explanation, and all changes be therefore intended in the implication of the equivalency by dropping on claim and scope are included in the present invention.Any Reference numeral in claim should be considered as the claim involved by limiting.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, and the technical scheme in each embodiment also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
Claims (8)
1. a DBC substrate, comprise insulating barrier and be formed at the metal level on this insulating barrier, described metal level comprises 2 the first igbt chip weld zones, 2 the second igbt chip weld zones, 2 FRD chips welding districts and bonding region, the first described igbt chip weld zone, second igbt chip weld zone and FRD chips welding district are symmetrically distributed in the both sides of described bonding region, be positioned at the first igbt chip weld zone of side, described bonding region, second igbt chip weld zone and FRD chip longitudinally arrange, and the second igbt chip weld zone is between the first igbt chip weld zone and FRD chip, it is characterized in that: described bonding region comprises emitter terminal bonding region and grid lead bonding region, the top of described grid lead bonding region is crossing or tangent with the horizontal line at the place, center of described first igbt chip weld zone, the bottom of described grid lead bonding region is crossing or tangent with the horizontal line at the place, center of the second igbt chip weld zone.
2. DBC substrate according to claim 1, is characterized in that: the described grid lead bonding region side relative with emitter terminal bonding region is parallel and be all set to L shape.
3. DBC substrate according to claim 1, is characterized in that: described metal level is layers of copper.
4. DBC substrate according to claim 1, is characterized in that: described metal level is copper alloy.
5. DBC substrate according to claim 4, is characterized in that: described copper alloy is cupromanganese, ormolu, albronze, copper magnesium alloy, copper zirconium alloy or Cu-Ni-Mg alloy.
6. DBC substrate according to claim 1, is characterized in that: described insulating barrier is potsherd.
7. DBC substrate according to claim 6, is characterized in that: described potsherd is aluminium oxide, aluminium nitride, beryllium oxide or carborundum.
8. an electronic device, is characterized in that: the chip comprising the arbitrary described DBC substrate of claim 1 to 7 and be welded on this DBC substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310309527.8A CN104332446A (en) | 2013-07-22 | 2013-07-22 | Dbc substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310309527.8A CN104332446A (en) | 2013-07-22 | 2013-07-22 | Dbc substrate |
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|---|---|
| CN104332446A true CN104332446A (en) | 2015-02-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310309527.8A Pending CN104332446A (en) | 2013-07-22 | 2013-07-22 | Dbc substrate |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109755229A (en) * | 2018-12-20 | 2019-05-14 | 浙江芯丰科技有限公司 | A kind of IGBT module |
| WO2020108365A1 (en) * | 2018-11-28 | 2020-06-04 | 烟台台芯电子科技有限公司 | Igbt half-bridge module structure |
| CN113035787A (en) * | 2019-12-25 | 2021-06-25 | 株洲中车时代半导体有限公司 | Reverse conducting type power semiconductor module packaging structure and packaging method thereof |
| CN116544127A (en) * | 2023-07-07 | 2023-08-04 | 赛晶亚太半导体科技(浙江)有限公司 | Preparation method and connection structure of power device with high current |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19549011A1 (en) * | 1995-12-28 | 1997-07-03 | Eupec Gmbh & Co Kg | Power semiconductor module with parallel IGBT chips |
| EP1808954A2 (en) * | 1991-09-20 | 2007-07-18 | Hitachi, Ltd. | IGBT-module |
| CN202502986U (en) * | 2012-02-23 | 2012-10-24 | 株洲南车时代电气股份有限公司 | Igbt module |
-
2013
- 2013-07-22 CN CN201310309527.8A patent/CN104332446A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1808954A2 (en) * | 1991-09-20 | 2007-07-18 | Hitachi, Ltd. | IGBT-module |
| DE19549011A1 (en) * | 1995-12-28 | 1997-07-03 | Eupec Gmbh & Co Kg | Power semiconductor module with parallel IGBT chips |
| CN202502986U (en) * | 2012-02-23 | 2012-10-24 | 株洲南车时代电气股份有限公司 | Igbt module |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020108365A1 (en) * | 2018-11-28 | 2020-06-04 | 烟台台芯电子科技有限公司 | Igbt half-bridge module structure |
| CN109755229A (en) * | 2018-12-20 | 2019-05-14 | 浙江芯丰科技有限公司 | A kind of IGBT module |
| CN109755229B (en) * | 2018-12-20 | 2023-08-25 | 浙江芯丰科技有限公司 | IGBT module |
| CN113035787A (en) * | 2019-12-25 | 2021-06-25 | 株洲中车时代半导体有限公司 | Reverse conducting type power semiconductor module packaging structure and packaging method thereof |
| CN113035787B (en) * | 2019-12-25 | 2024-04-19 | 株洲中车时代半导体有限公司 | Reverse conducting type power semiconductor module packaging structure and packaging method thereof |
| CN116544127A (en) * | 2023-07-07 | 2023-08-04 | 赛晶亚太半导体科技(浙江)有限公司 | Preparation method and connection structure of power device with high current |
| CN116544127B (en) * | 2023-07-07 | 2023-09-22 | 赛晶亚太半导体科技(浙江)有限公司 | Preparation method and connection structure of power device with high current |
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Application publication date: 20150204 |