CN203617266U - Power semiconductor module - Google Patents
Power semiconductor module Download PDFInfo
- Publication number
- CN203617266U CN203617266U CN201320555680.4U CN201320555680U CN203617266U CN 203617266 U CN203617266 U CN 203617266U CN 201320555680 U CN201320555680 U CN 201320555680U CN 203617266 U CN203617266 U CN 203617266U
- Authority
- CN
- China
- Prior art keywords
- power semiconductor
- chip
- semiconductor modular
- copper layer
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The utility model provides a power semiconductor module, which comprises a DBC substrate, wherein the DBC substrate is fixed above a pedestal, and the DBC substrate comprises a first copper layer set thereon, a ceramic layer fixedly set above the first copper layer, and second copper layers with a plurality of intervals fixedly set above the ceramic layer, and the upper surface of the ceramic layer is provided with groove, and the groove is set between two adjacent second copper layers; a chip, wherein the chip is fixedly set above the second copper layers; a housing, wherein the housing covers the chip, the DBC substrate and the upper surface of the pedestal; an electrode, wherein the electrode is fixedly set at on the upper surface of the housing; and a lead wire, wherein one end of the lead wire is connected to the electrode and the other end is connected to the chip. The power semiconductor module provided by the utility model can protect the chip when affected by outside force, and the service life of the power semiconductor template is prolonged.
Description
Technical field
The utility model relates to a kind of power semiconductor modular.
Background technology
DBC(Direct Bonding Cooper; Covering copper ceramic substrate) substrate is to adopt characteristics of Direct Wafer Bonded that copper circuit (covering copper layer) and ceramic substrate Direct Bonding is integral, on ceramic substrate, above some copper circuits of bonding, welding chip the corresponding aluminum steel of bonding carry out circuit connection, thereby realize the function of circuit turn-on.DBC substrate has the advantages such as high-termal conductivity, high-insulativity, easy weldability, is widely used in power semiconductor modular.
Although DBC substrate has above-mentioned many good performances, because the main part of DBC substrate is pottery, the mechanical strength of pottery is poor, easily fracture under the effect that is subject to external force.Fig. 1 is the profile of a power semiconductor modular of the prior art, with reference to figure 1, described power semiconductor modular comprises the base 11 that is positioned at bottom, be welded on the DBC substrate 12 of base 11 tops, be fixedly installed on the chip 13 of DBC substrate 12 tops, cover the shell 14 of described base 11, DBC substrate 12 and chip 13, described shell 14 is exposed in described base 11 bottoms, be positioned at the electrode 15 of described shell 14 upper surfaces, connect the lead-in wire 16 of described electrode 15 and chip 13.Described DBC substrate 12 comprise be positioned at bottom and be connected with base 11 first cover copper layer 121, be positioned at first and cover the ceramic layer 122 of copper layer 121 top and be positioned at multiple described second of ceramic layer 122 tops and cover copper layer 123, described first cover copper layer 121, ceramic layer 122 and multiple second covers copper layer 123 and links into an integrated entity.In the time that described power semiconductor modular is being subject under External Force Acting, there will be fracture because the ceramic layer 122 of DBC substrate 12 is more crisp, generally the ceramic layer 122 of described DBC substrate 12 can rupture in the multiple described second position of covering between copper layer 123, can cause in this case second to cover copper layer 123 and the first insulation distance covering between copper layer 121 shortens, decreasing insulating, in use there will be high voltage arc, beats the phenomenons such as electric arc; Under special circumstances, for example, when described power semiconductor modular is subject to External Force Acting when larger, the ceramic layer 122 of described DBC substrate 12 is likely from being positioned at the second chip 13 regional fractures that cover copper layer 123 top, thereby defective chip 13 makes described power semiconductor modular disabler.
Utility model content
The utility model one of is intended to solve the problems of the technologies described above at least to a certain extent or at least provides a kind of useful business to select.For this reason, the purpose of this utility model is to propose a kind of power semiconductor modular, adopts described power semiconductor modular not only can protect chip, and improves withstand voltage properties.
According to power semiconductor modular of the present utility model, comprise base; DBC substrate, described DBC substrate is fixedly installed on the top of described base, described DBC substrate comprise disposed thereon first cover copper layer, be fixedly installed on described first cover the ceramic layer of copper layer top and be fixedly installed on described ceramic layer top multiple intervals second cover copper layer, described ceramic layer upper surface is provided with groove, and described groove covers between copper layer at adjacent two described second; Chip, described chip is fixedly installed on the described second top of covering copper layer; Shell, described shell covers the upper surface of described chip, DBC substrate and base; Electrode, described electrode is fixedly installed on described upper surface of outer cover; Lead-in wire, described lead-in wire one end connects described electrode, and the other end connects described chip.
Power semiconductor modular of the present utility model is arranged groove and described groove is arranged on to adjacent two second by the ceramic layer upper surface at DBC substrate and covers between copper layer; in the time that described power semiconductor modular is subject to External Force Acting; the ceramic layer of described DBC substrate will be from described groove fracture; thereby can not rupture at chip area; protect chip, extended the life-span of power semiconductor modular.
In addition, the power semiconductor modular above-mentioned according to the utility model, can also have following additional technical characterictic:
Described power semiconductor modular also comprises insulating barrier, and described insulating barrier is filled described groove.
The degree of depth of described groove is 30%-70% of described ceramic layer thickness.
The width of described groove is 0.1-2mm.
Described groove is positioned at adjacent two described second middles of covering copper layer.
Described groove be shaped as U font, V-shape or rectangular build.
Described chip comprises IGBT(Insulated Gate Bipolar Transistor; Insulated gate bipolar transistor) chip and FRD(Fast Recovery Diode; Fast recovery diode) chip.
Described chip comprises FRD chip.
Power semiconductor modular of the present utility model is arranged groove and described groove is arranged on to adjacent two second by the ceramic layer upper surface at DBC substrate and covers between copper layer, in the time that described power semiconductor modular is subject to External Force Acting, the ceramic layer of described DBC substrate will be from described groove fracture, thereby can not rupture at chip area, protect chip, extended the life-span of power semiconductor modular; In described groove, fill insulating barrier, thereby in the time of described groove fracture, improve the withstand voltage properties of described power semiconductor modular simultaneously.
Additional aspect of the present utility model and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present utility model.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present utility model and advantage accompanying drawing below combination is understood becoming the description of embodiment obviously and easily, wherein:
Fig. 1 is the profile of a power semiconductor modular of the prior art;
Fig. 2 is the profile of the power semiconductor modular of an embodiment of the present utility model;
Fig. 3 is the enlarged drawing at A place in Fig. 2;
Fig. 4 is the profile that the power semiconductor modular of an embodiment of the present utility model comprises insulating barrier;
Fig. 5 is the enlarged drawing at B place in Fig. 4; And
Fig. 6 is the profile that the power semiconductor modular of an embodiment of the present utility model is combined with radiator.
Embodiment
Describe embodiment of the present utility model below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, be intended to for explaining the utility model, and can not be interpreted as restriction of the present utility model.
Fig. 2 is the profile of the power semiconductor modular of an embodiment of the present utility model, Fig. 3 is the enlarged drawing at A place in Fig. 2, with reference to figure 2-Fig. 3, a kind of power semiconductor modular that the utility model provides, comprise base 11, described base 11 copper pedestal that normally mechanical strength is higher, heat dispersion is good or aluminium backing, DBC substrate 12, described DBC substrate 12 is fixed on the top of described base 11 conventionally by the mode of welding, described DBC substrate 12 comprises that disposed thereon first covers copper layer 121, be fixedly installed on described first cover the ceramic layer 122 of copper layer 121 top and be fixedly installed on described ceramic layer 122 tops multiple intervals second cover copper layer 123, described DBC substrate 12 covers copper layer 121 by bonding techniques by described first, multiple second covers copper layer 123 is fixed into one with ceramic layer 122 bondings, the upper surface of described ceramic layer 122 is provided with groove 124, described groove 124 covers between copper layer 123 at adjacent two described second, chip 13, described chip 13 is fixedly installed on the described second top of covering copper layer 123, shell 14, described shell 14 covers the upper surface of described chip 13, DBC substrate 12 and base 11,, in the time encapsulating described semiconductor module with shell 14, the bottom surface of described base 11 is exposed, electrode 15, described electrode 15 is fixedly installed on described shell 14 upper surfaces, lead-in wire 16, described lead-in wire 16 one end connect described electrode 15, and the other end connects described chip 13.Power semiconductor modular of the present utility model is arranged groove 124 and described groove 124 is arranged on to adjacent two second by ceramic layer 122 upper surfaces at DBC substrate 12 and covers between copper layer 123; in the time that described power semiconductor modular is subject to External Force Acting; the ceramic layer 122 of described DBC substrate 12 will be from described groove 124 fractures; thereby can be at chip 13 regional fractures; and then protected chip 13, extend the life-span of power semiconductor modular.
In concrete enforcement, described power semiconductor modular also comprises insulating barrier 17, and described insulating barrier 17 is filled described groove 124.Fig. 4 is the profile that comprises insulating barrier of the power semiconductor modular of an embodiment of the utility model, Fig. 5 is the enlarged drawing at B place in Fig. 4, with reference to figure 4-5, in the present embodiment, described insulating barrier 17 is silica gel, use silica gel to fill described groove 124, in the time that described groove 124 ruptures, described silica gel can intercept described second and cover copper layer 123 and cover copper layer 121 with described first, thereby increase second and cover copper layer 123 and the first insulation distance covering between copper layer 121, increase the withstand voltage properties of power semiconductor modular, extend the life-span of power semiconductor modular.
In concrete enforcement, the degree of depth of described groove 124 is 30%-70% of described ceramic layer 122 thickness.In the present embodiment, the degree of depth of described groove 124 is preferably 50% of described ceramic layer 122 thickness.Be set to 50% of described ceramic layer 122 thickness by the degree of depth of described groove 124; both can guarantee the mechanical strength of ceramic layer 122; and described in the time being subject to External Force Acting, ceramic layer 122 can be from described groove 124 fractures; thereby protect chip 13, extended the life-span of power semiconductor modular.
In concrete enforcement, the width of described groove 124 is 0.1-2mm.In the present embodiment, the width of described groove 124 is preferably 1mm.Width by described groove 124 is set to 1mm; both can guarantee the mechanical strength of ceramic layer 122; and ceramic layer 122 can rupture from described groove 124 described in the time being subject to External Force Acting, thereby protect chip 13, extended the life-span of power semiconductor modular.
In concrete enforcement, described groove 124 is positioned at adjacent two described second middles of covering copper layer 123.By described groove 124 being arranged on to adjacent two described second positions, middle of covering copper layer 123; described in making in the time being subject to External Force Acting, second of groove 124 both sides covers the active force that copper layer 123 is subject to and equates; thereby make described ceramic layer 122 from described groove 124 fractures; and then protected chip 13, extend the life-span of power semiconductor modular.
In concrete enforcement, described groove 124 can be various shapes, such as U font, rectangular build, V-shape etc.
In concrete enforcement, described chip 13 comprises igbt chip and FRD chip.In the time that described chip 13 comprises igbt chip and FRD chip, described power semiconductor modular is IGBT module.
In concrete enforcement, described chip 13 comprises FRD chip.In the time that described chip 13 only includes FRD chip, described power semiconductor modular is FRD module.
Power semiconductor modular of the present utility model both can be applied in IGBT module, also can be applied in FRD module.
Power semiconductor modular of the present utility model in use can produce a large amount of heats, and the accumulation of amount of heat can affect the service behaviour of chip, therefore in actual applications, described power semiconductor modular and radiator need to be linked together, the dissipation of heat described power semiconductor modular being produced by radiator is gone out.Fig. 6 is the profile that the power semiconductor modular of an embodiment of the utility model is combined with radiator, with reference to figure 6, described power semiconductor modular is fixed on radiator 18 by screw 19, the base 11 of described power semiconductor modular contacts described radiator 18, and then the heat that described power semiconductor modular is produced distributes by radiator 18, thereby extend life-span of power semiconductor modular.
Power semiconductor modular of the present utility model is arranged groove 124 and described groove 124 is arranged on to adjacent two second by ceramic layer 122 upper surfaces at DBC substrate 12 and covers between copper layer 123, in the time that described power semiconductor modular is subject to External Force Acting, the ceramic layer 122 of described DBC substrate 12 will be from described groove 124 fractures, thereby can be at chip 13 regional fractures, protect chip 13, extended the life-span of power semiconductor modular; In described groove 124, fill insulating barrier 17, thereby in the time that described groove 124 ruptures, improve the withstand voltage properties of described power semiconductor modular simultaneously.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present utility model or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And specific features, structure, material or the feature of description can be with suitable mode combination in any one or more embodiment or example.
Although illustrated and described embodiment of the present utility model above, be understandable that, above-described embodiment is exemplary, can not be interpreted as restriction of the present utility model, those of ordinary skill in the art can change above-described embodiment in the situation that not departing from principle of the present utility model and aim in scope of the present utility model, modification, replacement and modification.
Claims (9)
1. a power semiconductor modular, is characterized in that, comprising:
Base;
DBC substrate, described DBC substrate is fixedly installed on the top of described base, described DBC substrate comprise disposed thereon first cover copper layer, be fixedly installed on described first cover the ceramic layer of copper layer top and be fixedly installed on described ceramic layer top multiple intervals second cover copper layer, described ceramic layer upper surface is provided with groove, and described groove covers between copper layer at adjacent two described second;
Chip, described chip is fixedly installed on the described second top of covering copper layer;
Shell, described shell covers the upper surface of described chip, DBC substrate and base;
Electrode, described electrode is fixedly installed on described upper surface of outer cover;
Lead-in wire, described lead-in wire one end connects described electrode, and the other end connects described chip.
2. power semiconductor modular as claimed in claim 1, is characterized in that, also comprises: insulating barrier, described insulating barrier is filled described groove.
3. power semiconductor modular as claimed in claim 1 or 2, is characterized in that, the degree of depth of described groove is described ceramic layer thickness 30%-70%.
4. power semiconductor modular as claimed in claim 1 or 2, is characterized in that, the width of described groove is 0.1-2mm.
5. power semiconductor modular as claimed in claim 3, is characterized in that, described groove is positioned at adjacent two described second middles of covering copper layer.
6. power semiconductor modular as claimed in claim 4, is characterized in that, described groove is positioned at adjacent two described second middles of covering copper layer.
7. the power semiconductor modular as described in claim 5 or 6, is characterized in that, described groove be shaped as U font, V-shape or rectangular build.
8. power semiconductor modular as claimed in claim 1 or 2, is characterized in that, described chip comprises igbt chip and FRD chip.
9. power semiconductor modular as claimed in claim 1 or 2, is characterized in that, described chip comprises FRD chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320555680.4U CN203617266U (en) | 2013-09-09 | 2013-09-09 | Power semiconductor module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320555680.4U CN203617266U (en) | 2013-09-09 | 2013-09-09 | Power semiconductor module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203617266U true CN203617266U (en) | 2014-05-28 |
Family
ID=50769892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320555680.4U Expired - Lifetime CN203617266U (en) | 2013-09-09 | 2013-09-09 | Power semiconductor module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203617266U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106531702A (en) * | 2016-12-15 | 2017-03-22 | 重庆大学 | Cellular structure type power module 3D packaging configuration |
| CN113726224A (en) * | 2021-09-13 | 2021-11-30 | 雅迪科技集团有限公司 | Motor controller of integrative encapsulation |
-
2013
- 2013-09-09 CN CN201320555680.4U patent/CN203617266U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106531702A (en) * | 2016-12-15 | 2017-03-22 | 重庆大学 | Cellular structure type power module 3D packaging configuration |
| CN106531702B (en) * | 2016-12-15 | 2019-07-23 | 重庆大学 | Structure cell formula power module 3D packaging structure |
| CN113726224A (en) * | 2021-09-13 | 2021-11-30 | 雅迪科技集团有限公司 | Motor controller of integrative encapsulation |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9871463B2 (en) | Power module | |
| US8872332B2 (en) | Power module with directly attached thermally conductive structures | |
| JP2007073743A (en) | Semiconductor device | |
| US8674492B2 (en) | Power module | |
| EP3104412B1 (en) | Power semiconductor module | |
| CN107004644B (en) | Insulate electrical substrate, power module and power cell | |
| US20170117212A1 (en) | Semiconductor device | |
| US9159715B2 (en) | Miniaturized semiconductor device | |
| CN105518865A (en) | Semiconductor device | |
| US10672677B2 (en) | Semiconductor package structure | |
| JPWO2014097798A1 (en) | Semiconductor device | |
| CN105161477A (en) | Planar power module | |
| US10192806B2 (en) | Semiconductor device | |
| CN104882423A (en) | Semiconductor device | |
| JP2015198171A (en) | power semiconductor module | |
| CN110246835B (en) | Three-dimensional integrated high-voltage silicon carbide module packaging structure | |
| JP6124810B2 (en) | Power module | |
| CN203617266U (en) | Power semiconductor module | |
| CN103531544B (en) | Explosion-proof semiconductor module | |
| CN105529309B (en) | Semiconductor device | |
| KR102100859B1 (en) | Dual side cooling power module and manufacturing method of the same | |
| CN203617265U (en) | Power semiconductor module | |
| CN105247675A (en) | Semiconductor device | |
| CN203774281U (en) | Intelligent power module integrally injection-moulded and packaged | |
| CN111524877B (en) | Double-sided heat dissipation power module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20191230 Address after: 518119 1 Yanan Road, Kwai Chung street, Dapeng New District, Shenzhen, Guangdong Patentee after: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. Address before: BYD 518118 Shenzhen Road, Guangdong province Pingshan New District No. 3009 Patentee before: BYD Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: BYD Semiconductor Co.,Ltd. Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140528 |
|
| CX01 | Expiry of patent term |