CN218647931U - Half-bridge driving chip structure for active clamping flyback framework - Google Patents

Half-bridge driving chip structure for active clamping flyback framework Download PDF

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CN218647931U
CN218647931U CN202221206656.5U CN202221206656U CN218647931U CN 218647931 U CN218647931 U CN 218647931U CN 202221206656 U CN202221206656 U CN 202221206656U CN 218647931 U CN218647931 U CN 218647931U
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pin
chip
gallium nitride
base island
power tube
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赵少峰
程兆辉
孙经纬
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Dongke Semiconductor Anhui Co ltd
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Dongke Semiconductor Anhui Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The embodiment of the utility model provides a half-bridge drive chip structure for active clamping flyback framework has first base island and second base island in the PDFN frame, and first base island and second base island are kept apart through the insulating layer; the main control module and the second gallium nitride power tube are arranged in the first base island, and the first gallium nitride power tube is arranged in the second base island; the number of the pins of the PDFN frame is 10; the first to sixth pins are arranged at one side close to the first base island, and the seventh to tenth pins are arranged at one side close to the second base island; the second gallium nitride power tube is positioned above the main control module; the first gallium nitride power tube and the second gallium nitride power tube are horizontally arranged; a first driving signal output end GTH of the main control module is connected with a grid electrode of a first gallium nitride power tube through the internal routing of the chip, and a second driving signal output end GTL is connected with a grid electrode of a second gallium nitride power tube through the internal routing of the chip; and the source electrode of the first gallium nitride power tube is connected with the drain electrode of the second gallium nitride power tube to be used as half-bridge output of the chip.

Description

Half-bridge driving chip structure for active clamping flyback framework
Technical Field
The utility model relates to an integrated circuit technical field especially relates to a half-bridge driver chip structure that is used for active clamping to turn over and swashs framework.
Background
The half-bridge driving circuit is widely applied to an electronic ballast, a Pulse Width Modulation (PWM) motor driving and inverting circuit, and comprises a discrete component driving circuit, a pulse trigger transformer driving circuit and a special integrated chip driving circuit. Among them, discrete component driving has an advantage of low price, but its application is limited due to its poor integration level; the trigger transformer driving has the advantage of convenient realization, but because of the manufacturing error, the two paths of driving signals are easy to distort, and the transformer has large volume and severe heating; the special integrated chip has the advantages of small volume, high reliability, high efficiency and the like.
The half-bridge topology of the power switch device is a common structure of a medium-high power switch power supply, the voltage stress of the primary power switch device of the transformer can be reduced, and in order to reduce the switching loss, a soft switch zero voltage switching-on (ZVS) technology is commonly adopted in the half-bridge topologies such as Active Clamped (ACF) and LLC resonance, the switching frequency can be improved, and the product volume can be reduced.
As a third generation semiconductor material, compared with a charger based on a traditional silicon power device, the gallium nitride fast charging device has the characteristics of smaller product volume, lighter weight, higher efficiency, less heat generation and the like. Therefore, in the aspect of the controller, three mainstream gallium nitride fast charging architectures including flyback (QR), active Clamping (ACF) and resonance (LLC) are mainly covered.
The QR framework covers the application field of low-power quick charging, and the cost performance is high; the ACF framework covers a power section of mainstream quick charging application, and the power density is high; the LLC architecture covers most high power applications with a wide frequency range. Each of which has its own advantages.
In terms of the existing ACF framework, the threshold voltage Vth and the gate-source withstand voltage value of the high-voltage enhanced GaN power device are lower than those of a silicon-based (Si) power device, and the requirement on the precision of the gate-source driving voltage is higher. It is common in the art to have the driver and GaN power devices separate and externally connected by Printed Circuit Board (PCB) wiring. The parasitic inductance of the structure is large, and the gate-source voltage of the GaN power device can generate ringing phenomenon, so that the device is easy to damage.
Some manufacturers have started the development of highly integrated control chips, integrating controllers, drivers, and power transistors. Under the structure, the specific realization of the physical structure of the chip plays an important role in the performance of the chip.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a half-bridge driver chip structure for active clamping flyback framework to form bilateral flat pin-free encapsulation PDFN frame integration host system, first gallium nitride power tube and second gallium nitride power tube of square, reduce the parasitic parameter in the drive loop through rationally distributed physical structure, guarantee host system and gallium nitride power tube's heat dissipation, optimize the pin, make chip peripheral device quantity reduce by a wide margin, promoted power density.
Therefore, the embodiment of the utility model provides a half-bridge driver chip structure for active clamping flyback framework, the chip structure includes: the device comprises a square bilateral flat pin-free packaging PDFN frame, a master control module, a first gallium nitride power tube and a second gallium nitride power tube;
the PDFN frame is internally provided with a first base island and a second base island which are isolated by an insulating layer; the main control module and the second gallium nitride power tube are arranged in the first base island, and the first gallium nitride power tube is arranged in the second base island; the number of the pins of the PDFN frame is 10; the first to sixth pins are on one side close to the first base island, and the seventh to tenth pins are on one side close to the second base island; in the first base island, the second gallium nitride power tube is positioned above the main control module; a first gallium nitride power tube in the second base island and a second gallium nitride power tube in the first base island are horizontally arranged;
the main control module comprises a first driving signal output end GTH and a second driving signal output end GTL; the first driving signal output end GTH is connected with the grid electrode of the first gallium nitride power tube through the internal routing of the chip, and the second driving signal output end GTL is connected with the grid electrode of the second gallium nitride power tube through the internal routing of the chip; and the source electrode of the first gallium nitride power tube is connected with the drain electrode of the second gallium nitride power tube to be used as the half-bridge output of the chip.
Preferably, 10 of the pins respectively include: a first pin high voltage input negative terminal V-, a second pin high voltage input negative terminal V-, third to fifth pin input output I/O, a sixth pin chip power input VCC, a seventh pin high voltage start circuit input HV, an eighth pin high side driver power input VCCH, a ninth pin half-bridge output HB, a tenth pin high voltage input positive terminal V +; the 10 pins are arranged on two sides of the chip in a counterclockwise sequence, wherein the left side is provided with a first pin, a second pin, a third pin and a fourth pin, the sixth pin and the seventh pin are arranged on the right side, and the seventh pin, the fourth pin and the tenth pin are arranged on the right side.
Further preferably, the main control module further includes: the power supply circuit comprises a power supply input end VCC, a high-voltage starting circuit input end HV, a ground end GND, a high-end driver power supply input end VCCH, a half-bridge output end HB and three input and output ends;
the power supply input end VCC of the main control module is connected with the sixth pin of the chip through the internal routing of the chip;
three input and output ends of the main control module are respectively connected with the third pin, the third pin and the fifth pin of the chip through internal routing of the chip;
the input end HV of the high-voltage starting circuit of the main control module is connected with the seventh pin of the chip through the internal routing of the chip;
a ground end GND of the main control module is connected to the first base island through a wire bonding inside the chip and is communicated with the first pin and the second pin of the chip through the first base island;
and the half-bridge output end HB of the master control module is connected to the second base island through a wire bonding inside the chip and is communicated with the ninth pin of the chip through the second base island.
Further preferably, the main control module further includes: the power supply circuit comprises a power supply input end VCC, a high-voltage starting circuit input end HV, a ground end GND, a high-end driver power supply input end VCCH, a half-bridge output end HB and three input and output ends;
the power supply input end VCC of the main control module is connected with the sixth pin of the chip through internal routing of the chip;
three input and output ends of the main control module are respectively connected with the third pin, the second pin and the fifth pin of the chip through internal routing of the chip;
the input end HV of the high-voltage starting circuit of the main control module is connected with the seventh pin of the chip through the internal routing of the chip;
a ground end GND of the main control module is connected to the first base island through a wire bonding inside the chip and is communicated with the first pin and the second pin of the chip through the first base island;
and the half-bridge output end HB of the main control module is connected to the second base island through the internal routing of the chip and is communicated with the ninth pin of the chip through the second base island.
Further preferably, the source of the first gallium nitride power tube and the drain of the second gallium nitride power tube are respectively directed to an insulating layer isolating the first base island and the second base island;
the drain electrode of the first gallium nitride power tube is connected with a tenth pin of the chip through the internal routing of the chip;
the source electrode of the first gallium nitride power tube and the drain electrode of the second gallium nitride power tube are respectively connected to the second base island through routing inside the chip and communicated with the ninth pin of the chip through the second base island;
and the source electrode of the second gallium nitride power tube is connected to the first base island through the internal routing of the chip and is communicated with the first pin and the second pin of the chip through the first base island.
Preferably, the pins of the chip are isolated by the insulating layer.
Preferably, the copper sheet is exposed on the back of the chip corresponding to the positions of the first base island and the second base island.
Preferably, the main control module outputs a driving signal through a first driving signal output terminal GTH and a second driving signal output terminal GTL according to the input signal of the third to fifth pin input/output I/O, so as to drive the first gallium nitride power tube and the second gallium nitride power tube to be alternately turned on and off.
The embodiment of the utility model provides a half-bridge drive chip structure for active clamping flyback framework, with the integrated host system of shape bilateral flat pin-free encapsulation PDFN frame, first gallium nitride power tube and second gallium nitride power tube, reduce the parasitic parameter in the drive loop through reasonable layout physical structure, realize keeping apart with insulating layer separation base island, distribute the pin of low pressure signal in one side, the pin of high pressure signal is distributed in the opposite side, has guaranteed that the physical space of high, low pressure signal keeps apart, realizes optimizing the pin simultaneously; the copper sheet leaks from the back of the base island, so that the back of the chip can be directly welded on a PCB when the chip is applied, the heat dissipation of the main control module and the gallium nitride power tube is ensured, the number of peripheral devices of the chip is greatly reduced, and the power density is improved.
Drawings
Fig. 1 is a schematic structural diagram of a half-bridge driving chip for an active clamping flyback architecture according to the present invention;
fig. 2 is a schematic diagram of a half-bridge driving signal provided by the present invention.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and examples.
The embodiment of the utility model provides a half-bridge driver chip structure for active clamping flyback framework, as shown in fig. 1, include: a square bilateral flat leadless Package (PDFN) frame 3, a main control module 4, a first gallium nitride power tube 5 and a second gallium nitride power tube 6;
the PDFN frame 3 is internally provided with a base island 1 and a base island 2, and the base island 1 and the base island 2 are isolated by an insulating layer 7;
the main control module 4 and the second gallium nitride power tube 6 are arranged in the base island 1, and the first gallium nitride power tube 5 is arranged in the base island 2.
In the active clamp flyback architecture, the number of pins of the chip is preferably 10, and each pin includes: a first pin high voltage input negative terminal V-, a second pin high voltage input negative terminal V-, third to fifth pin input output I/O, a sixth pin chip power input VCC, a seventh pin high voltage start circuit input HV, an eighth pin high side driver power input VCCH, a ninth pin half-bridge output HB, a tenth pin high voltage input positive terminal V +; the 10 pins are arranged on two sides of the chip in a counterclockwise sequence, wherein the left side is provided with a first pin, a second pin, a third pin and a fourth pin, the sixth pin and the seventh pin are arranged on the right side, and the seventh pin, the fourth pin and the tenth pin are arranged on the right side. The chip structure is used in an active clamping flyback framework, and input/output I/O of third to fifth pins can be respectively connected with voltage detection VS, secondary feedback FB and current sampling CS ends of the active clamping flyback.
In the internal structure layout of the chip, a base island 1 is arranged on one side close to first to sixth pins, and a base island 2 is arranged on one side close to seventh to tenth pins; in the base island 1, a second gallium nitride power tube 6 is positioned above the main control module 4; the first gallium nitride power tube 5 in the base island 2 and the second gallium nitride power tube 6 in the base island 1 are horizontally arranged, and the source electrode of the first gallium nitride power tube 5 and the drain electrode of the second gallium nitride power tube 6 respectively face the insulating layer 7 for isolating the base island 1 and the base island 2. The layout structure enables the positions of the device modules to basically correspond to the positions of the peripheral pins connected with the device modules, and the connecting routing between the device modules is also optimal, so that the routing inside the chip is optimized, the routing distance is shortened, and the parasitic parameters inside the chip are reduced.
The modules, devices and routing connection structures inside the chip are as follows:
the main control module 4 includes: the driving circuit comprises a first driving signal output end GTH, a second driving signal output end GTL, a power supply input end VCC, a high-voltage starting circuit input end HV, a grounding end GND, a high-end driver power supply input end VCCH, a half-bridge output end HB and three input and output ends;
the first driving signal output end GTH is connected with the grid electrode of the first gallium nitride power tube 5 through the internal routing of the chip, and the second driving signal output end GTL is connected with the grid electrode of the second gallium nitride power tube 6 through the internal routing of the chip;
the power supply input end VCC is connected with a sixth pin of the chip through a wire bonding inside the chip;
the three input and output ends are respectively connected with the third pin to the fifth pin of the chip through internal routing of the chip;
the input end HV of the high-voltage starting circuit is connected with a seventh pin of the chip through internal routing of the chip;
the ground end GND is connected to the base island 1 through the internal routing of the chip and is communicated with the first pin and the second pin of the chip through the base island 1;
the half-bridge output end HB is connected to the base island 2 through the internal routing of the chip and is communicated with a ninth pin of the chip through the base island 2.
The inside of the drain chip of the first gallium nitride power tube 5 is connected with a tenth pin of the chip by wire bonding;
and the source electrode of the first gallium nitride power tube 5 and the drain electrode of the second gallium nitride power tube are respectively connected to the second base island through routing inside the chip, and are communicated with the ninth pin of the chip through the second base island to be used as half-bridge output of the chip.
Further, the respective pins of the chip are also isolated by the insulating layer 3.
The utility model discloses in, the copper sheet is leaked at the 2 backs in base island 1 and base island, and this chip can be with back lug weld on the PCB board when using, has guaranteed the heat dispersion of chip. Especially the heat dissipation of the main control module 4, the first gallium nitride power tube 5 and the second gallium nitride power tube 6.
In the specific application of the half-bridge driving chip for the active clamping flyback architecture based on the above structure, the main control module 4 may specifically include sub-modules such as a controller, a high-voltage start circuit, a high-side driver, and a low-side driver, the controller outputs a control signal to the driver according to an input signal of an input/output I/O terminal, and the control signal output to the high-side driver and the low-side driver may specifically be a complementary pulse width modulation signal.
The high-side driver and the low-side driver can both contain a level conversion circuit and a driving circuit. The high-side driver drives the first gan power tube 5, the low-side driver drives the second gan power tube 6, the first gan power tube 5 and the second gan power tube 6 alternately turn on and off according to the driving to generate half-bridge driving signals VgH and VgL, and there is a dead time T _ dt in the alternation process, and the half-bridge driving signals are schematically shown in fig. 2.
The embodiment of the utility model provides a half-bridge drive chip structure for active clamping flyback framework, with the integrated host system of shape bilateral flat pin-free encapsulation PDFN frame, first gallium nitride power tube and second gallium nitride power tube, reduce the parasitic parameter in the drive loop through reasonable layout physical structure, realize keeping apart with insulating layer separation base island, distribute the pin of low pressure signal in one side, the pin of high pressure signal is distributed in the opposite side, guaranteed the physical space of high, low pressure signal and keep apart, realize optimizing the pin simultaneously; the copper sheet leaks from the back of the base island, so that the back of the chip can be directly welded on a PCB when the chip is applied, the heat dissipation of the main control module and the gallium nitride power tube is ensured, the number of peripheral devices of the chip is greatly reduced, and the power density is improved.
It should be noted that, the utility model provides a chip architecture can confirm the frame type and the size specifically chooseed for use according to active clamping flyback circuit's practical application environment and system parameter requirement, and the number and the definition of pin position, IO mouth also all can decide according to the practical application demand. The above is only a specific way to realize the implementation, and is not intended to limit the scope of the practical implementation.
The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (7)

1. A half-bridge driver chip structure for an active clamping flyback architecture, the chip structure comprising: the square bilateral flat pin-free packaging PDFN frame, the master control module, the first gallium nitride power tube and the second gallium nitride power tube are arranged in the square bilateral flat pin-free packaging frame;
the PDFN frame is internally provided with a first base island and a second base island which are isolated by an insulating layer; the main control module and the second gallium nitride power tube are arranged in the first base island, and the first gallium nitride power tube is arranged in the second base island; the number of the pins of the PDFN frame is 10; the first to sixth pins are arranged at one side close to the first base island, and the seventh to tenth pins are arranged at one side close to the second base island; in the first base island, the second gallium nitride power tube is positioned above the main control module; a first gallium nitride power tube in the second base island and a second gallium nitride power tube in the first base island are horizontally arranged;
the main control module comprises a first driving signal output end GTH and a second driving signal output end GTL; the first driving signal output end GTH is connected with the grid electrode of the first gallium nitride power tube through the internal routing of the chip, and the second driving signal output end GTL is connected with the grid electrode of the second gallium nitride power tube through the internal routing of the chip; and the source electrode of the first gallium nitride power tube is connected with the drain electrode of the second gallium nitride power tube to be used as the half-bridge output of the chip.
2. The half-bridge driver chip structure of claim 1, wherein 10 of the pins each include: a first pin high-voltage input negative terminal V-, a second pin high-voltage input negative terminal V-, a third pin to a fifth pin input/output I/O, a sixth pin chip power input VCC, a seventh pin high-voltage start circuit input HV, an eighth pin high-side driver power input VCCH, a ninth pin half-bridge output HB, and a tenth pin high-voltage input positive terminal V +; the 10 pins are arranged on two sides of the chip in a counterclockwise sequence, wherein the left side is provided with a first pin, a second pin, a third pin and a fourth pin, the sixth pin and the seventh pin are arranged on the right side, and the seventh pin, the fourth pin and the tenth pin are arranged on the right side.
3. The half-bridge driver chip structure of claim 2, wherein the master module further comprises: the power supply circuit comprises a power supply input end VCC, a high-voltage starting circuit input end HV, a ground end GND, a high-end driver power supply input end VCCH, a half-bridge output end HB and three input and output ends;
the power supply input end VCC of the main control module is connected with the sixth pin of the chip through the internal routing of the chip;
three input and output ends of the main control module are respectively connected with the third pin, the third pin and the fifth pin of the chip through internal routing of the chip;
the input end HV of the high-voltage starting circuit of the main control module is connected with the seventh pin of the chip through the internal routing of the chip;
the ground end GND of the main control module is connected to the first base island through a routing in the chip and is communicated with the first pin and the second pin of the chip through the first base island;
and the half-bridge output end HB of the main control module is connected to the second base island through the internal routing of the chip and is communicated with the ninth pin of the chip through the second base island.
4. The half-bridge driver chip structure of claim 2, wherein the source of the first gallium nitride power transistor and the drain of the second gallium nitride power transistor are respectively directed toward an insulating layer separating the first and second base islands;
the drain electrode of the first gallium nitride power tube is connected with a tenth pin of the chip through routing inside the chip;
the source electrode of the first gallium nitride power tube and the drain electrode of the second gallium nitride power tube are respectively connected to the second base island through routing inside the chip and are communicated with the ninth base pin of the chip through the second base island;
and the source electrode of the second gallium nitride power tube is connected to the first base island through the internal routing of the chip and is communicated with the first pin and the second pin of the chip through the first base island.
5. The half-bridge driver chip structure of claim 2, the pins of the chip being isolated by the insulating layer.
6. The half-bridge driver chip structure of claim 1, wherein the back side of the chip corresponding to the locations of the first and second islands is exposed with copper.
7. The half-bridge driving chip structure of claim 2, wherein the main control module outputs driving signals through a first driving signal output terminal GTH and a second driving signal output terminal GTL according to the input signals of the third to fifth pin input/output I/O, so as to alternately turn on and off the first gallium nitride power transistor and the second gallium nitride power transistor.
CN202221206656.5U 2022-05-18 2022-05-18 Half-bridge driving chip structure for active clamping flyback framework Active CN218647931U (en)

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CN202221206656.5U CN218647931U (en) 2022-05-18 2022-05-18 Half-bridge driving chip structure for active clamping flyback framework

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Application Number Priority Date Filing Date Title
CN202221206656.5U CN218647931U (en) 2022-05-18 2022-05-18 Half-bridge driving chip structure for active clamping flyback framework

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CN218647931U true CN218647931U (en) 2023-03-17

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