CN220041853U - Packaging structure of synchronous rectification control chip - Google Patents
Packaging structure of synchronous rectification control chip Download PDFInfo
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- CN220041853U CN220041853U CN202321666059.5U CN202321666059U CN220041853U CN 220041853 U CN220041853 U CN 220041853U CN 202321666059 U CN202321666059 U CN 202321666059U CN 220041853 U CN220041853 U CN 220041853U
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- base island
- synchronous rectification
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- power mos
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- 230000001360 synchronised effect Effects 0.000 title claims abstract description 60
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims abstract description 26
- 238000007789 sealing Methods 0.000 claims abstract description 22
- 239000000853 adhesive Substances 0.000 claims abstract description 4
- 230000001070 adhesive effect Effects 0.000 claims abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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Abstract
The embodiment of the utility model relates to a packaging structure of a synchronous rectification control chip, wherein the synchronous rectification control chip comprises an input end A and an output end K, and the packaging structure comprises the following components: the synchronous rectification chip, the power MOS tube and the sealing capacitor; the packaging structure is internally provided with a first base island and a second base island, and the two base islands are isolated by an insulating layer; the input end A is led out of the first base island, and the output end K is led out of the second base island; the synchronous rectification chip and the combined sealing capacitor are arranged in the first base island, and the power MOS tube is arranged in the second base island; the voltage source pin VCC and the control power source pin VCCH of the synchronous rectification chip are connected with the first end of the sealing capacitor; the second end of the sealed capacitor is connected with the first base island; the ground pin GND and the power ground pin GNDP of the synchronous rectification chip are connected with the first base island; an output pin K of the synchronous rectification chip is connected with a second base island; the grid electrode of the power MOS tube is connected with the control pin GT of the synchronous rectification chip, the source electrode is connected with the first base island, and the drain electrode is connected with the second base island through conductive adhesive.
Description
Technical Field
The utility model relates to the technical field of integrated circuits, in particular to a packaging structure of a synchronous rectification control chip.
Background
Synchronous rectification chips are a critical device for power conversion systems to improve the efficiency and performance of power conversion. The traditional rectifying circuit uses a diode for rectification, but the diode has larger conduction voltage drop, and meanwhile, the switching speed is slower, so that energy loss and low circuit efficiency are caused.
Synchronous rectification chips achieve efficient conversion of electrical energy by using synchronous switches (typically power MOSFETs) instead of diodes. When the polarity of the input voltage makes the switch conduct, the synchronous rectification control chip transmits electric energy to the load. When the polarity of the input voltage makes the switch turn off, the synchronous rectification control chip turns off the passage to prevent the generation of reverse current.
However, the combination of a separate synchronous rectification chip and power MOSFET also has some drawbacks, in that the connection between them needs to be made by external wiring or connectors, and in that the design complexity increases the risk of reliability. At the same time, the number and layout of pins may also be limited. Meanwhile, the adoption of the design can lead to larger overall size, is not beneficial to the application of limited space, and does not meet the design requirement of miniaturization. Because of the existence of more connecting wires and pins, the circuit is more sensitive to electromagnetic interference, and the external electromagnetic interference can influence signal transmission and system performance. In addition, thermal gradients between multiple chips can be challenging in terms of thermal management for high power application environments, and heat transfer and dissipation can be inefficient, which can also lead to overall system performance degradation.
Disclosure of Invention
The utility model aims to provide a packaging structure of a synchronous rectification control chip, which is formed by combining a sealing capacitor, a power MOS and the synchronous rectification chip, so that pins are optimized to the greatest extent, the requirements of high-power rapid synchronous rectification control can be met, the design area can be saved, and the reliability can be improved.
To this end, an embodiment of the present utility model provides a packaging structure of a synchronous rectification control chip, where the synchronous rectification control chip includes an input end a and an output end K, and an interior of the packaging structure includes: the synchronous rectification chip, the power MOS tube and the sealing capacitor;
the packaging structure is internally provided with a first base island and a second base island, and the first base island and the second base island are isolated through an insulating layer; the input end A is led out of the first base island, and the output end K is led out of the second base island; the synchronous rectification chip and the sealing capacitor are arranged in the first base island, and the power MOS tube is arranged in the second base island;
the voltage source pin VCC and the control power source pin VCCH of the synchronous rectification chip are connected with the first end of the sealing capacitor; the second end of the sealed capacitor is connected with the first base island; the ground pin GND and the power ground pin GNDP of the synchronous rectification chip are connected with the first base island; an output pin K of the synchronous rectification chip is connected with the second base island;
the grid electrode of the power MOS tube is connected with the control pin GT of the synchronous rectification chip, the source electrode of the power MOS tube is connected with the first base island, and the drain electrode of the power MOS tube is connected with the second base island through conductive adhesive.
Preferably, the clock pin TCK of the synchronous rectification chip is empty.
Preferably, the pins are connected with the base island, the sealing capacitor and the grid electrode of the power MOS tube through wire bonding, and the base island is connected with the sealing capacitor, and the source electrode of the power MOS tube is connected with the first base island through wire bonding.
Further preferably, the wire diameter of the wire bond is 1.1mil.
Preferably, copper sheets are exposed on the back surfaces of the chips corresponding to the positions of the first base island and the second base island.
The packaging structure of the synchronous rectification control chip provided by the embodiment of the utility model constructs the synchronous rectification control chip by combining the sealing capacitor, the power MOS and the synchronous rectification chip, optimizes pins to the greatest extent, can meet the requirement of high-power rapid synchronous rectification control, can save the design area and improves the reliability. Through leaking copper sheet with the island back for this chip can be with back direct welding on the PCB board when using, guarantees excellent and balanced heat dispersion.
Drawings
Fig. 1 is a schematic diagram of a package structure of a synchronous rectification control chip provided by the utility model.
Detailed Description
The technical scheme of the utility model is further described in detail through the drawings and the embodiments.
The embodiment of the utility model provides a packaging structure of a synchronous rectification control chip, as shown in fig. 1, comprising:
the synchronous rectification control chip comprises an input end A and an output end K, and the inside of the packaging structure comprises: the synchronous rectification chip 1, the power MOS tube 2 and the sealing capacitor 3; the circuit connection of the sealing capacitor 3 and the PCB provides stable power supply voltage for ensuring the normal operation of the chip for the synchronous rectification control chip.
The packaging structure is internally provided with a first base island 4 and a second base island 5, and the first base island 4 and the second base island 5 are isolated by an insulating layer; the input end A is led out of the first base island 4, and the output end K is led out of the second base island 5; the synchronous rectification chip 1 and the sealing capacitor 3 are arranged in the first base island 4, and the power MOS tube 2 is arranged in the second base island 5.
The voltage source pin VCC and the control power source pin VCCH of the synchronous rectification chip 1 are connected with the first end of the sealing capacitor 3; the second end of the sealed capacitor 3 is connected with the first base island 4; the ground pin GND and the power ground pin GNDP of the synchronous rectification chip 1 are connected with the first base island 4; an output pin K of the synchronous rectification chip 1 is connected with a second base island 5; the clock pin TCK of the synchronous rectification chip is empty.
The grid electrode G of the power MOS tube 2 is connected with the control pin GT of the synchronous rectification chip 1, the source electrode S is connected with the first base island 4, and the drain electrode D (not shown in the figure) is connected with the second base island 5 through conductive adhesive.
The back of the chip corresponding to the positions of the first base island 4 and the second base island 5 is provided with a bare copper sheet. The chip can be directly welded on the back surface of the PCB during application, and excellent and balanced heat dissipation performance is ensured.
The pins are connected with the base island, the sealing capacitor 3 and the grid electrode G of the power MOS tube 2, the base island and the sealing capacitor 3, and the source electrode S of the power MOS tube 2 and the first base island 4 through wire bonding. In a specific example, the Al thickness of the press-bonding pad of the synchronous rectification chip 1 is 1.8 micrometers, and the size of the press-bonding pad is 80 x 80 micrometers 2 The wire diameter of the bond wire was 1.1mil (1 mil=0.001 inch).
In a specific example, the power MOS transistor 2 adopts a 100R25 power MOS or a 45R20 power MOS, and the synchronous rectification chip 1 adopts a DK059B1 type chip.
It should be noted that, the type of the MOS transistor and the type and size of the synchronous rectification chip adopted in the packaging structure provided by the utility model can be determined and selected according to the actual application environment and the system parameter requirement. The above is merely a specific manner that can be implemented, and is not intended to limit the scope of what can be actually implemented.
According to the packaging structure of the synchronous rectification control chip, which is provided by the embodiment of the utility model, the synchronous rectification control chip is constructed by combining the sealing capacitor, the power MOS and the synchronous rectification chip, so that pins are optimized to the greatest extent, the requirements of high-power rapid synchronous rectification control can be met, the design area can be saved, and the reliability can be improved. Through leaking copper sheet with the island back for this chip can be with back direct welding on the PCB board when using, guarantees excellent and balanced heat dispersion.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the utility model, and is not meant to limit the scope of the utility model, but to limit the utility model to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the utility model are intended to be included within the scope of the utility model.
Claims (5)
1. The utility model provides a packaging structure of synchronous rectification control chip, its characterized in that, synchronous rectification control chip includes input A and output K, packaging structure's inside includes: the synchronous rectification chip, the power MOS tube and the sealing capacitor;
the packaging structure is internally provided with a first base island and a second base island, and the first base island and the second base island are isolated through an insulating layer; the input end A is led out of the first base island, and the output end K is led out of the second base island; the synchronous rectification chip and the sealing capacitor are arranged in the first base island, and the power MOS tube is arranged in the second base island;
the voltage source pin VCC and the control power source pin VCCH of the synchronous rectification chip are connected with the first end of the sealing capacitor; the second end of the sealed capacitor is connected with the first base island; the ground pin GND and the power ground pin GNDP of the synchronous rectification chip are connected with the first base island; an output pin K of the synchronous rectification chip is connected with the second base island;
the grid electrode of the power MOS tube is connected with the control pin GT of the synchronous rectification chip, the source electrode of the power MOS tube is connected with the first base island, and the drain electrode of the power MOS tube is connected with the second base island through conductive adhesive.
2. The package structure of claim 1, wherein the clock pin TCK of the synchronous rectification chip is empty.
3. The package structure of claim 1, wherein the pins are connected to the base island, the sealing capacitor, the gate of the power MOS transistor, the base island and the sealing capacitor, and the source of the power MOS transistor and the first base island by wire bonding.
4. The package of claim 3, wherein the wire bond has a wire diameter of 1.1mil.
5. The package structure of claim 1, wherein the back side of the chip corresponding to the first and second islands is exposed to copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321666059.5U CN220041853U (en) | 2023-06-27 | 2023-06-27 | Packaging structure of synchronous rectification control chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321666059.5U CN220041853U (en) | 2023-06-27 | 2023-06-27 | Packaging structure of synchronous rectification control chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220041853U true CN220041853U (en) | 2023-11-17 |
Family
ID=88733405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321666059.5U Active CN220041853U (en) | 2023-06-27 | 2023-06-27 | Packaging structure of synchronous rectification control chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220041853U (en) |
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2023
- 2023-06-27 CN CN202321666059.5U patent/CN220041853U/en active Active
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