CN218497463U - IIC communication level matching circuit - Google Patents
IIC communication level matching circuit Download PDFInfo
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- CN218497463U CN218497463U CN202222051961.8U CN202222051961U CN218497463U CN 218497463 U CN218497463 U CN 218497463U CN 202222051961 U CN202222051961 U CN 202222051961U CN 218497463 U CN218497463 U CN 218497463U
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Abstract
The utility model relates to the technical field of power supply circuits, in particular to an IIC communication level matching circuit, which comprises a CPU power supply VDD and a Device power supply VCC, a bus connected between the CPU power supply VDD and the Device power supply VCC for transmitting electric signals, and a high-speed triode connected to the bus and capable of amplifying the electric signals; the chip resistor component PR3 is connected to the bus and can be matched with the high-speed triode to conduct or cut off an electric signal; the emitter of the high-speed triode is connected with a CPU port, and the collector of the high-speed triode is connected with a Device port; the matching circuit also comprises an electrostatic discharge circuit which can play a role in ESD protection; the matching circuit can adapt to IIC communication between two devices with different levels, so that level matching is achieved between the two devices, the working voltage range is wide, the compatibility is good, the circuit configuration is flexible, and the communication speed is high; the voltages are not influenced with each other, so that the interference of external input can be effectively prevented; the circuit has low overall cost and stable and reliable work.
Description
Technical Field
The utility model relates to a power supply circuit technical field, concretely relates to IIC communication level matching circuit.
Background
IIC (inter integrated circuit), namely I2C, is a bus structure, and with the development of large-scale integrated circuit technology, a singlechip or a microcontroller which is manufactured by integrating a CPU and peripheral circuits such as ROM, RAM, I/0 port, A/D, D/A and the like which are necessary for a working system into a single chip is more and more convenient. At present, many companies in the world produce single-chip microcomputers of various varieties. However, the variety and specification of the single chip microcomputer are still limited, so that only a certain single chip microcomputer can be selected for expansion. There are two methods of expansion: one is a parallel bus and the other is a serial bus. Because the serial bus has few connecting wires and simple structure, all the devices are often connected by wires without special motherboards and sockets. Thus, it is a high performance serial bus. An I2C serial bus typically has two signal lines, one being a bi-directional data line SDA and the other being a clock line SCL. All serial data SDA connected to I2C bus equipment are connected to SDA of the bus, and clock lines SCL of all the equipment are connected to SCL of the bus. The I2C bus is a bus that uses the least number of signal lines among various buses and has functions of auto addressing, multi-master clock synchronization, arbitration, and the like. Therefore, the computer system designed by using the I2C bus is very convenient and flexible, has small volume and is widely applied to various practical applications.
However, in actual use, it is often encountered that the power supply level of each system is not consistent, which may result in poor communication compatibility between the devices, for example, the MCU is at a 3.3V level, the Device is at a 5V level, there is a level difference between the MCU and the Device, and during communication, if there is noise interference on the bus, it is likely to cause communication errors in communication, and may also cause instability of the electric equipment, or cause malfunction.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to an IIC communication level matching circuit for solving the problem that the power supply level of each system is not consistent in the prior art, which may result in poor communication compatibility between the device and the device, and the problem of noise interference on the bus during the communication process.
To achieve the above and other related objects, the present invention provides an IIC communication level matching circuit, comprising:
a CPU power supply VDD and a Device power supply VCC;
a bus connected between the CPU power supply VDD and the Device power supply VCC for transmitting electrical signals;
a high-speed triode which is connected to the bus and can amplify the electric signal; and (c) a second step of,
the chip resistor component PR3 is connected to the bus and can be matched with the high-speed triode to conduct or cut off an electric signal;
the emitter of the high-speed triode is connected with a CPU port, and the collector of the high-speed triode is connected with a Device port;
the matching circuit also comprises an electrostatic discharge circuit which can clamp the bus level to play a role of ESD protection.
In an embodiment of the present invention, the bus includes a clock bus SCL connected in parallel between the CPU power VDD and the Device power VCC for transmitting clock signals and a data bus SDA for transmitting data signals, and the chip resistor PR3 is connected to the clock bus SCL and the data bus SDA simultaneously.
In an embodiment of the present invention, the high-speed triode includes a first high-speed triode Q11 and a second high-speed triode Q26, the base of the first high-speed triode Q11 is connected to the clock bus SCL, and the base of the second high-speed triode Q26 is connected to the data bus SDA.
In an embodiment of the present invention, the CPU port includes a CPU end clock port ISCL and a CPU end data port ISDA, the CPU end clock port ISCL is connected to the emitter of the first high-speed triode Q11, and the CPU end data port ISDA is connected to the emitter of the second high-speed triode Q26.
In an embodiment of the present invention, the Device port includes a Device port clock port DSCL and a Device port data port DSDA, the Device port clock port DSCL is connected to the collector of the first high-speed triode Q11, and the Device port data port DSDA is connected to the collector of the second high-speed triode Q26.
In an embodiment of the present invention, the first high-speed transistor Q11 and the second high-speed transistor Q26 are NPN transistors, and the switching frequency thereof is 800MHz capable of adapting to the high-speed communication interface.
In an embodiment of the present invention, the electrostatic discharge circuit includes a first electrostatic discharge circuit capable of clamping the clock bus SCL level to perform the ESD protection and a second electrostatic discharge circuit capable of clamping the data bus SDA level to perform the ESD protection.
In an embodiment of the present invention, the first electrostatic discharge circuit and the second electrostatic discharge circuit have the same structure and are composed of a power voltage VCC1, a ground GND, and a rectifying diode Q connected between the power voltage VCC1 and the ground GND.
In an embodiment of the present invention, a first resistor R22 capable of matching the impedance of the clock circuit is connected in series on the clock bus SCL near the Device power VCC; and a second resistor R23 capable of matching the impedance of the data circuit is connected in series on a line of the data bus SDA close to the Device power supply VCC.
As described above, the IIC communication level matching circuit of the present invention has the following advantageous effects:
the utility model provides a IIC communication level matching circuit theory of operation as follows:
when the CPU sends 0, the ISDA of the CPU end data port is 0V, the base of the second high-speed triode Q26 is in saturation conduction to the VDD through the chip resistor component PR3, and therefore the DSDA of the Device end data port is 0V; when the CPU sends 1, the ISDA of the CPU end is 3.3V, the base electrode of the second high-speed triode Q26 is cut off and cut off from the power supply VDD of the CPU through the chip resistor component PR3, so that the DSDA of the Device end is pulled up to 5V from R23, and the purpose of level matching is achieved.
Has the following beneficial effects:
the matching circuit can adapt to IIC communication between two devices with different levels, so that level matching is achieved between the two devices, the working voltage range is wide, the compatibility is good, the circuit configuration is flexible, and the communication speed is high; the voltages are not influenced with each other, so that the interference of external input can be effectively prevented; the circuit has low overall cost and stable and reliable operation.
Drawings
Fig. 1 is a schematic diagram of an IIC communication level matching circuit according to the present invention.
Fig. 2 is an enlarged view of the structure of the electrostatic discharge circuit in the IIC communication level matching circuit according to the present disclosure.
Detailed Description
The following description is provided for illustrative purposes, and other advantages and features of the present invention will become apparent to those skilled in the art from the following detailed description.
Please refer to fig. 1-2. It should be understood that the structure, ratio, size and the like shown in the drawings attached to the present specification are only used for matching with the content disclosed in the specification, so as to be known and read by those skilled in the art, and are not used for limiting the limit conditions that the present invention can be implemented, so that the present invention has no technical essential meaning, and any structure modification, ratio relationship change or size adjustment should still fall within the scope that the technical content disclosed in the present invention can cover without affecting the function that the present invention can produce and the purpose that the present invention can achieve. Meanwhile, the terms such as "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for convenience of description, and are not intended to limit the scope of the present invention, and changes or adjustments of the relative relationship thereof may be made without substantial technical changes, and the present invention is also regarded as the scope of the present invention.
Referring to fig. 1 to 2, the present invention provides an IIC communication level matching circuit, which includes:
a CPU power supply VDD and a Device power supply VCC;
a bus connected between the CPU power supply VDD and the Device power supply VCC for transmitting electrical signals;
a high-speed triode which is connected to the bus and can amplify the electric signal; and the number of the first and second groups,
the chip resistor component PR3 is connected to the bus and can be matched with the high-speed triode to conduct or cut off an electric signal;
the emitter of the high-speed triode is connected with a CPU port, and the collector of the high-speed triode is connected with a Device port;
the matching circuit further comprises an electrostatic discharge circuit capable of clamping a bus level to play an ESD protection role, the electrostatic discharge circuit comprises a first electrostatic discharge circuit a1 capable of clamping a clock bus SCL level to play an ESD (namely electrostatic discharge) protection role and a second electrostatic discharge circuit a2 capable of clamping a data bus SDA level to play an ESD (namely electrostatic discharge) protection role, and the first electrostatic discharge circuit a1 and the second electrostatic discharge circuit a2 are of the same structure and are formed by a power supply voltage VCC1, a grounding GND and a rectifier diode Q connected between the power supply voltage VCC1 and the grounding GND in series.
The bus comprises a clock bus SCL and a data bus SDA, wherein the clock bus SCL is connected between a CPU power supply VDD and a Device power supply VCC in parallel and used for transmitting clock signals, the data bus SDA is used for transmitting data signals, and the chip resistor component PR3 is connected with the clock bus SCL and the data bus SDA at the same time.
The high-speed triodes comprise a first high-speed triode Q11 and a second high-speed triode Q26, wherein the base electrode of the first high-speed triode Q11 is connected to the clock bus SCL, and the base electrode of the second high-speed triode Q26 is connected to the data bus SDA.
The CPU port comprises a CPU end clock port ISCL and a CPU end data port ISDA, the CPU end clock port ISCL is connected to the emitter of the first high-speed triode Q11, and the CPU end data port ISDA is connected to the emitter of the second high-speed triode Q26.
The Device port comprises a Device end clock port DSCL and a Device end data port DSDA, the Device end clock port DSCL is connected to a collector electrode of the first high-speed triode Q11, and the Device end data port DSDA is connected to a collector electrode of the second high-speed triode Q26.
The first high-speed triode Q11 and the second high-speed triode Q26 are both NPN type triodes, and the switching frequency thereof is 800MHz that can adapt to a high-speed communication interface.
A first resistor R22 capable of matching the impedance of a clock circuit is connected in series on a line of the clock bus SCL close to a Device power supply VCC; a second resistor R23 capable of matching the impedance of the data circuit is connected in series on a line of the data bus SDA close to the Device power supply VCC, because the impedance of a signal source is very low, the impedance is not matched with that of a signal line, and after the second resistor is connected in series, the matching condition can be improved, so that reflection is reduced, oscillation is avoided, and the like.
The utility model provides a IIC communication level matching circuit theory of operation as follows:
when the CPU sends 0, the data port ISDA of the CPU end is 0V, the base electrode of the second high-speed triode Q26 is in saturated conduction to the power supply VDD of the CPU through the chip resistor component PR3, and therefore the data port DSDA of the Device end is 0V; when the CPU sends 1, the ISDA of the CPU end is 3.3V, the base electrode of the second high-speed triode Q26 is cut off and cut off from the power supply VDD of the CPU through the chip resistor component PR3, so that the DSDA of the Device end is pulled up to 5V from R23, and the purpose of level matching is achieved.
To sum up, the utility model provides a matching circuit can adapt to the IIC communication between two equipment different levels, makes reach the level matching between the two, and its working voltage range is wide, and is compatible good, and circuit configuration is nimble, and communication rate is high; the voltages are not influenced mutually, so that the interference of external input can be effectively prevented; the circuit has low overall cost and stable and reliable work. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. An IIC communication level matching circuit, the matching circuit comprising:
a CPU power supply VDD and a Device power supply VCC;
a bus connected between the CPU power supply VDD and the Device power supply VCC for transmitting electrical signals;
a high-speed triode which is connected to the bus and can amplify the electric signal; and the number of the first and second groups,
the chip resistor component PR3 is connected to the bus and can be matched with the high-speed triode to conduct or cut off an electric signal;
the emitter of the high-speed triode is connected with a CPU port, and the collector of the high-speed triode is connected with a Device port;
the matching circuit also comprises an electrostatic discharge circuit which can clamp the bus level to play a role of ESD protection.
2. The IIC communication level matching circuit of claim 1, wherein: the bus comprises a clock bus SCL and a data bus SDA, wherein the clock bus SCL is connected between a CPU power supply VDD and a Device power supply VCC in parallel and used for transmitting clock signals, the data bus SDA is used for transmitting data signals, and the chip resistor component PR3 is connected with the clock bus SCL and the data bus SDA at the same time.
3. The IIC communication level matching circuit of claim 2, wherein: the high-speed triodes comprise a first high-speed triode Q11 and a second high-speed triode Q26, wherein the base electrode of the first high-speed triode Q11 is connected to the clock bus SCL, and the base electrode of the second high-speed triode Q26 is connected to the data bus SDA.
4. The IIC communication level matching circuit of claim 3, wherein: the CPU port comprises a CPU end clock port ISCL and a CPU end data port ISDA, the CPU end clock port ISCL is connected to the emitter of the first high-speed triode Q11, and the CPU end data port ISDA is connected to the emitter of the second high-speed triode Q26.
5. The IIC communication level matching circuit of claim 3, wherein: the Device port comprises a Device end clock port DSCL and a Device end data port DSDA, the Device end clock port DSCL is connected to a collector electrode of the first high-speed triode Q11, and the Device end data port DSDA is connected to a collector electrode of the second high-speed triode Q26.
6. The IIC communication level matching circuit of claim 3, wherein: the first high-speed triode Q11 and the second high-speed triode Q26 are both NPN type triodes, and the switching frequency of the NPN type triodes is 800MHz capable of adapting to a high-speed communication interface.
7. The IIC communication level matching circuit of claim 2, wherein: the static electricity discharge circuit comprises a first static electricity discharge circuit capable of clamping the level of a clock bus SCL for ESD protection and a second static electricity discharge circuit capable of clamping the level of a data bus SDA for ESD protection.
8. The IIC communication level matching circuit of claim 7, wherein: the first electrostatic discharge circuit and the second electrostatic discharge circuit are of the same structure and are composed of a power supply voltage VCC1, a grounding GND and a rectifier diode Q connected in series between the power supply voltage VCC1 and the grounding GND.
9. The IIC communication level matching circuit of claim 8, wherein: a first resistor R22 capable of matching the impedance of a clock circuit is connected in series on a line of the clock bus SCL close to a Device power supply VCC; and a second resistor R23 capable of matching the impedance of the data circuit is connected in series on a line of the data bus SDA close to the Device power supply VCC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222051961.8U CN218497463U (en) | 2022-08-04 | 2022-08-04 | IIC communication level matching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222051961.8U CN218497463U (en) | 2022-08-04 | 2022-08-04 | IIC communication level matching circuit |
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| Publication Number | Publication Date |
|---|---|
| CN218497463U true CN218497463U (en) | 2023-02-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202222051961.8U Active CN218497463U (en) | 2022-08-04 | 2022-08-04 | IIC communication level matching circuit |
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