CN211830742U - Communication control circuit and electronic equipment - Google Patents
Communication control circuit and electronic equipment Download PDFInfo
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- CN211830742U CN211830742U CN202020441621.4U CN202020441621U CN211830742U CN 211830742 U CN211830742 U CN 211830742U CN 202020441621 U CN202020441621 U CN 202020441621U CN 211830742 U CN211830742 U CN 211830742U
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Abstract
The utility model discloses a communication control circuit and electronic equipment, this communication control circuit includes: the signal modulation circuit comprises a first signal input end, a gating signal input end and an output end, and is used for modulating a first communication signal accessed by the first signal input end and a gating signal accessed by the gating signal input end and then outputting a modulation signal; the integrated chip comprises a first input/output end and a second input/output end, the first input/output end is connected with the output end of the signal modulation circuit, and the second input/output end of the integrated chip is used for accessing a second communication signal. The utility model discloses be favorable to simplifying integrated chip's encapsulation, reduce integrated chip's cost of manufacture.
Description
Technical Field
The utility model relates to an integrated circuit technical field, in particular to communication control circuit and electronic equipment.
Background
In the existing communication of an integrated chip, three signal lines are usually needed to realize the communication, so that three I/O ports are needed to be arranged on the integrated chip to access three signals. The more pins of the integrated chip, the more complex the process, and the great design pressure is brought to the circuit wiring and the like, and the more pins, the smaller the packaging application range, so the packaging cost is higher.
SUMMERY OF THE UTILITY MODEL
The main objective of the present invention is to provide a communication control circuit and an electronic device, which are aimed at simplifying the packaging of an integrated chip.
In order to achieve the above object, the utility model provides a communication control circuit, communication control circuit includes:
the signal modulation circuit comprises a first signal input end, a gating signal input end and an output end, and is used for modulating a first communication signal accessed by the first signal input end and a gating signal accessed by the gating signal input end and then outputting a modulation signal;
the integrated chip comprises a first input/output end and a second input/output end, the first input/output end is connected with the output end of the signal modulation circuit, and the second input/output end of the integrated chip is used for accessing a second communication signal.
Optionally, a signal demodulation circuit is integrated in the integrated chip, and an input end of the signal demodulation circuit is connected to the first input/output end;
the signal demodulation circuit is used for demodulating the accessed modulation signal into a chip strobe signal and an internal communication signal.
Optionally, the signal demodulation circuit includes a first signal processing circuit and a second signal processing circuit, one input ends of the first signal processing circuit and the second signal processing circuit are respectively connected to the first input/output end, and an output end of the first signal processing circuit is connected to another input end of the second signal processing circuit.
Optionally, the signal modulation circuit includes a first resistor and a first diode, an anode of the first diode is a gating signal input end of the signal modulation circuit, and a first end of the first resistor is a first signal input end of the signal modulation circuit; and the second end of the first resistor and the common end of the cathode of the first diode are output ends of the signal modulation circuit.
Optionally, the signal modulation circuit further includes a first pull-up resistor, a first end of the first resistor is connected to an anode of the first diode, and a second end of the first pull-up resistor is connected to a first dc power supply.
Optionally, a second resistor is further integrated in the integrated chip, a first end of the second resistor is connected to the first input/output end, and a second end of the second resistor is grounded.
Optionally, the signal modulation circuit includes a third resistor and a second diode, an anode of the second diode is a gating signal input terminal of the signal modulation circuit, and a first end of the third resistor is a first signal input terminal of the signal modulation circuit; and the common end of the second end of the third resistor and the cathode of the second diode is the output end of the signal modulation circuit.
Optionally, the signal modulation circuit further includes a first pull-down resistor, a first end of the first pull-down resistor is connected to a cathode of the first diode, and a second end of the first pull-down resistor is grounded.
Optionally, a fourth resistor is further integrated in the integrated chip, a first end of the fourth resistor is connected to the first input/output end, and the fourth resistor is connected to a power supply end of the integrated chip.
The utility model also provides an electronic equipment, electronic equipment includes as above communication control circuit.
The utility model discloses communication control circuit is through setting up signal modulation circuit to output modulation signal to integrated chip after modulating the gating signal that first communication signal that first signal input part inserts and gating signal input part insert, integrated chip's first input/output end is connected with signal modulation circuit's output, and integrated chip's second input/output end inserts second communication signal. The utility model discloses integrated chip adopts a pin to realize the multiplexing input of two way signals, only needs two chip pins to realize the input of three routes signal, can practice thrift integrated chip's pin. The utility model discloses be favorable to simplifying integrated chip's encapsulation, reduce integrated chip's cost of manufacture.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic diagram of functional modules of an embodiment of the communication control circuit of the present invention;
fig. 2 is a schematic diagram of a functional module of another embodiment of the communication control circuit of the present invention;
fig. 3 is a schematic circuit diagram of a communication control circuit according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of another embodiment of the communication control circuit of the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 10 | Signal modulation circuit | I/O2 | Second inputInput/ |
| 20 | Integrated chip | R1～R4 | First to |
| 21 | Signal demodulation circuit | R11 | First pull-up resistor |
| 211 | First signal processing circuit | R12 | First pull-down resistor |
| 212 | Second signal processing circuit | D1 | First diode |
| I/O1 | First input/output terminal | D2 | Second diode |
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that, if directional indications (such as upper, lower, left, right, front and rear … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description relating to "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a communication control circuit is applicable to in the electronic equipment who is provided with integrated chip. For example, the electronic device is provided with an MCU, a plurality of memories and a processor, the MCU is respectively connected to the integrated chips, and when the electronic device works, the corresponding integrated chips are triggered to work by a strobe signal. Usually, when a chip communicates with another chip, three signal lines, that is, a strobe signal (chip select signal), a clock signal line, and a data signal line, need to be provided. Therefore, at least three chip pins need to be provided on the MCU and each integrated chip to realize the communication between the chips. However, when designing a chip, one more IC pin requires a chip package with more than 1 pin, which greatly increases the package cost of the IC, for example: exactly 25 pins on the IC design: 3 communication control pins and 22 other functional pins; at this time, only a general package of 28 pins can be selected, and if only 2 control signals are used, a general package of 24 pins can be used. Because 24-pin packages are more widely used than 28-pin packages, the cost and cost of the package is much lower. And the chip process can be reduced.
Referring to fig. 1 to 4, in an embodiment of the present invention, a novel communication control circuit is provided, which aims to implement signal transmission on three signal lines by using two pins. The communication control circuit includes:
the signal modulation circuit 10 comprises a first signal input end, a gating signal input end and an output end, and the signal modulation circuit 10 is used for modulating a first communication signal accessed by the first signal input end and a gating signal accessed by the gating signal input end and then outputting a modulation signal;
an integrated chip 20, the integrated chip 20 includes a first input/output port I/O1 and a second input/output port, the first input/output port I/O1 is connected to the output port of the signal modulation circuit 10, and the second input/output port I/O2 of the integrated chip 20 is used for accessing a second communication signal.
In this embodiment, the first signal input terminal of the signal modulation circuit 10 and the second input/output terminal I/O2 of the integrated chip 20 are used for inputting a clock signal and a data signal, respectively, where the clock signal is accessible to the first signal input terminal of the signal modulation circuit 10, and the data signal is input to the second input/output terminal I/O2. Alternatively, the first signal input terminal of the signal modulation circuit 10 may receive a data signal, and the second input/output terminal I/O2 receives a clock signal. In this embodiment, the first communication signal is denoted as "signal a", and the second communication signal accessed by the second input/output terminal I/O2 is denoted as "signal B". The signal modulation circuit 10 modulates the strobe signal and the "signal a" and outputs a modulated signal to the first input/output I/O1 of the integrated chip 20. Modulated by level into a signal and sent to the inside of the integrated chip 20 through an IC pin.
It is understood that the strobe signal may be either the high-level trigger integrated chip 20 or the low-level trigger integrated chip 20. Specifically, when the integrated chip 20 is triggered at a high level, in a non-gated state, a signal accessed by the gated signal input terminal of the signal modulation circuit 10 is at a low level, and at this time, the signal modulation circuit 10 does not perform modulation no matter whether a signal is input at the first signal input terminal. In the gating state, the signal accessed by the gating signal input terminal of the signal modulation circuit 10 is at a high level, and the signal modulation circuit 10 modulates the high-level or low-level communication signal input by the first signal input terminal and the high-level gating signal and outputs the modulated signal to the integrated chip 20. When the integrated chip 20 is triggered at a low level, in a non-gated state, a signal accessed by the gated signal input end of the signal modulation circuit 10 is at a high level, and at this time, the signal modulation circuit 10 does not perform modulation no matter whether a signal is input at the first signal input end. In the gating state, the signal accessed by the gating signal input terminal of the signal modulation circuit 10 is the low level signal modulation circuit 10, and then the high level or low level communication signal input by the first signal input terminal and the high level gating signal are modulated and output to the integrated chip 20.
In the integrated chip 20, the integrated chip 20 may demodulate the modulated signal and resolve and identify the "signal a" and the strobe signal. When the strobe signal is not accessed, the integrated chip 20 is in a sleep state, and when the strobe signal is accessed, the integrated chip 20 realizes data transmission according to the decomposed a signal and the B signal accessed by the second input/output terminal I/O2, thereby realizing the function of the integrated chip 20.
The utility model discloses communication control circuit is through setting up signal modulation circuit 10 to output modulation signal to integrated chip 20 after modulating the first communication signal that first signal input part inserts and the gating signal that gating signal input part inserts, integrated chip 20's first input/output IO 1 is connected with signal modulation circuit 10's output, and integrated chip 20's second input/output IO 2 inserts second communication signal. The utility model discloses integrated chip 20 adopts a pin to realize the multiplexing input of two way signals, only needs two chip pins to realize the input of three routes signal, can practice thrift integrated chip 20's pin. The utility model discloses be favorable to simplifying integrated chip 20's encapsulation, reduce integrated chip 20's cost of manufacture.
Referring to fig. 1 to 4, in an embodiment, a signal demodulation circuit 21 is integrated in the integrated chip 20, and an input terminal of the signal demodulation circuit 21 is connected to the first input/output terminal I/O1;
the signal demodulation circuit 21 is configured to demodulate the accessed modulation signal into a chip strobe signal and an internal communication signal.
In this embodiment, the signal demodulation circuit 21 is integrated in the IC, and by level comparison, the incoming signal is decomposed into the "gating signal" and the "signal a" again, so that the three communication control line signals of the IC are changed into signals that can be input through two IC pins, and the timing sequence of the three communication control lines is compatible with the original timing sequence. Therefore, by adding peripheral devices with limited cost, the chip packaging cost is greatly reduced, and the compatibility with the original communication control time sequence can be kept.
Further, in the above embodiment, the signal demodulation circuit 21 includes the first signal processing circuit 211 and the second signal processing circuit 212, one input terminals of the first signal processing circuit 211 and the second signal processing circuit 212 are respectively connected to the first input/output terminal I/O1, and an output terminal of the first signal processing circuit 211 is connected to another input terminal of the second signal processing circuit 212.
In this embodiment, the integrated chip 20 may be a microprocessor such as a single chip, a DSP, an FPGA, or a functional chip such as a memory. Those skilled in the art can integrate some hardware circuits and software programs or algorithms in the integrated chip 20, connect various parts of the whole electronic device by using various interfaces and lines, perform various functions of the electronic device and process data by running or executing the software programs and/or modules in the integrated chip 20 and calling data in the integrated chip 20, thereby performing overall monitoring of the electronic device or realizing various functions of the electronic device. The first signal processing circuit 211 and the second signal processing circuit 212 are integrated in the integrated chip 20, and in a specific embodiment, may be implemented by a hardware circuit such as a comparator. When the levels of the gating signal and the signal a are input or not input, the levels of the gating signal and the signal a are different from each other on the modulated signal output by the signal modulation circuit 10, and a "demodulation threshold 1" and a "demodulation threshold 2" are reasonably configured inside the chip, wherein the first signal processing circuit 211 is configured to trigger the second signal processing circuit 212 to operate according to whether the modulated signal meets the condition of the demodulation threshold 1. If so, the second signal processing circuit 212 is triggered, otherwise, the second signal processing circuit 212 does not work. The second signal processing circuit 212, after triggering, compares the modulated signal with the demodulation threshold 2 to identify whether the accessed signal a is high or low.
The present embodiment restores by comparing the level of the first input/output terminal I/O1: "internal strobe signal", "internal signal a". In the embodiment of the integrated chip 20 low-level gating, it is recognized that: when "the first input/output terminal I/O1 level" > "the demodulation threshold 1", the integrated chip 20 performs internal processing: "internal strobe signal": high (VDD), not gated on. "internal signal a": at this time, the chip interface does not work, and the fact that the signal A is does not need to be concerned. Recognizing that: when the "first input/output terminal I/O1 level" < "demodulation threshold 1", the internal processing at this time: "internal strobe signal": low level (GND), gating "internal signal a": when "first input/output terminal I/O1 level" > "demodulation threshold 2", the "internal signal a" is high level; when the "first input/output terminal I/O1 level" < ═ demodulation threshold 2 ", the" internal signal a "is at a low level.
In the embodiment of the integrated chip 20 high-level gating, it is recognized that: when the "first input/output terminal I/O1 level" < ═ demodulation threshold 1 ", the integrated chip 20 performs internal processing: "internal strobe signal": low (GND), not gated. "internal signal a": at this time, the chip interface does not work, and the fact that the signal A is does not need to be concerned. Recognizing that: "first input/output terminal I/O1 level" > "demodulation threshold 1", internal processing at this time: "internal strobe signal": high (VDD), gating "internal signal a": when "first input/output terminal I/O1 level" > "demodulation threshold 2", the "internal signal a" is high level; when the "first input/output terminal I/O1 level" < ═ demodulation threshold 2 ", the" internal signal a "is at a low level.
Referring to fig. 1 to 4, in an embodiment, the signal modulation circuit 10 includes a first resistor R1 and a first diode D1, an anode of the first diode D1 is a gate signal input terminal of the signal modulation circuit 10, and a first terminal of the first resistor R1 is a first signal input terminal of the signal modulation circuit 10; the second end of the first resistor R1 and the common end of the cathode of the first diode D1 are the output end of the signal modulation circuit 10.
In this embodiment, the integrated chip 20 is gated at a low level, that is, when the integrated chip 20 does not operate, the gating signal is at a high level, and when the integrated chip 20 is triggered to operate, the gating signal is at a low level. The anode of the first diode D1 is also connected to the first dc power supply VDD via a resistor R11. The resistance of the first resistor R1 is set to be large, and the driving capability is much smaller than that of the first diode D1. Therefore, in the non-gated state, the gate signal is high (VDD), the anode of the first diode D1 is turned on, and the voltage of the first input/output terminal I/O1 is VDD-Von; where Von is the turn-on voltage drop of the first diode D1. The I/O interface of the chip does not work in a gating mode, and does not need to be concerned about whether the signal A is accessed or not. In the gating state, the gating signal is low level, the external is connected to the low level signal, the first diode D1 is cut off, and the voltage of the first input/output terminal I/O1 is determined by the signal a.
Referring to fig. 1 to 4, in an embodiment, a second resistor R2 is further integrated in the integrated chip 20, a first terminal of the second resistor R2 is connected to the first input/output terminal I/O1, and a second terminal of the second resistor R2 is grounded.
In this example, when the integrated chip 20 is turned on, the voltage at the point of the first input/output terminal I/O1 is determined by the "signal a", the voltage of the "signal a" is divided by the first resistor R1 and the second resistor R2, when the "signal a" is at a high level, the voltage at the point of the first input/output terminal I/O1 is VDD × R2/(R1+ R2), and when the "signal a" is at a low level, the point of the first input/output terminal I/O1 is at a low level GND. The voltage at the point of the first input/output terminal I/O1 satisfies the following relationship, "VDD-Von" > "VDD × R2/(R1+ R2)".
In an embodiment, the signal modulation circuit 10 further includes a first pull-up resistor R11, a first end of the first resistor R1 is connected to the anode of the first diode D1, and a second end of the first pull-up resistor R11 is connected to a first dc power supply VDD. The first pull-up resistor R11 is a resistor with a small resistance, and provides a pull-up function in the absence of a strong pull-up of the "strobe signal". Of course, the R11 resistor is not required when the "gate signal" itself has strong pull-up driving capability.
Referring to fig. 1 to 4, in an embodiment, the signal modulation circuit 10 includes a third resistor R3 and a second diode D2, an anode of the second diode D2 is a gate signal input terminal of the signal modulation circuit 10, and a first terminal of the third resistor R3 is a first signal input terminal of the signal modulation circuit 10; the common terminal of the second terminal of the third resistor R3 and the cathode of the second diode D2 is the output terminal of the signal modulation circuit 10.
In this embodiment, the integrated chip 20 is gated at a high level, that is, when the integrated chip 20 does not operate, the gating signal is at a low level, and when the integrated chip 20 is triggered to operate, the gating signal is at a high level. The cathode of the second diode D2 is also connected to a second ground line through a resistor R12. The resistance of the third resistor R3 is set to be large, and the driving capability is much smaller than that of the second diode D2. Therefore, in the non-gated state, the gate signal is at low level (GND), the cathode of the second diode D2 is grounded and turned on, and the voltage of the first input/output terminal I/O1 is GND + Von; where Von is the turn-on voltage drop of the first diode D1. The I/O interface of the chip does not work in a gating mode, and does not need to be concerned about whether the signal A is accessed or not. In the gating state, the gating signal is at a high level, the high level signal is externally connected, and the first diode D1 is cut off. At this time, the voltage of the first input/output terminal I/O1 is determined by the signal a.
Referring to fig. 1 to 4, in an embodiment, a fourth resistor R4 is further integrated in the integrated chip 20, a first terminal of the fourth resistor R4 is connected to the first input/output terminal I/O1, and the fourth resistor R4 is connected to a power supply terminal of the integrated chip 20.
In this example, when the integrated chip 20 is turned on, the voltage at the point of the first input/output terminal I/O1 is determined by "signal a", the voltage of the "signal a" is divided by the third resistor R3 and the fourth resistor R4, when the "signal a" is at a high level, the voltage at the point of the first input/output terminal I/O1 is at a low level GND, and when the "signal a" is at a low level, the point of the first input/output terminal I/O1 is VDD × R3/(R3+ R4).
Referring to fig. 1 to 4, in an embodiment, the signal modulation circuit 10 further includes a first pull-down resistor R12, a first end of the first pull-down resistor R12 is connected to the cathode of the first diode D1, and a second end of the first pull-down resistor R12 is grounded. In this embodiment, the first pull-down resistor R12 is a resistor with a small resistance, and provides a pull-down function when the "strobe signal" is not strongly pulled down. Of course, the R12 resistor is not required when the "gate signal" itself has strong pull-down driving capability.
The utility model also provides an electronic equipment, electronic equipment includes as above communication control circuit. The detailed structure of the communication control circuit can refer to the above embodiments, and is not described herein; it can be understood that, because the utility model discloses used above-mentioned communication control circuit among the electronic equipment, consequently, the utility model discloses electronic equipment's embodiment includes all technical scheme of the whole embodiments of above-mentioned communication control circuit, and the technological effect that reaches is also identical, no longer gives unnecessary details here.
The above is only the optional embodiment of the present invention, and not therefore the limit of the patent scope of the present invention, all of which are in the concept of the present invention, the equivalent structure transformation of the content of the specification and the drawings is utilized, or the direct/indirect application is included in other related technical fields in the patent protection scope of the present invention.
Claims (10)
1. A communication control circuit, comprising:
the signal modulation circuit comprises a first signal input end, a gating signal input end and an output end, and is used for modulating a first communication signal accessed by the first signal input end and a gating signal accessed by the gating signal input end and then outputting a modulation signal;
the integrated chip comprises a first input/output end and a second input/output end, the first input/output end is connected with the output end of the signal modulation circuit, and the second input/output end of the integrated chip is used for accessing a second communication signal.
2. The communication control circuit according to claim 1, wherein a signal demodulation circuit is integrated in the integrated chip, and an input terminal of the signal demodulation circuit is connected to the first input/output terminal;
the signal demodulation circuit is used for demodulating the accessed modulation signal into a chip strobe signal and an internal communication signal.
3. The communication control circuit according to claim 2, wherein the signal demodulation circuit includes a first signal processing circuit and a second signal processing circuit, one input terminals of the first signal processing circuit and the second signal processing circuit are respectively connected to the first input/output terminal, and an output terminal of the first signal processing circuit is connected to another input terminal of the second signal processing circuit.
4. The communication control circuit according to any one of claims 1 to 3, wherein the signal modulation circuit comprises a first resistor and a first diode, an anode of the first diode is a gating signal input terminal of the signal modulation circuit, and a first terminal of the first resistor is a first signal input terminal of the signal modulation circuit; and the second end of the first resistor and the common end of the cathode of the first diode are output ends of the signal modulation circuit.
5. The communication control circuit of claim 4, wherein the signal modulation circuit further comprises a first pull-up resistor, a first terminal of the first resistor is connected to the anode of the first diode, and a second terminal of the first pull-up resistor is connected to a first DC power supply.
6. The communication control circuit of claim 4, wherein a second resistor is further integrated into the integrated chip, a first terminal of the second resistor is connected to the first input/output terminal, and a second terminal of the second resistor is connected to ground.
7. The communication control circuit according to claim 4, wherein the signal modulation circuit comprises a third resistor and a second diode, an anode of the second diode is a gating signal input terminal of the signal modulation circuit, and a first terminal of the third resistor is a first signal input terminal of the signal modulation circuit; and the common end of the second end of the third resistor and the cathode of the second diode is the output end of the signal modulation circuit.
8. The communication control circuit of claim 7, wherein the signal modulation circuit further comprises a first pull-down resistor, a first terminal of the first pull-down resistor is connected to the cathode of the first diode, and a second terminal of the first pull-down resistor is connected to ground.
9. The communication control circuit according to claim 7, wherein a fourth resistor is further integrated into the integrated chip, a first terminal of the fourth resistor is connected to the first input/output terminal, and the fourth resistor is connected to a power supply terminal of the integrated chip.
10. An electronic device, characterized in that the electronic device comprises a communication control circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020441621.4U CN211830742U (en) | 2020-03-30 | 2020-03-30 | Communication control circuit and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020441621.4U CN211830742U (en) | 2020-03-30 | 2020-03-30 | Communication control circuit and electronic equipment |
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| CN211830742U true CN211830742U (en) | 2020-10-30 |
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| CN202020441621.4U Active CN211830742U (en) | 2020-03-30 | 2020-03-30 | Communication control circuit and electronic equipment |
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Effective date of registration: 20240409 Address after: 410000 Room 201, building C12, Jinrong Wangcheng science and Technology Industrial Park, No. 858, Purui West Road, Wangcheng economic and Technological Development Zone, Changsha City, Hunan Province Patentee after: Hunan xinyide Technology Co.,Ltd. Country or region after: China Address before: 518000 a412, 4th floor, block a, Shenzhen famous industrial products exhibition and procurement center, Baoyuan Road, Xixiang street, Bao'an District, Shenzhen, Guangdong Patentee before: SHENZHEN SOLIDIC TECHNOLOGY CO.,LTD. Country or region before: China |