CN210327615U - Communication circuit - Google Patents
Communication circuit Download PDFInfo
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- CN210327615U CN210327615U CN201921181679.3U CN201921181679U CN210327615U CN 210327615 U CN210327615 U CN 210327615U CN 201921181679 U CN201921181679 U CN 201921181679U CN 210327615 U CN210327615 U CN 210327615U
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- 238000004891 communication Methods 0.000 title claims abstract description 164
- 230000001629 suppression Effects 0.000 claims description 4
- 230000001052 transient effect Effects 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
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Abstract
The utility model discloses a communication circuit relates to the communication field, including control chip, control chip includes UART unit and a plurality of IO the control unit, communication circuit includes a plurality of communication units, an IO the control unit is connected to every communication unit, control chip passes through the communication state of IO the control communication unit, a plurality of communication units are connected with the UART unit simultaneously, control chip sends data or receives communication bus data to communication bus through UART unit and communication unit; the communication circuit comprises a single communication state and a plurality of communication states, wherein in the single communication state, only one communication unit is in the communication state, and the communication unit is in the disabled state; in a plurality of communication states, the control chip adopts a polling mode, the communication units are in the communication state in sequence, and other communication units which are not in the communication state are in the forbidden state. The utility model discloses when not increasing serial ports extension chip, be connected and communicate with a plurality of communication unit simultaneously.
Description
[ technical field ] A method for producing a semiconductor device
The utility model relates to the field of communication, concretely relates to communication circuit.
[ background of the invention ]
In the prior art, in a control chip, a UART unit cannot mount a plurality of communication chips at the same time without adopting a serial port extension chip, and can only be connected with one communication chip, and one communication chip can only be connected with one device. Due to the fact that the number of the UART units of the control chip is limited, the driving capacity of the control chip to the equipment is reduced.
[ Utility model ] content
In order to solve the technical problem, the utility model provides a communication circuit is connected and communicates with a plurality of communication unit simultaneously when not increasing serial ports extension chip.
In order to achieve the above purpose, the utility model adopts the following technical scheme: a communication circuit comprises a control chip, wherein the control chip comprises a UART unit and a plurality of I/O control units, the communication circuit comprises a plurality of communication units, each communication unit is connected with one I/O control unit, the control chip controls the communication unit connected with the control chip to be in a communication state or a forbidden state through the I/O control unit, the communication units are simultaneously connected with the UART unit, and the control chip sends data to a communication bus or receives communication bus data through the UART unit and the communication units;
the communication circuit comprises a single communication state and a plurality of communication states, wherein in the single communication state, the control chip controls the communication unit connected with the control chip to be in a communication state through one of the I/O control units, and controls the respectively connected communication units to be in a forbidden state through the rest I/O control units; in the plurality of communication states, the control chip makes the communication units connected with the control chip be in the communication state in sequence through the I/O control unit in a polling mode, and other communication units which are not in the communication state are in the forbidden state.
Further, the control chip is provided with a polling interval, in the plurality of communication states, if the communication unit is successfully communicated, the I/O control unit connected with the communication unit successfully communicated puts the communication unit successfully communicated in a disabled state, the next communication unit needing to be communicated is put in a communication state under the control of the I/O control unit connected with the communication unit, if the communication unit fails to successfully communicate within the polling interval, the communication unit is put in a disabled state by the I/O control unit connected with the communication unit, and the next communication unit needing to be communicated is put in a communication state under the control of the I/O control unit connected with the communication unit.
Preferably, the communication unit is an RS485 chip, and the communication bus is an RS485 communication bus.
Furthermore, the communication circuit further comprises an I/O signal interface circuit, the RS485 chip has an enable end, the I/O control unit sends a control signal to the RS485 chip through the I/O signal interface circuit, and the enable end receives the control signal.
Furthermore, the enabling end is including sending the enabling end and receiving the enabling end, I/O the control unit passes through I/O signal interface circuit way send enabling end and receiving the enabling end and send control signal, send enabling end with when receiving the enabling end and being the high level, the RS485 chip is in communication state and sends data to RS485 communication bus, send enabling end with when receiving the enabling end and being the low level, the RS485 chip is in communication state and receives data from RS485 communication bus, send enabling end be the low level, when receiving enabling end is the high level, the RS485 chip is in forbidden state.
Furthermore, the I/O signal interface circuit includes two triodes, the base stages of the two triodes are connected to the control chip, the emitter is grounded, the collector of one of the triodes is connected to the transmitting enable terminal, and the collector of the other triode is connected to the receiving enable terminal.
Preferably, a transient suppression diode is connected in parallel between two pins connected with the RS485 communication bus of the RS485 chip.
Furthermore, one of two pins of the RS485 chip connected with the RS485 communication bus is connected with a thermistor in series.
Compared with the prior art, the utility model provides a method has following beneficial effect:
the utility model discloses when not increasing serial ports extension chip, only with a UART unit, can realize the data transmission and the data reception of many RS485 buses, and need not increase unnecessary logical unit, realized under the condition that does not increase serial ports extension chip, improve single control chip controlgear's ability. Because the utility model discloses relative prior art does not relate to serial ports extension chip and logic unit, only uses the IO the control unit of control chip itself, consequently, has advantage with low costs, that the circuit is simple. Since the polling mechanism belongs to the prior art, and the I/O control unit controls the RS485 unit to be in the communication state or the disabled state, the implementation of the beneficial effects described in this specification is implemented based on the improvement of the connection structure of the technical solution, and does not involve the improvement in the program.
These features and advantages of the present invention will be disclosed in more detail in the following detailed description and the accompanying drawings. The best mode or means of the present invention will be described in detail with reference to the accompanying drawings, but not limited thereto. In addition, the features, elements and components appearing in each of the following and in the drawings are plural and different symbols or numerals are labeled for convenience of representation, but all represent components of the same or similar construction or function.
[ description of the drawings ]
The present invention will be further explained with reference to the accompanying drawings:
FIG. 1 is a schematic diagram of an embodiment of the present invention;
fig. 2 is a circuit diagram of an RS485 chip in an embodiment of the present invention.
[ detailed description ] embodiments
The technical solutions of the embodiments of the present invention are explained and explained below with reference to the drawings of the embodiments of the present invention, but the embodiments described below are only preferred embodiments of the present invention, and not all embodiments. Based on the embodiments in the embodiment, other embodiments obtained by those skilled in the art without any creative work belong to the protection scope of the present invention.
Reference in the specification to "one embodiment" or "an example" means that a particular feature, structure or characteristic described in connection with the embodiment itself may be included in at least one embodiment of the patent disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
Example (b):
as shown in fig. 1 and fig. 2, the present embodiment provides a communication circuit, which includes a control chip 1, where the control chip 1 includes a UART unit 11 and a plurality of I/O control units 12, and the communication circuit further includes a plurality of communication units and a plurality of I/O signal interface circuits 13. In this embodiment, the communication unit is an RS485 chip 2. The number of the I/O control units 12 is the same as the number of the plurality of I/O signal interface circuits 13 and the number of the RS485 chips 2. Each RS485 chip 2 is connected to an I/O control unit 12 through an I/O signal interface circuit 13, the control chip 1 controls the RS485 chip 2 connected thereto to be in a communication state or a disabled state through the I/O control unit 12, the plurality of RS485 chips 2 are simultaneously connected to the UART unit 11, the control chip 1 sends data to or receives data from the communication bus through the UART unit 11 and the RS485 chip 2, in this embodiment, the communication bus is an RS485 communication bus, and the RS485 chip 2 communicates with the external device 3 through the RS485 chip 2.
The communication circuit includes a single communication state and a plurality of communication states:
in a single communication state, the control chip 1 controls the RS485 chip 2 connected with the control chip to be in a communication state through one of the I/O control units 12, and controls the RS485 chip 2 connected with the control chip to be in a forbidden state through the other I/O control units 12;
in a plurality of communication states, the control chip 1 makes the RS485 chips 2 connected with it in a communication state in sequence through the I/O control unit 12 in a polling manner, and other RS485 chips 2 not in a communication state are in a disabled state.
The control chip 1 is provided with a polling interval time, in a plurality of communication states, if the RS485 chip 2 is successfully communicated, the I/O control unit 12 connected with the RS485 chip 2 which is successfully communicated puts the RS485 chip 2 which is successfully communicated in a disabled state, the next communication unit which needs to be communicated is put in a communication state under the control of the I/O control unit 12 connected with the next communication unit, if the RS485 chip 2 is not successfully communicated in the polling interval time, the RS485 chip 2 is put in the disabled state by the I/O control unit 12 connected with the next communication unit which needs to be communicated, and the next communication unit which needs to be communicated is put in the communication state under the control of the I/O control unit 12 connected with the next communication unit.
In this embodiment, the RS485 chip 2 has an enable end, and the I/O control unit 12 sends a control signal to the RS485 chip 2 through the I/O signal interface circuit 13, and the enable end receives the control signal, and the enable end includes a sending enable end RE and a receiving enable end DE.
Next, the present embodiment takes the connection between one I/O signal interface circuit 13 and one RS485 chip 2 and the connection between one RS485 chip 2 and the communication bus as an example, and describes the circuit connection between the I/O signal interface circuit 13 and one RS485 chip 2 and the circuit connection between the RS485 chip 2 and the communication bus. The circuit connection between the rest of the I/O signal interface circuits 13 and the RS485 chip 2, and the circuit connection between the rest of the RS485 chip 2 and the communication bus are the same, and therefore, the description is omitted.
As shown in fig. 2, the I/O signal interface circuit 13 includes two transistors, wherein a collector of one transistor is connected to the receiving enable terminal DE and is connected to +5V level through a resistor R118, a base is connected to the control chip 1 through a resistor R120, and an emitter is grounded. The collector of the other triode is connected with a transmitting enable end RE and is connected with +5V level through a resistor R119, the base of the other triode is connected with the control chip 1 through a resistor R121, and the emitter of the other triode is grounded.
The RS485 chip 2 includes an RO pin and a DI pin connected to the UART unit 11, and is configured to receive an RX signal and a TX signal of the UART unit 11, and a differential signal is used between the RS485 chip 2 and the UART unit 11 to transmit data.
The RS485 chip 2 further comprises a grounding pin and a VCC pin, wherein the VCC pin is connected with a 5V level and is grounded through a capacitor C46.
The RS485 chip 2 further comprises a pin A and a pin B, and the pin A and the pin B of the RS485 chip 2 are correspondingly connected with the pin A and the pin B of the RS485 communication bus. In this embodiment, in addition to the parallel resistor R123, a transient suppression diode TVS3 is connected in parallel between the pin a and the pin B for surge protection, and a thermistor RT3 is connected in series between the pin a for current limiting protection, and the thermistor RT3 is connected behind the transient suppression diode TVS 3.
In the present embodiment, pin a is connected to +5V level through resistor R124 before resistor R124, and pin a is connected to ground through resistor R122 before resistor R123.
In this embodiment, when the transmission enable end RE and the reception enable end DE are both at a high level, the RS485 chip 2 is in a communication state to transmit data to the RS485 communication bus, when the transmission enable end RE and the reception enable end DE are both at a low level, the RS485 chip 2 is in a communication state to receive data from the RS485 communication bus, and when the transmission enable end RE is at a low level and the reception enable end DE is at a high level, the RS485 chip 2 is in a disabled state.
According to the embodiment, data transmission and data reception of a plurality of RS485 buses can be realized by only using one UART unit 11 without increasing a serial port extension chip, and the capacity of a single control chip 1 for controlling equipment is improved without increasing a serial port extension chip by adding redundant logic units. Because the utility model discloses relative prior art does not relate to serial ports extension chip and logic unit, only uses the IO the control unit of control chip itself, consequently, has advantage with low costs, that the circuit is simple. Since the polling mechanism belongs to the prior art, and the I/O control unit controls the RS485 unit to be in the communication state or the disabled state, the implementation of the beneficial effects described in this specification is implemented based on the improvement of the connection structure of the technical solution, and does not involve the improvement in the program.
While the present invention has been described with reference to the particular illustrative embodiments, it will be understood by those skilled in the art that the present invention is not limited thereto, and may be embodied in many different forms without departing from the spirit and scope of the present invention as set forth in the following claims. Any modification which does not depart from the functional and structural principles of the present invention is intended to be included within the scope of the claims.
Claims (8)
1. A communication circuit, comprising a control chip, characterized in that: the control chip comprises a UART unit and a plurality of I/O control units, the communication circuit comprises a plurality of communication units, each communication unit is connected with one I/O control unit, the control chip controls the communication unit connected with the control chip to be in a communication state or a forbidden state through the I/O control unit, the communication units are simultaneously connected with the UART unit, and the control chip sends data to a communication bus or receives communication bus data through the UART unit and the communication units;
the communication circuit comprises a single communication state and a plurality of communication states, wherein in the single communication state, the control chip controls the communication unit connected with the control chip to be in a communication state through one of the I/O control units, and controls the respectively connected communication units to be in a forbidden state through the rest I/O control units; in the plurality of communication states, the control chip makes the communication units connected with the control chip be in the communication state in sequence through the I/O control unit in a polling mode, and other communication units which are not in the communication state are in the forbidden state.
2. The communication circuit according to claim 1, wherein the control chip is provided with a polling interval time, and in the plurality of communication states, if the communication unit succeeds in communication, the I/O control unit connected to the communication unit that succeeds in communication places the communication unit that succeeds in communication in a disabled state, and the next communication unit that needs to communicate is placed in a communication state under the control of the I/O control unit connected thereto, and if the communication unit fails in communication within the polling interval time, the communication unit is placed in a disabled state by the I/O control unit connected thereto, and the next communication unit that needs to communicate is placed in a communication state under the control of the I/O control unit connected thereto.
3. The communication circuit according to claim 1, wherein the communication unit is an RS485 chip, and the communication bus is an RS485 communication bus.
4. The communication circuit of claim 3, further comprising an I/O signal interface circuit, wherein the RS485 chip has an enable terminal, and wherein the I/O control unit sends a control signal to the RS485 chip via the I/O signal interface circuit, and wherein the enable terminal receives the control signal.
5. The communication circuit according to claim 4, wherein the enable terminal includes a transmit enable terminal and a receive enable terminal, the I/O control unit transmits a control signal to the transmit enable terminal and the receive enable terminal through the I/O signal interface circuit, the RS485 chip is in a communication state to transmit data to the RS485 communication bus when both the transmit enable terminal and the receive enable terminal are at a high level, the RS485 chip is in a communication state to receive data from the RS485 communication bus when both the transmit enable terminal and the receive enable terminal are at a low level, the RS485 chip is in a disable state when the transmit enable terminal is at a low level and the receive enable terminal is at a high level.
6. The communication circuit according to claim 4 or 5, wherein the I/O signal interface circuit comprises two transistors, bases of the two transistors are connected with the control chip, emitters of the two transistors are grounded, a collector of one transistor is connected with the transmitting enable terminal, and a collector of the other transistor is connected with the receiving enable terminal.
7. The communication circuit according to claim 4 or 5, wherein a transient suppression diode is connected in parallel between two pins connected with the RS485 communication bus of the RS485 chip.
8. The communication circuit according to claim 7, wherein a thermistor is connected in series to one of two pins of the RS485 chip connected to the RS485 communication bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921181679.3U CN210327615U (en) | 2019-07-25 | 2019-07-25 | Communication circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921181679.3U CN210327615U (en) | 2019-07-25 | 2019-07-25 | Communication circuit |
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| Publication Number | Publication Date |
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| CN210327615U true CN210327615U (en) | 2020-04-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201921181679.3U Expired - Fee Related CN210327615U (en) | 2019-07-25 | 2019-07-25 | Communication circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114301814A (en) * | 2021-12-10 | 2022-04-08 | 贵州航天凯山石油仪器有限公司 | Method for realizing 485 communication with multiple products based on polling mode |
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2019
- 2019-07-25 CN CN201921181679.3U patent/CN210327615U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114301814A (en) * | 2021-12-10 | 2022-04-08 | 贵州航天凯山石油仪器有限公司 | Method for realizing 485 communication with multiple products based on polling mode |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200414 |
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| CF01 | Termination of patent right due to non-payment of annual fee |