CN216670542U - CAN bus interface circuit - Google Patents

CAN bus interface circuit Download PDF

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CN216670542U
CN216670542U CN202123081163.1U CN202123081163U CN216670542U CN 216670542 U CN216670542 U CN 216670542U CN 202123081163 U CN202123081163 U CN 202123081163U CN 216670542 U CN216670542 U CN 216670542U
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pin
bus
electrically connected
chip
power supply
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耿涛
王腊梅
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Micogen General Technology Inc
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The utility model relates to a CAN bus interface circuit. The CAN bus interface circuit comprises a CAN bus control unit, a CAN bus isolation unit and a CAN bus transceiving unit, wherein the CAN bus control unit comprises a control chip, the CAN bus isolation unit comprises an isolation chip, and the CAN bus transceiving unit comprises a drive chip. The CAN signal transmitting pin TX0 of the control chip is electrically connected to the input pin INB of the isolation chip through a resistor R494, the CAN signal receiving pin RX0 of the control chip is electrically connected to the output pin OUTA of the isolation chip through a resistor R528, the input pin INA of the isolation chip is electrically connected to the receiving data pin RXD of the driving chip through a resistor R488, and the output pin OUTB of the isolation chip is electrically connected to the transmitting data pin TXD of the driving chip. The CAN bus is subjected to an optical isolation design, so that the electrical isolation of a CAN bus communication circuit is realized, and the anti-interference capability and the isolation protection effect of the CAN are improved.

Description

CAN bus interface circuit
Technical Field
The utility model relates to the technical field of CAN communication, in particular to a CAN bus interface circuit.
Background
Communication circuits play an important role in various industries and are responsible for the exchange and transfer of data among various components of a system. The Controller Area Network (CAN) bus communication belongs to the field bus category, is a serial communication Network which effectively supports distributed control and real-time control, and compared with a common communication bus, the CAN bus has outstanding reliability, real-time performance and flexibility in remote data communication.
However, because some field situations are very complicated, for example, electromagnetic environments in some fields are severe, and the positions of the nodes are not consistent, so that a backflow current exists, a common mode voltage is generated, although the CAN interface has a certain capability of resisting common mode interference, when the common mode voltage exceeds the limit receiving voltage of the CAN transceiver, the CAN transceiver cannot normally work, and in severe cases, the CAN transceiver or a circuit board is even burnt, so that in order to adapt to a strong interference environment or high performance requirements, each communication node of the CAN bus must be electrically isolated.
The above statements in the background are only intended to facilitate a thorough understanding of the present technical solutions (technical means used, technical problems solved and technical effects produced, etc.) and should not be taken as an acknowledgement or any form of suggestion that the messages constitute prior art already known to a person skilled in the art.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a CAN bus interface circuit, a CAN signal sending pin TX0 is transmitted to a sending data pin TXD of a driving chip through an isolation chip so as to be transmitted through a CAN bus, a receiving data pin RXD of the driving chip transmits a signal received through the CAN bus to a CAN signal receiving pin RX0 through the isolation chip, and the CAN bus is subjected to optical isolation design, so that the electrical isolation of a CAN bus communication circuit is realized, and the anti-interference capability and the isolation protection effect of the CAN are improved.
According to an embodiment of the present invention, there is provided a CAN bus interface circuit, including a CAN bus control unit, a CAN bus isolation unit, and a CAN bus transceiver unit, where the CAN bus control unit includes a control chip, and the control chip includes a CAN signal transmission pin TX0 and a CAN signal reception pin RX 0; the CAN bus isolation unit comprises an isolation chip, wherein the isolation chip comprises an input pin INA, an input pin INB, an output pin OUTA and an output pin OUTB; the CAN bus transceiving unit comprises a driving chip, wherein the driving chip comprises a data transmitting pin TXD, a data receiving pin RXD, a high-level CAN bus pin CANH and a low-level CAN bus pin CANL; the CAN signal transmitting pin TX0 of the control chip is electrically connected to the input pin INB of the isolation chip through a resistor R494, the CAN signal receiving pin RX0 of the control chip is electrically connected to the output pin OUTA of the isolation chip through a resistor R528, the input pin INA of the isolation chip is electrically connected to the receiving data pin RXD of the driving chip through a resistor R488, and the output pin OUTB of the isolation chip is electrically connected to the transmitting data pin TXD of the driving chip; the CAN bus transceiver unit is provided with the contact pin, the first foot and the first foot of contact pin are short-circuited through short circuit cap J9, driver chip's high level CAN bus pin CANH is electrically connected to the first foot of contact pin through resistance R490 electricity, driver chip's low level CAN bus pin CANL is electrically connected to the second foot of contact pin.
Furthermore, the CAN bus transceiver unit is provided with a TVS diode, pin 1 of the TVS diode is electrically connected with low level CAN bus pin CANL of the driver chip, pin 2 of the TVS diode is electrically connected with high level CAN bus pin CANH of the driver chip, and pin 3 of the TVS diode is electrically connected to signal ground CAN0_ GND.
Further, the control chip further comprises: power supply pin VDD1, power supply pin VDD2, power supply pin VDD3, ground pin VSS1, ground pin VSS2, ground pin VSS3, MODE selection pin MODE, interrupt output pin
Figure BDA0003402161440000021
And CAN signal receive pin RX 1; the power pin VDD1, the power pin VDD2 and the power pin VDD3 are electrically connected to a power supply 5V0 respectively; the ground pins VSS1, VSS2 and VSS3 are electrically connected to the power ground respectivelyGND; the MODE selection pin MODE is electrically connected to the power supply 5V0 through a resistor R482; interrupt output pin
Figure BDA0003402161440000022
Is electrically connected to a power supply 3V3 through a resistor R486; the CAN signal receiving pin RX1 is electrically connected to the power supply 5V0 through a resistor R484 and to the power supply ground GND through a resistor R485; a capacitor C512, a capacitor C525 and a capacitor C524 are connected in parallel between the power supply 5V0 and the power ground GND.
Further, the isolated chip further comprises a power supply pin VCC1, a power supply pin VCC2, a ground pin GND1 and a ground pin GND 2; the ground pin GND1 is electrically connected to the power ground GND, and the ground pin GND2 is electrically connected to the signal ground CAN0_ GND; the power supply pin VCC1 is electrically connected to the power supply 5V0, and the power supply pin VCC2 is electrically connected to the power supply CAN0_5V 0; a capacitor C538 is electrically connected between the power supply 5V0 and the power supply ground GND, and a capacitor C539 is electrically connected between the power supply CAN0_5V0 and the signal ground CAN0_ GND; a resistor R489 is connected between the output pin OUTA and the power supply 5V0 in a bridging manner; a resistor R487 is connected across the output pin OUTB and the power supply CAN0_5V 0.
Further, the driving chip further includes: a power supply pin VCC, a ground pin GND, a common mode output pin VREF and a pin STB for selecting the working mode or the standby mode of the driving chip; the ground pin GND is electrically connected to the signal ground CAN0_ GND; the power pin VCC is electrically connected to the power CAN0_5V 0; pin STB is electrically connected to signal ground CAN0_ GND through resistor R483.
Further, the pins are single row 2-core pins with a pitch of 2.54 mm.
Further, the model of the TVS diode is NUP2105LT 1G.
Further, the model of the control chip is SMSJA 1000.
Further, the type of the isolation chip is CBMuD1201HAS 8.
Further, the model of the driving chip is SM 1040.
By adopting the technical scheme, the utility model has the following beneficial effects: the CAN signal transmission pin TX0 is transmitted to the transmission data pin TXD of the driving chip through the isolation chip, so that the transmission is realized through a CAN bus, and the signal received by the CAN bus through the isolation chip is transmitted to the CAN signal reception pin RX0 through the reception data pin RXD of the driving chip, so that the electrical isolation of a CAN bus communication circuit CAN be realized through the optical isolation design of the CAN bus, and the anti-interference capability and the isolation protection effect of the CAN are improved.
Drawings
Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same elements. It is noted that the drawings are merely schematic and are not necessarily drawn to scale. In these drawings:
fig. 1 is a block diagram illustrating a CAN bus interface circuit according to an exemplary embodiment of the present invention.
Fig. 2 is a circuit schematic diagram illustrating a CAN bus control unit of a CAN bus interface circuit according to an exemplary embodiment of the present invention.
Fig. 3 is a circuit schematic diagram illustrating a CAN bus isolation unit of a CAN bus interface circuit according to an exemplary embodiment of the present invention.
Fig. 4 is a circuit schematic diagram illustrating a CAN-bus transceiving unit of a CAN-bus interface circuit according to an exemplary embodiment of the present invention.
Detailed Description
The embodiments of the present invention will be described in detail below, which are carried out on the premise of the technical scheme of the present invention, and detailed embodiments and specific operation procedures are given, but the scope of the present invention is not limited to the embodiments described below.
Fig. 1 is a block diagram illustrating a CAN bus interface circuit according to an exemplary embodiment of the present invention. As shown in fig. 1, a CAN bus interface circuit according to an exemplary embodiment of the present invention includes: a CAN bus control unit 100, a CAN bus isolation unit 200, and a CAN bus transceiver unit 300.
In an exemplary embodiment of the present invention, the CAN bus control Unit 100 is used to control an execution state of the CAN bus, and particularly, a Micro Controller Unit (MCU) (not shown) may write data to be transmitted to a transmission register of the CAN bus control Unit 100 or read data from a reception register of the CAN bus control Unit 100 through an external bus.
The CAN-bus control unit 100 CAN receive and transmit data in accordance with the timing of the CAN bus. The CAN bus transceiver 300 transmits and receives signals to and from the CAN bus, and the CAN bus transceiver 300 provides an interface between the CAN bus controller 100 and the physical bus, and has a differential transmission capability to the CAN bus and a differential reception capability to the CAN bus controller. Specifically, the CAN bus transceiver unit 300 CAN convert the logic level (CAN _ TX0, CAN _ RX0) from the CAN bus controller 100 into a differential signal (CANH, CANL) required by the CAN bus for transmission, and simultaneously receive the signal on the differential line and transmit the received signal to the receive pin of the CAN bus controller 100.
The CAN bus isolation unit 200 is electrically connected between the CAN bus control unit 100 and the CAN bus transceiver unit 300, and is used for electrically isolating signals transmitted and received by the CAN bus.
Fig. 2 is a circuit schematic diagram illustrating a CAN bus interface circuit according to an exemplary embodiment of the present invention. Fig. 3 is a circuit schematic diagram illustrating a CAN bus isolation unit of a CAN bus interface circuit according to an exemplary embodiment of the present invention. Fig. 4 is a circuit schematic diagram illustrating a CAN-bus transceiving unit of a CAN-bus interface circuit according to an exemplary embodiment of the present invention.
As shown in fig. 2, the CAN-bus control unit 100 may include a control chip. In one embodiment, the model of the control chip may be SMSJA1000, but the utility model is not limited thereto. The SMSJA1000 is an independent CAN protocol controller and fully supports the CAN V2.0B technical specification. The SMSJA1000 is capable of sending and receiving standard and extended data frames as well as remote frames. The acceptance mask register of the SMSJA1000 can filter out unwanted messages, thereby reducing the overhead of the micro-control unit. The connection of the SMSJA1000 to the parallel bus is achieved by the industry standard Localbus. The communication speed can reach 10KM at 1Mbps communication distance.
As shown in fig. 3, the CAN bus isolation unit 200 may include an isolation chip. In one embodiment, the type of the isolated chip may be CBMuD1201HAS8, but the utility model is not limited thereto.
As shown in fig. 4, the CAN-bus transceiving unit 300 may include a driving chip. In one embodiment, the model of the driving chip may be SM1040, but the present invention is not limited thereto.
Referring to fig. 2, 3 and 4, the control chip of the CAN bus control unit 100 may include a CAN signal transmission pin TX0 and a CAN signal reception pin RX 0. The isolated chip of the CAN bus isolation unit 200 may include input pins INA and INB and output pins OUTA and OUTB. The driving chip of the CAN bus transceiving unit 300 may include a transmission data pin TXD and a reception data pin RXD, and a high level CAN bus pin CANH and a low level CAN bus pin CANL.
According to the embodiment of the utility model, the CAN signal transmission pin TX0 of the control chip is electrically connected to the input pin INB of the isolated chip through a resistor R494, the CAN signal reception pin RX0 of the control chip is electrically connected to the output pin OUTA of the isolated chip through a resistor R528, the input pin INA of the isolated chip is electrically connected to the reception data pin RXD of the driving chip through a resistor R488, and the output pin OUTB of the isolated chip is electrically connected to the transmission data pin TXD of the driving chip.
Therefore, the process of the CAN bus transceiver unit 300 converting the signal of the transmission pin TX0 of the CAN bus control unit 100 into the CAN specification differential signal output is as follows: the signal sent by the CAN signal sending pin TX0 of the control chip is transmitted to the input pin INB of the isolated chip through the resistor R494, transmitted to the sending data pin TXD of the driving chip through the output pin OUTB of the isolated chip, and converted into a differential signal for output. Preferably, R494 ═ 330 Ω, but the present invention is not limited thereto.
The process of the CAN bus transceiver unit 300 receiving the differential signal of the CAN bus and transmitting the received signal to the receiving pin RX0 of the CAN bus control unit is as follows: the signal on the data receiving pin RXD of the driver chip is sent to the input pin INA of the isolated chip through the resistor R488, and is transmitted to the CAN signal receiving pin RX0 of the control chip through the output pin OUTA and the resistor R528 of the isolated chip. Preferably, R488 ═ 470 Ω and R528 ═ 0 Ω, but the present invention is not limited thereto.
According to the exemplary embodiment of the utility model, the CAN signal transmission pin TX0 is transmitted to the transmission data pin TXD of the driver chip through the isolation chip, so as to be transmitted through the CAN bus, and the reception data pin RXD of the driver chip transmits the signal received through the CAN bus to the CAN signal reception pin RX0 through the isolation chip, so that through the optical isolation design of the CAN bus, the electrical isolation of the CAN bus communication circuit CAN be realized, and the anti-interference capability and the isolation protection effect of the CAN are increased.
In an exemplary embodiment of the present invention, the CAN bus transceiver unit is provided with pins, preferably, pins are single row 2-core pins with a pitch of 2.54 mm. The first pin and the second pin of the contact pin are in short circuit through a short circuit cap J9, a high-level CAN bus pin CANH of the drive chip is electrically connected to the first pin of the contact pin through a resistor R490, and a low-level CAN bus pin CANL of the drive chip is electrically connected to the second pin of the contact pin. R490 serves as a termination matching resistance of the bus, preferably, R490 ═ 120 Ω. The interface is designed with a 120 Ω matching resistance short-circuit cap J9, and whether to skip selection can be selected according to the bus requirements.
The CAN bus transceiver unit is provided with a TVS diode, preferably of the type NUP2105LT 1G. Pin 1 of the TVS diode is electrically connected to a low-level CAN bus pin CANL of the driver chip, pin 2 of the TVS diode is electrically connected to a high-level CAN bus pin CANH of the driver chip, and pin 3 of the TVS diode is electrically connected to a signal ground CAN0_ GND.
As shown in fig. 2, in an exemplary embodiment of the present invention, the control chip of the CAN-bus control unit 100 may further include: power supply pin VDD1, power supply pin VDD2, power supply pin VDD3, ground pin VSS1, ground pin VSS2, ground pin VSS3, MODE selection pin MODE, interrupt output pin
Figure BDA0003402161440000071
And CAN signal receive pin RX 1. The power pin VDD1, the power pin VDD2 and the power pin VDD3 are electrically connected to the power supply 5V0 respectively; the ground pin VSS1, the ground pin VSS2, and the ground pin VSS3 are electrically connected to the power ground GND, respectively; the MODE selection pin MODE is electrically connected to the power supply 5V0 through a resistor R482; interrupt output pin
Figure BDA0003402161440000072
Is electrically connected to a power supply 3V3 through a resistor R486; the CAN signal receiving pin RX1 is electrically connected to the power supply 5V0 through a resistor R484 and to the power supply ground GND through a resistor R485; a capacitor C512, a capacitor C525 and a capacitor C524 are connected in parallel between the power supply 5V0 and the power ground GND.
Preferably, the voltage of the power supply 5V0 is 5.0V, the voltage of the power supply 3V3 is 3.3V, R482 is 2.2K Ω, R486 is 2.2K Ω, R484 is 10K Ω, R485 is 10K Ω, C512 is 100NF, C525 is 100NF, and R524 is 100NF, but the present invention is not limited thereto.
As shown in fig. 3, in an exemplary embodiment of the present invention, the isolation chip of the CAN bus isolation unit 200 may further include: power pin VCC1 and power pin VCC2, ground pin GND1 and ground pin GND 2. The ground pin GND1 is electrically connected to the power ground GND, and the ground pin GND2 is electrically connected to the signal ground CAN0_ GND; the power pin VCC1 is electrically connected to the power supply 5V0, and the power pin VCC2 is electrically connected to the power supply CAN0_5V 0; a capacitor C538 is electrically connected between the power supply 5V0 and the power supply ground GND, and a capacitor C539 is electrically connected between the power supply CAN0_5V0 and the signal ground CAN0_ GND; a resistor R489 is connected between the output pin OUTA and the power supply 5V0 in a bridging manner; a resistor R487 is connected across the output pin OUTB and the power supply CAN0_5V 0.
Preferably, the voltage of the power supply 5V0 is 5.0V, the voltage of the power supply CAN0_5V0 is 5.0V, C538 is 100NF, C539 is 100NF, R487 is 2.2K Ω, and R489 is 2.2K Ω, but the present invention is not limited thereto.
As shown in fig. 4, the driving chip of the CAN bus transceiver unit 300 further includes: a power supply pin VCC, a ground pin GND, a common mode output pin VREF, and a pin STB for selecting an operation or standby mode of the driver chip. The ground pin GND is electrically connected to the signal ground CAN0_ GND; the power pin VCC is electrically connected to the power CAN0_5V 0; pin STB is electrically connected to signal ground CAN0_ GND through resistor R483.
Preferably, the voltage of the power supply CAN0 — 5V0 is 5.0V, and R483 ═ 1K Ω, but the present invention is not limited thereto.
According to the exemplary embodiment of the utility model, the CAN signal transmission pin TX0 is transmitted to the transmission data pin TXD of the driver chip through the isolation chip, so as to be transmitted through the CAN bus, and the reception data pin RXD of the driver chip transmits the signal received through the CAN bus to the CAN signal reception pin RX0 through the isolation chip, so that through the optical isolation design of the CAN bus, the electrical isolation of the CAN bus communication circuit CAN be realized, and the anti-interference capability and the isolation protection effect of the CAN are increased.
The various embodiments of the utility model are not an exhaustive list of all possible combinations, but are intended to describe representative aspects of the utility model, and what is described in the various embodiments can be applied independently or in combinations of two or more.
The above description of exemplary embodiments has been presented only to illustrate the technical solutions of the present invention, and is not intended to be exhaustive or to limit the utility model to the precise forms described. Obviously, many modifications and variations are possible in light of the above teaching to those skilled in the art. The exemplary embodiments were chosen and described in order to explain certain principles of the utility model and its practical application to thereby enable others skilled in the art to understand, implement and utilize the utility model in various exemplary embodiments and with various alternatives and modifications. It is intended that the scope of the utility model be defined by the following claims and their equivalents.

Claims (10)

1. A CAN bus interface circuit is characterized by comprising a CAN bus control unit, a CAN bus isolation unit and a CAN bus transceiving unit,
the CAN bus control unit comprises a control chip, and the control chip comprises a CAN signal transmitting pin TX0 and a CAN signal receiving pin RX 0;
the CAN bus isolation unit comprises an isolation chip, wherein the isolation chip comprises an input pin INA, an input pin INB, an output pin OUTA and an output pin OUTB;
the CAN bus transceiving unit comprises a driving chip, wherein the driving chip comprises a data transmitting pin TXD, a data receiving pin RXD, a high-level CAN bus pin CANH and a low-level CAN bus pin CANL;
the CAN signal transmitting pin TX0 of the control chip is electrically connected to the input pin INB of the isolation chip through a resistor R494, the CAN signal receiving pin RX0 of the control chip is electrically connected to the output pin OUTA of the isolation chip through a resistor R528, the input pin INA of the isolation chip is electrically connected to the receiving data pin RXD of the driving chip through a resistor R488, and the output pin OUTB of the isolation chip is electrically connected to the transmitting data pin TXD of the driving chip;
the CAN bus transceiver unit is provided with the contact pin, the first foot and the second foot of contact pin are short-circuited through short circuit cap J9, driver chip's high level CAN bus pin CANH is electrically connected to the first foot of contact pin through resistance R490 electricity, driver chip's low level CAN bus pin CANL is electrically connected to the second foot of contact pin.
2. The CAN-bus interface circuit of claim 1,
the CAN bus transceiver unit is provided with a TVS diode, a pin 1 of the TVS diode is electrically connected with a low-level CAN bus pin CANL of the drive chip, a pin 2 of the TVS diode is electrically connected with a high-level CAN bus pin CANH of the drive chip, and a pin 3 of the TVS diode is electrically connected to a signal ground CAN0_ GND.
3. The CAN-bus interface circuit of claim 1,
the control chip further comprises: power supply pin VDD1, power supply pin VDD2, power supply pin VDD3, ground pin VSS1, ground pin VSS2, ground pin VSS3, mode selection pinPin MODE, interrupt output pin
Figure FDA0003402161430000011
And CAN signal receive pin RX 1;
the power pin VDD1, the power pin VDD2 and the power pin VDD3 are electrically connected to a power supply 5V0 respectively;
the ground pin VSS1, the ground pin VSS2, and the ground pin VSS3 are electrically connected to the power ground GND, respectively;
the MODE selection pin MODE is electrically connected to the power supply 5V0 through a resistor R482;
interrupt output pin
Figure FDA0003402161430000021
Is electrically connected to a power supply 3V3 through a resistor R486;
the CAN signal receiving pin RX1 is electrically connected to the power supply 5V0 through a resistor R484 and to the power supply ground GND through a resistor R485;
a capacitor C512, a capacitor C525 and a capacitor C524 are connected in parallel between the power supply 5V0 and the power ground GND.
4. The CAN-bus interface circuit of claim 1,
the isolation chip further comprises a power supply pin VCC1, a power supply pin VCC2, a ground pin GND1 and a ground pin GND 2;
the ground pin GND1 is electrically connected to the power ground GND, and the ground pin GND2 is electrically connected to the signal ground CAN0_ GND;
the power supply pin VCC1 is electrically connected to the power supply 5V0, and the power supply pin VCC2 is electrically connected to the power supply CAN0_5V 0;
a capacitor C538 is electrically connected between the power supply 5V0 and the power supply ground GND, and a capacitor C539 is electrically connected between the power supply CAN0_5V0 and the signal ground CAN0_ GND;
a resistor R489 is connected between the output pin OUTA and the power supply 5V0 in a bridging manner;
a resistor R487 is connected across the output pin OUTB and the power supply CAN0_5V 0.
5. The CAN-bus interface circuit of claim 1,
the driving chip further includes: a power supply pin VCC, a ground pin GND, a common mode output pin VREF and a pin STB for selecting the working mode or the standby mode of the driving chip;
the ground pin GND is electrically connected to the signal ground CAN0_ GND;
the power pin VCC is electrically connected to the power CAN0_5V 0;
pin STB is electrically connected to signal ground CAN0_ GND through resistor R483.
6. The CAN bus interface circuit of claim 1, wherein the pins are single row 2-core pins with a pitch of 2.54 mm.
7. The CAN bus interface circuit of claim 2, wherein said TVS diode is of the type NUP2105LT 1G.
8. The CAN bus interface circuit of claim 1, wherein the control chip is model number SMSJA 1000.
9. The CAN bus interface circuit of claim 1, wherein the isolated die is of the type CBMuD1201HAS 8.
10. The CAN bus interface circuit of claim 1, wherein the driver chip is model SM 1040.
CN202123081163.1U 2021-12-09 2021-12-09 CAN bus interface circuit Active CN216670542U (en)

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