CN206181001U - Take integrated circuit of multiplexing pin - Google Patents
Take integrated circuit of multiplexing pin Download PDFInfo
- Publication number
- CN206181001U CN206181001U CN201621074150.8U CN201621074150U CN206181001U CN 206181001 U CN206181001 U CN 206181001U CN 201621074150 U CN201621074150 U CN 201621074150U CN 206181001 U CN206181001 U CN 206181001U
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- Prior art keywords
- signal
- integrated circuit
- multiplexing pins
- signal input
- input
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Abstract
The utility model discloses a take integrated circuit of multiplexing pin, the utility model discloses extend two links with integrated circuit's a pin for receiving two logic level signals, and finally restoring in the piece these two signals, the signal whether sign made the ability is received to the the first signal input, and the 2nd signal input part receives the function signal, realizes the signal of a certain function promptly, and uses multipurposely diode, resistance and first electric current source, according to switching on of diode and clamper characteristic, in order to realize the multiplexing of pin, reduce the area that the chip occupy on the PIN foot scalar sum board of encapsulation, be favorable to the little packaging design of chip.
Description
Technical field
The utility model is related to technical field of integrated circuits, and in particular to a kind of integrated circuit with multiplexing pins.
Background technology
It is using certain technique, the elements such as the transistor needed for a circuit, resistance, electric capacity and inductance and wiring is mutual
Together with, it is produced on a fritter or a few fritter semiconductor wafers or dielectric substrate, is then encapsulated in a shell, is formed
Integrated circuit (integrated circuit), also referred to as chip.
Pin is provided with chip, to be attached with peripheral circuit.Under normal circumstances, when chip needs input two
During the logical signal of individual low and high level, need to take two input PINs, such as, one is accessed the pin for characterizing enable signal,
Another is the pin for accessing pending signal or realizing some function.
By taking LNB chips (the low news frequency reducing amplifiers of low noise block downconverter-) as an example, prior art
LNB chips as shown in figure 1, having special EXTM pin for receiving 22kHz signals, and chip has special EN pin for connecing
Receive and enable signal.The pin resource of chip is so taken very much, is unfavorable for the small package design of chip, this technical problem certainly will
Also people can be promoted to pay creative work to reduce number of pins.
Utility model content
In view of this, the purpose of this utility model is to provide one kind to realize that a pin can be input into two low and high level letters
Number the integrated circuit with multiplexing pins, to the technical problem that cannot realize pin multiplexing for solving prior art presence.
Technical solution of the present utility model is to provide a kind of integrated circuit with multiplexing pins of following structure, bag
Include：
For receiving the multiplexing pins of two low and high level signals, described multiplexing pins extend two connection ends, its
In, the first connection end is connected with the anode of diode, the first signal input part of the negative electrode of the diode as the connection end；
Second connection end is connected with one end of resistance, the secondary signal input of the other end of the resistance as the connection end；
On-chip circuit, including the first current source and comparison circuit, the first described current source is electrically connected with the multiplexing pins
Connect, the comparison circuit is compared the voltage in multiplexing pins and first threshold voltage, obtain characterizing first signal
Voltage in the multiplexing pins and second threshold voltage are compared, are obtained by the signal of input input, the comparison circuit
To the signal for characterizing the secondary signal input input.
Preferably, the first described signal input part is used as Enable Pin, described secondary signal input is used as function
Signal input part, in the case where first signal input part receives and characterizes and enable signal, the integrated circuit is enabled, by than
The signal and with the function signal consistent signal consistent with the enable signal is exported respectively compared with circuit.
Preferably, described comparison circuit includes first comparator and the second comparator, described first comparator
First input end is connected with the multiplexing pins, and its second input receives described first threshold voltage, its output end output the
One comparison signal；The first input end of the second described comparator is connected with the multiplexing pins, and its second input receives institute
Second threshold voltage is stated, its output end exports the second comparison signal.
Preferably, be additionally provided with bleeder circuit and the first electric capacity at described multiplexing pins, described bleeder circuit it is defeated
Enter end and receive the function signal, its output end is connected with the secondary signal input, described the first electric capacity and the electricity
Resistance is in parallel.
Preferably, forward conduction voltage drop of the first threshold voltage more than the diode, so that the first signal is defeated
Enter end in the case where the low level that reception sign is not enabled does not enable signal, the integrated circuit is not enabled.
Preferably, when first signal input part receives high level signal, the voltage of the high level and described two
The forward conduction voltage drop sum of pole pipe is big in the ohmically pressure drop more than first current source more than second threshold voltage
In first threshold voltage.
Preferably, when the secondary signal input receives the function signal of high level, the high level function signal
Voltage and first current source be more than second threshold voltage in the ohmically pressure drop sum.
Another technical solution of the present utility model is to provide a kind of LNB chips of following structure, including any of the above
A kind of integrated circuit with multiplexing pins.
Preferably, described secondary signal input receives square-wave signal.
Using circuit structure of the present utility model, compared with prior art, with advantages below：The utility model will be integrated
One pin of circuit extends two connection ends, to receive two logic level signals, and finally the two signals is existed
Restore in piece, the first signal input part is received and characterizes the signal for whether enabling, secondary signal input receive capabilities signal, i.e., in fact
The signal of existing some function, and diode, resistance and the first current source are comprehensively utilized, the conducting and clamper spy according to diode
Property, to realize the multiplexing of pin；The area that the PIN number and chip on board of encapsulation take is reduced, is conducive to the little envelope of chip
Installing meter.
Description of the drawings
Fig. 1 is the structural representation of the integrated circuit pin of prior art；
Fig. 2 is the structural representation of integrated circuit of the utility model with multiplexing pins；
Fig. 3 is the corresponding working waveform figure of the integrated circuit with multiplexing pins of Fig. 2；
Fig. 4 is working waveform figure of Fig. 2 embodiments when diode parasitic capacitance is larger；
Fig. 5 is the structural representation of another embodiment of the utility model.
Specific embodiment
Preferred embodiment of the present utility model is described in detail below in conjunction with accompanying drawing, but the utility model is not merely
It is limited to these embodiments.The utility model covers any replacement made in spirit and scope of the present utility model, modification, equivalent
Method and scheme.
In order that the public has to the utility model thoroughly understand, in following the utility model preferred embodiment specifically
Clear concrete details, and for a person skilled in the art description without these details can also completely understand that this practicality is new
Type.
Referring to the drawings the utility model more particularly described below by way of example in the following passage.It should be noted that, accompanying drawing
In the form of more simplifying and using non-accurately ratio, only conveniently, lucidly to aid in illustrating the utility model
The purpose of embodiment.
With reference to shown in Fig. 2, illustrate the integrated circuit with multiplexing pins, including multiplexing pins with mutually cooperate with therewith in piece
Circuit.The pin of integrated circuit is transformed by way of increasing peripheral applications circuit so as to which, with multiplexing function, the multiplexing is drawn
Pin mainly in two logic level signals as the multiplexing pins input signal.Described multiplexing pins extend two
Connection end, wherein, the first connection end is connected with the anode of diode, and the negative electrode of the diode is believed as the first of the connection end
Number input；Second connection end is connected with one end of resistance, and the other end of the resistance is defeated as the secondary signal of the connection end
Enter end.On-chip circuit, including the first current source IENAnd comparison circuit, the first described current source IENWith multiplexing pins electricity
Connection, the comparison circuit is compared the voltage in multiplexing pins and first threshold voltage EN_REF, obtains sign described
The signal of the first signal input part input, the comparison circuit is by the voltage and second threshold voltage in the multiplexing pins
EXTM_REF is compared, and obtains characterizing the signal of the secondary signal input input.
The embodiment of Fig. 2 can be applicable in LNB circuits, and the defeated of two logic levels of EN and EXTM is needed in the prior art
Enter signal respectively by two pin inputs, the EXTM pin and EN pin of chip are multiplexed with into EN_EXTM pin in the present embodiment, reduce
The PIN number of encapsulation, the small package that is conducive to chip is designed.As shown in Fig. 2 connection end EXTM passes through resistance R (its resistance
It is set as R) it is connected with multiplexing pins EN_EXTM, connection end EN is connected by a diode D with multiplexing pins EN_EXTM, even
Meet end EN and connect diode cathode.It is I including in the chip of on-chip circuit a size can be flowed out to multiplexing pins EN_EXTMEN's
Electric current.
The mode that chip internal judges may be set to when input voltage is higher than EN_REF, and chip is started working, that is, enable.
When input voltage is in the upper and lower saltus steps of EXTM_REF, it is considered as and have input a square-wave signal.Input voltage referred herein is referred to
Input voltage in multiplexing pins, by diode D, resistance R and the first current source IENComprehensive function determine.
When in connection end EN input high level signals, it is 0 that in connection end, EXTM is input into a low level, and high level adds IEN*R
When being the 22kHz square-wave signals more than EXTM_REF, chip just can receive connection end while EN high level is received
The 22kHz input signals of EXTM.
With reference to shown in Fig. 3, the corresponding work wave with the integrated circuit with multiplexing pins shown in Fig. 2 is illustrated.In figure
Including the waveform of EN, EXTM, EN_EXTM, EN_H and EXTM_H, EN_H and EXTM_H is respectively first comparator in comparison circuit
With the output signal of the second comparator.
In order to obtain more preferable implementation result, during specific works, external devices setting is set to internal reference：
1、EN_REF>Vd (Vd is the forward conduction voltage drop of external diode)；
2、VEN(EN inputs are high level)+Vd>EXTM_REF>IEN*R>EN_REF；
3、VEXTM(EXTM inputs are high level)+IEN*R>EXTM_REF
Particular state is as follows：
1st, EN accesses low level：Now no matter which kind of state EXTM inputs are in, and EN_EXTM voltages are clamped at all the time two
Pole pipe conduction voltage drop Vd voltages or so, according to setting condition 1, EN_REF>Vd, then first comparator output EN_H is low, chip
Do not enable.
2nd, EN high level, EXTM is low level：According to condition 2 is arranged, external diode is not turned on, EN_EXTM voltages etc.
In IEN*R.This voltage is between EN_REF and EXTM_REF, therefore EN_H is height, and EXTM_H is low；
EN high level, EXTM is high level：According to condition 3 is arranged, EN_EXTM signals are higher than EXTM_REF, therefore EN_H is
Height, EXTM_H is height.
According to case above, then in EN high level, when EXTM receives 22kHz square-wave signals：It is low when the EXTM signal half periods
During level, EN_H is height, and EXTM_H is low.When the EXTM signal half periods being high level, according to condition 3 is arranged, EN_EXTM believes
Number be higher than EXTM_REF, therefore EN_H for height, EXTM_H for height.So in chip, EXTM_H has restored the signal of 22kHz.
With reference to shown in Fig. 4, work wave of Fig. 2 embodiments when diode parasitic capacitance is larger is illustrated.I.e. in reality
Using when, if the parasitic capacitance of the diode D for using is larger, it is possible that the trailing edge of EN_EXTM signals is too slow, so as to
The quality of chip internal reductase 12 2kHz signals is affected, and certain impact may be caused on its dutycycle, can be with reference in Fig. 4
EXTM waveforms, EN_EXTM waveforms and EXTM_H waveforms are contrasted, and in EXTM_H waveforms, the trailing edge of dotted portion is theoretical
Value, and bold portion for actual conditions.
With reference to shown in Fig. 5, circuit structure of the utility model relative to the improvement embodiment of Fig. 2 is illustrated.The above is retouched
State for it may be found that phenomenon, if this kind of phenomenon occurs, several devices can be increased on peripheral circuit and is realized EN_
The trailing edge steepening of EXTM signals.R1 and R2 are composed in series bleeder circuit, and the common port of the two is connected with one end of resistance R, point
The input of volt circuit is used as secondary signal input EXTM.The value of wherein R1 and R2 will cause the square wave width after EXTM partial pressures
Value VPP meets：VEN+Vd-EN_REF>VPP>EXTM_REF-IEN*R, and the first electric capacity C2 (described the first electric capacity C2 and institute
State resistance R in parallel) value to be significantly greater than parasitic capacitance C1.So, when EXTM rises, due to the coupling of the first electric capacity C2
Close so that EN_EXTM rapid increases, and it is finally stable in VEXTM*R2/(R1+R2)+IEN*R.When EXTM declines, the first electric capacity
The coupling of C2 can also make EN_EXTM rapid decreases, now meet square wave peak value VPP conditions, be unlikely to draw EN_EXTM voltages
The low EN_REF that crosses causes chip to turn off.The present embodiment can be by EN_EXTM rise and fall along steepening, the internal 22kHz signals of optimization
Dutycycle, the input signal of EXTM can be gone out by accurate recovery in EXTM_H.
In addition, although above embodiment is separately illustrated and is illustrated, but it is related to the common technology in part, in this area
Those of ordinary skill apparently, can between the embodiments be replaced and integrate, and be related to one of embodiment and be not expressly recited
Content, then refer to another embodiment on the books.
Embodiments described above, does not constitute the restriction to the technical scheme protection domain.It is any in above-mentioned enforcement
Modification, equivalent and improvement made within the spirit and principle of mode etc., should be included in the protection model of the technical scheme
Within enclosing.
Claims (9)
1. a kind of integrated circuit with multiplexing pins, it is characterised in that：Including：
For receiving the multiplexing pins of two low and high level signals, described multiplexing pins extend two connection ends, wherein, the
One connection end is connected with the anode of diode, the first signal input part of the negative electrode of the diode as the connection end；Second
Connection end is connected with one end of resistance, the secondary signal input of the other end of the resistance as the connection end；
On-chip circuit, including the first current source and comparison circuit, the first described current source is electrically connected with the multiplexing pins, institute
State comparison circuit to be compared the voltage in multiplexing pins and first threshold voltage, obtain characterizing first signal input part
The signal of input, the comparison circuit is compared the voltage in the multiplexing pins and second threshold voltage, is characterized
The signal of the secondary signal input input.
2. the integrated circuit with multiplexing pins according to claim 1, it is characterised in that：The first described signal input part
Used as Enable Pin, described secondary signal input receives table as function signal input in first signal input part
In the case of levying enable signal, the integrated circuit is enabled, and by comparison circuit the letter consistent with the enable signal is exported respectively
Number and the signal consistent with the function signal.
3. the integrated circuit with multiplexing pins according to claim 1 and 2, it is characterised in that：Described comparison circuit bag
First comparator and the second comparator are included, the first input end of described first comparator is connected with the multiplexing pins, it
Two inputs receive the first threshold voltage, and its output end exports the first comparison signal；The first of the second described comparator
Input is connected with the multiplexing pins, and its second input receives the second threshold voltage, and its output end output second is compared
Compared with signal.
4. the integrated circuit with multiplexing pins according to claim 2, it is characterised in that：Also set at described multiplexing pins
There are bleeder circuit and the first electric capacity, the input of described bleeder circuit receives the function signal, its output end and described the
Binary signal input connects, described the first electric capacity and the resistor coupled in parallel.
5. the integrated circuit of the multiplexing pins according to claim 1 or 4, it is characterised in that：The first threshold voltage is big
In the forward conduction voltage drop of the diode, so that the first signal input part does not enable letter in the low level that reception sign is not enabled
In the case of number, the integrated circuit is not enabled.
6. the integrated circuit with multiplexing pins according to claim 1 or 4, it is characterised in that：It is defeated in first signal
When entering end reception high level signal, the voltage of the high level is more than Second Threshold with the forward conduction voltage drop sum of the diode
Voltage is more than first threshold voltage more than first current source in the ohmically pressure drop.
7. the integrated circuit with multiplexing pins according to claim 5, it is characterised in that：In the secondary signal input
When receiving the function signal of high level, the voltage of the high level function signal is with first current source in the ohmically pressure
Drop sum is more than second threshold voltage.
8. a kind of LNB chips, it is characterised in that：Including any one integrated circuit with multiplexing pins of above claim 1-7.
9. LNB chips according to claim 8, it is characterised in that：Described secondary signal input receives square-wave signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621074150.8U CN206181001U (en) | 2016-09-23 | 2016-09-23 | Take integrated circuit of multiplexing pin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621074150.8U CN206181001U (en) | 2016-09-23 | 2016-09-23 | Take integrated circuit of multiplexing pin |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206181001U true CN206181001U (en) | 2017-05-17 |
Family
ID=58676555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621074150.8U Withdrawn - After Issue CN206181001U (en) | 2016-09-23 | 2016-09-23 | Take integrated circuit of multiplexing pin |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206181001U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106452421A (en) * | 2016-09-23 | 2017-02-22 | 杰华特微电子（杭州）有限公司 | Integrated circuit with multiplexing pin and pin multiplexing method |
| CN108736977A (en) * | 2018-03-29 | 2018-11-02 | 青岛海信宽带多媒体技术有限公司 | A kind of optical module |
-
2016
- 2016-09-23 CN CN201621074150.8U patent/CN206181001U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106452421A (en) * | 2016-09-23 | 2017-02-22 | 杰华特微电子（杭州）有限公司 | Integrated circuit with multiplexing pin and pin multiplexing method |
| CN106452421B (en) * | 2016-09-23 | 2023-05-16 | 杰华特微电子股份有限公司 | Integrated circuit with multiplexing pins and pin multiplexing method |
| CN108736977A (en) * | 2018-03-29 | 2018-11-02 | 青岛海信宽带多媒体技术有限公司 | A kind of optical module |
| CN108736977B (en) * | 2018-03-29 | 2021-05-11 | 青岛海信宽带多媒体技术有限公司 | Optical module |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province, 310030 Patentee after: Jiehuate Microelectronics Co.,Ltd. Address before: Room 424, building 1, 1500 Wenyi West Road, Cangqian street, Yuhang District, Hangzhou City, Zhejiang Province Patentee before: JOULWATT TECHNOLOGY Inc.,Ltd. |
|
| CP03 | Change of name, title or address | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20170517 Effective date of abandoning: 20230516 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20170517 Effective date of abandoning: 20230516 |
|
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |