CN218351490U - Silicon-based epitaxial wafer and semiconductor device - Google Patents
Silicon-based epitaxial wafer and semiconductor device Download PDFInfo
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Abstract
The utility model provides a silicon-based epitaxial wafer and a semiconductor device, wherein the silicon-based epitaxial wafer comprises a silicon-based substrate, an epitaxial structure and a buffer structure arranged between the silicon-based substrate and the epitaxial structure; the buffer structure comprises a low-temperature n-type doped aluminum nitride layer, a low-temperature undoped aluminum nitride layer, a high-temperature n-type doped aluminum nitride layer and a high-temperature undoped aluminum nitride layer which are sequentially stacked from the silicon-based substrate to one side of the epitaxial structure; the low-temperature n-type doped aluminum nitride layer and the high-temperature n-type doped aluminum nitride layer adopt a three-dimensional growth mode, and the low-temperature undoped aluminum nitride layer and the high-temperature undoped aluminum nitride layer adopt a two-dimensional growth mode. According to the method, through optimization of the buffer structure, the silicon-based epitaxial wafer with the smooth surface, the low dislocation density and the better crystal quality can be obtained.
Description
Technical Field
The utility model belongs to the technical field of semiconductor device, specifically relate to a silicon-based epitaxial wafer, and adopt this silicon-based epitaxial wafer's semiconductor device.
Background
Gallium nitride materials have been widely used in the fields of high frequency, high temperature, high voltage electronic devices, light Emitting Diodes (LEDs) and semiconductor lasers, etc. due to their advantages of low thermal generation efficiency, radiation resistance, high breakdown voltage, high electron saturation drift velocity, and low dielectric constant, and have become the hot spot of current research. Common substrates for epitaxially growing the gallium nitride film in the field are sapphire, silicon carbide and silicon, wherein the gallium nitride film epitaxially grown on the sapphire and silicon carbide substrates is mature, but the gallium nitride film epitaxially grown on the sapphire and silicon carbide substrates is expensive, particularly the silicon carbide is expensive, the production cost is greatly increased, the heat dissipation effect of the sapphire is poor, and the large-size epitaxial growth is difficult to realize. The gallium nitride film epitaxially grows on the silicon substrate, although the heat conductivity is good, large-size epitaxy can be realized, particularly 6-inch, 8-inch and 12-inch epitaxial wafers can be realized, the production cost can be reduced, and the market competitiveness is great. However, the gallium nitride epitaxial layer grown on the silicon substrate has larger lattice mismatch and thermal mismatch, the dislocation density in the gallium nitride epitaxial layer is higher, the dislocations can penetrate through the multiple quantum well active layers to form non-radiative recombination centers, the radiative recombination efficiency of carriers is reduced, and meanwhile, the dislocations can form a leakage channel to reduce the reliability of the LED device.
To grow a high quality epitaxial layer of gallium nitride with low dislocation density on a silicon substrate. In the existing silicon-based gallium nitride LED epitaxial process, low-temperature aluminum nitride, aluminum gallium nitride, aluminum nitride/aluminum gallium nitride superlattice or aluminum nitride/gallium nitride superlattice and the like are generally used as buffer layers between a silicon substrate and a gallium nitride epitaxial layer, so as to reduce lattice mismatch between the substrate and the gallium nitride epitaxial layer, reduce dislocation density and improve epitaxial layer crystal quality. However, although the extension of most threading dislocations can be effectively suppressed to reduce the dislocation density by applying the buffer layer structure, new dislocations may be introduced into the buffer layer structure itself, and it is difficult to effectively reduce the dislocation density, so that the crystal quality of the epitaxial wafer is not effectively improved.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a silicon-based epitaxial wafer and semiconductor device adopts the buffer structure including range upon range of low temperature n type doping aluminium nitride layer, low temperature undoped aluminium nitride layer, high temperature n type doping aluminium nitride layer and high temperature undoped aluminium nitride layer, can obtain surfacing, dislocation density is low, the better silicon-based epitaxial wafer of crystal quality.
In a first aspect, the present application provides a silicon-based epitaxial wafer, comprising:
a silicon-based substrate;
an epitaxial structure;
the buffer structure is arranged between the silicon-based substrate and the epitaxial structure and used for reducing lattice mismatch between the silicon-based substrate and the epitaxial structure;
the buffer structure comprises a low-temperature n-type doped aluminum nitride layer, a low-temperature undoped aluminum nitride layer, a high-temperature n-type doped aluminum nitride layer and a high-temperature undoped aluminum nitride layer which are sequentially stacked from the silicon-based substrate to one side of the epitaxial structure; the low-temperature n-type doped aluminum nitride layer and the high-temperature n-type doped aluminum nitride layer adopt a three-dimensional growth mode, and the low-temperature undoped aluminum nitride layer and the high-temperature undoped aluminum nitride layer adopt a two-dimensional growth mode.
Compared with the prior art, the beneficial effects of the application are that: through optimization of a buffer structure of the silicon-based epitaxial wafer, the low-temperature n-type doped aluminum nitride layer and the high-temperature n-type doped aluminum nitride layer can promote three-dimensional island-shaped growth of aluminum nitride, the three-dimensional island-shaped aluminum nitride layer can block extension of threading dislocation, silicon is doped in the growth process of the aluminum nitride layer, the healing process of the aluminum nitride island can be delayed, tensile stress formed in the healing process can be weakened, the defect inhibiting effect can be enhanced, the silicon doping can play a role of a mask, the dislocation is inhibited under the mask, and the dislocation in the aluminum nitride layer is deflected and annihilated; and the high-temperature n-type doped aluminum nitride layer grows again in a high-temperature three-dimensional manner, the dislocation density formed in the healing process of the low-temperature aluminum nitride island is reduced, the crystal quality of the whole aluminum nitride is improved by increasing the temperature, and the doping concentration of silicon can be reduced because the dislocation is mostly inhibited in the low-temperature aluminum nitride layer, and is lower than that of the low-temperature n-type doped aluminum nitride layer. In addition, the low-temperature undoped aluminum nitride layer and the high-temperature undoped aluminum nitride layer enable the low-temperature aluminum nitride island to be healed, fill up the three-dimensional island-shaped low-temperature aluminum nitride layer and reduce the surface roughness of aluminum nitride; and the high temperature undoped aluminum nitride layer enhances the crystal quality of the bulk aluminum nitride by raising the temperature.
Preferably, the thickness of the low-temperature n-type doped aluminum nitride layer is 30nm to 50nm, and the low-temperature n-type doped aluminum nitride layer is prepared by adopting vapor deposition growth conditions of 800 ℃ to 900 ℃, 50torr to 100torr of pressure and 400-800V/III ratio.
Preferably, the high temperature n-type doped aluminum nitride layer has a thickness of 30nm to 50nm and is prepared by vapor deposition growth at a temperature of 1100 ℃ to 1200 ℃, a pressure of 50torr to 100torr, and a V/III ratio of 400 to 800.
Preferably, the n-type dopant in the low-temperature n-type doped aluminum nitride layer and the high-temperature n-type doped aluminum nitride layer is silicon; wherein the silicon doping concentration of the low-temperature n-type doped aluminum nitride layer is 10 18 cm -3 ～10 19 cm -3 The silicon doping concentration of the high-temperature n-type doped aluminum nitride layer is 10 17 cm -3 ～10 18 cm -3 。
Preferably, the thickness of the low-temperature undoped aluminum nitride layer is 50nm to 100nm, and the low-temperature undoped aluminum nitride layer is prepared by adopting vapor deposition growth conditions of 800 ℃ to 900 ℃, 30torr to 70torr of pressure and 40-80V/III ratio.
Preferably, the thickness of the high-temperature undoped aluminum nitride layer is 50nm to 100nm, and the high-temperature undoped aluminum nitride layer is prepared by adopting vapor deposition growth conditions of 1100 ℃ to 1200 ℃, 30torr to 70torr and 40-80V/III ratio.
Preferably, the epitaxial structure comprises an undoped aluminum gallium nitride layer, an n-type doped aluminum gallium nitride layer, a multi-quantum well layer, an electron barrier layer, a p-type doped gallium nitride layer and a contact layer which are sequentially stacked; the undoped aluminum gallium nitride layer is arranged on the high-temperature undoped aluminum nitride layer.
Preferably, the MQW layer consists of 5-12 periods of Al x Ga 1-x N/Al y Ga 1-y N is formed; wherein, al x Ga 1-x N is a well layer, and x is more than 0 and less than 0.2; al (aluminum) y Ga 1-y N is a barrier layer, and y is more than 0.4 and less than 0.8.
Preferably, the thickness of the p-type doped gallium nitride layer is 30nm to 200nm, and the p-type doped gallium nitride layer is prepared by adopting the meteorological deposition growth condition that the temperature is 950 ℃ to 1050 ℃ and the pressure is 50torr to 300 torr; and has a magnesium doping concentration of 10 19 cm -3 ～10 20 cm -3 In the meantime.
In a second aspect, the present application provides a semiconductor device comprising the silicon-based epitaxial wafer of the first aspect.
Compared with the prior art, the beneficial effects of the application are that: according to the semiconductor device, the dislocation density of the silicon-based epitaxial wafer in the semiconductor device is effectively reduced by adopting the silicon-based epitaxial wafer optimized by the buffer structure, so that the surface smoothness and the crystal quality of the silicon-based epitaxial wafer are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments or the prior art descriptions will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.
Fig. 1 is a cross-sectional view of a silicon-based epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a silicon-based epitaxial wafer according to embodiment 1 of the present invention.
Description of reference numerals:
a 10-silicon-based substrate;
20-buffer structure, 21-low temperature n-type doped aluminum nitride layer, 22-low temperature undoped aluminum nitride layer, 23-high temperature n-type doped aluminum nitride layer, 24-high temperature undoped aluminum nitride layer;
30-epitaxial structure, 31-undoped aluminum gallium nitride layer, 32-n type doped aluminum gallium nitride layer, 33-multi-quantum well layer, 34-electron barrier layer, 35-p type doped gallium nitride layer and 36-contact layer.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below by referring to the drawings are exemplary and intended to explain the embodiments of the present invention and are not to be construed as limiting the present invention.
In the description of the embodiments of the present invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings, which is only for convenience in describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element so indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless specifically limited otherwise.
In the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly, e.g., as fixed or detachable connections or as an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the embodiments of the present invention can be understood by those of ordinary skill in the art according to specific situations.
As shown in fig. 1, the present application provides a semiconductor device including a silicon-based epitaxial wafer. The silicon-based epitaxial wafer comprises a silicon-based substrate 10, an epitaxial structure 30 and a buffer structure 20 arranged between the silicon-based substrate 10 and the epitaxial structure 30; the buffer structure 20 is used to reduce lattice mismatch between the silicon-based substrate 10 and the epitaxial structure 30, so as to reduce crystal dislocation density and improve crystal quality. Specifically, the buffer structure 20 includes a low-temperature n-type doped aluminum nitride layer 21, a low-temperature undoped aluminum nitride layer 22, a high-temperature n-type doped aluminum nitride layer 23, and a high-temperature undoped aluminum nitride layer 24, which are sequentially stacked from the silicon-based substrate 10 toward one side of the epitaxial structure 30; the low-temperature n-type doped aluminum nitride layer 21 and the high-temperature n-type doped aluminum nitride layer 23 adopt a three-dimensional growth mode, and the low-temperature undoped aluminum nitride layer 22 and the high-temperature undoped aluminum nitride layer 24 adopt a two-dimensional growth mode.
In some embodiments, during the process of growing the low-temperature n-type doped aluminum nitride layer 21 on the silicon-based substrate 10, a three-dimensional growth mode is adopted, and the low-temperature n-type doped aluminum nitride layer 21 with a thickness of 30nm to 50nm is prepared by vapor deposition growth conditions of a growth temperature of 800 ℃ to 900 ℃, a growth pressure of 50torr to 100torr, and a v/iii ratio during growth of 400 to 800. Wherein the n-type dopant in the low-temperature n-type doped aluminum nitride layer 21 is silicon with a doping concentration of 10 18 cm -3 ～10 19 cm -3 。
In some embodiments, the low-temperature undoped aluminum nitride layer 22 is grown on the low-temperature n-type doped aluminum nitride layer 21 in a two-dimensional growth mode, and the low-temperature undoped aluminum nitride layer 22 with a thickness of 50nm to 100nm is prepared by vapor deposition growth conditions of a growth temperature of 800 ℃ to 900 ℃, a growth pressure of 30torr to 70torr, and a v/iii ratio during growth of 40to 80.
In some embodiments, during the growth of the high temperature n-type doped aluminum nitride layer 23 on the low temperature undoped aluminum nitride layer 22, the high temperature n-type doped aluminum nitride layer 23 is prepared to a thickness of 30nm to 50nm in a three-dimensional growth mode, and specifically by vapor deposition growth conditions at a growth temperature of 1100 ℃ to 1200 ℃, a growth pressure of 50torr to 100torr, and a v/iii ratio during growth of 400 to 800. Wherein the n-type dopant in the high-temperature n-type doped aluminum nitride layer 23 is silicon, and the doping concentration of the silicon is 10 17 cm -3 ～10 18 cm -3 。
In some embodiments, the high temperature undoped aluminum nitride layer 24 is grown on the high temperature n-type doped aluminum nitride layer 23 in a two-dimensional growth mode and is prepared to a thickness of 50nm to 100nm by vapor deposition growth conditions at a growth temperature of 1100 ℃ to 1200 ℃, a growth pressure of 30torr to 70torr, and a v/iii ratio during growth of 40to 80.
In some embodiments, the epitaxial structure 30 includes an undoped aluminum gallium nitride layer 31, an n-type doped aluminum gallium nitride layer 32, a multiple quantum well layer 33, an electron blocking layer 34, a p-type doped gallium nitride layer 35, and a contact layer 36, which are sequentially stacked; the undoped aluminum gallium nitride layer 31 is disposed on the high temperature undoped aluminum nitride layer 24.
In some embodiments, during the growth of the undoped aluminum gallium nitride layer 31 on the high temperature undoped aluminum nitride layer 24, the undoped aluminum gallium nitride layer 31 with a thickness of 1000nm to 3000nm is prepared by vapor deposition growth conditions with a growth temperature of 1050 ℃ to 1200 ℃ and a growth pressure of 50torr to 100 torr. Wherein, the aluminum component in the undoped aluminum gallium nitride layer 31 is between 0.3 and 0.8.
In some embodiments, during the process of growing the n-type doped aluminum gallium nitride layer 32 on the undoped aluminum gallium nitride layer 31, the n-type doped aluminum gallium nitride layer with a thickness of 1000nm to 3000nm is prepared by vapor deposition growth conditions with a growth temperature of 1100 ℃ to 1200 ℃ and a growth pressure of 50torr to 100 torr. Wherein the n-type doping in the n-type doped AlGaN layer 32The impurity agent is silicon with the doping concentration of 10 19 cm -3 ～10 20 cm -3 (ii) a The aluminum component in the n-type doped aluminum gallium nitride layer 32 is between 0.2 and 0.6.
In some embodiments, the MQW layer 33 consists of 5 to 12 periods of Al x Ga 1-x N/Al y Ga 1-y N is formed; wherein, al x Ga 1-x N is a well layer, and x is more than 0 and less than 0.2; al (Al) y Ga 1-y N is a barrier layer, and y is more than 0.4 and less than 0.8. In the process of growing the multi-quantum well layer 33 on the n-type aluminum-gallium-nitrogen-doped layer 32, the single-period Al with the thickness of 3nm to 5nm is prepared by vapor deposition growth conditions with the growth temperature of 1000 ℃ to 1100 ℃ and the growth pressure of 40torr to 80torr x Ga 1-x An N well layer; and preparing single-period Al with the thickness of 10 nm-20 nm by vapor deposition growth conditions of the growth temperature of 1000-1200 ℃ and the growth pressure of 40-60 torr y Ga 1-y And N barrier layers.
In some embodiments, the electron blocking layer 34 is prepared to a thickness of 20nm to 100nm during the growth of the electron blocking layer 34 on the mqw layer 33, specifically by vapor deposition growth conditions at a growth temperature of 1000 ℃ to 1100 ℃ and a growth pressure of 50torr to 100 torr. Wherein, the aluminum component in the electron blocking layer 34 is between 0.1 and 0.5.
In some embodiments, the p-type doped gallium nitride layer 35 with a thickness of 30nm to 200nm is prepared by vapor deposition growth conditions at a growth temperature of 950 ℃ to 1050 ℃ and a growth pressure of 50torr to 300torr during growth of the p-type doped gallium nitride layer 35 on the electron blocking layer 34. Wherein the p-type dopant in the p-type doped GaN layer 35 is Mg, and the Mg doping concentration is 10 19 cm -3 ～10 20 cm -3 In between.
In some embodiments, the contact layer 36 is grown on the p-type doped gallium nitride layer 35 by vapor deposition growth at a growth temperature of 1000 ℃ to 1100 ℃ and a growth pressure of 50torr to 100torr to form the contact layer 36 with a thickness of 10nm to 50 nm. Wherein the aluminum composition in the contact layer 36 is between 0.1 and 0.3.
Example 1
Referring to fig. 1, the silicon-based epitaxial wafer of the present embodiment includes a silicon-based substrate 10, a buffer structure 20, and an epitaxial structure 30. Specifically, the buffer structure 20 includes a low-temperature n-type doped aluminum nitride layer 21, a low-temperature undoped aluminum nitride layer 22, a high-temperature n-type doped aluminum nitride layer 23, and a high-temperature undoped aluminum nitride layer 24, which are sequentially stacked from the silicon-based substrate 10 toward one side of the epitaxial structure 30; the low-temperature n-type doped aluminum nitride layer 21 and the high-temperature n-type doped aluminum nitride layer 23 adopt a three-dimensional growth mode, and the low-temperature undoped aluminum nitride layer 22 and the high-temperature undoped aluminum nitride layer 24 adopt a two-dimensional growth mode. The epitaxial structure 30 comprises an undoped aluminum gallium nitride layer 31, an n-type doped aluminum gallium nitride layer 32, a multi-quantum well layer 33, an electron barrier layer 34, a p-type doped gallium nitride layer 35 and a contact layer 36 which are sequentially stacked; the undoped aluminum gallium nitride layer 31 is disposed on the high temperature undoped aluminum nitride layer 24.
Specifically, the thickness of the low-temperature n-type doped aluminum nitride layer 21 is 30nm, and the silicon doping concentration is 5 × 10 18 cm -3 (ii) a The thickness of the low-temperature undoped aluminum nitride layer 22 is 70nm; the thickness of the high-temperature n-type doped aluminum nitride layer 23 is 30nm, and the silicon doping concentration is 6 multiplied by 10 17 cm -3 (ii) a The thickness of the high-temperature undoped aluminum nitride layer 34 is 70nm; the thickness of the undoped aluminum gallium nitride layer 31 is 1000nm, and the aluminum component is 0.3; the n-type doped AlGaN layer 32 has a thickness of 1000nm and a silicon doping concentration of 10 19 cm -3 The aluminum component is 0.2; the MQW layer 33 is composed of 5 periods of Al x Ga 1-x N/Al y Ga 1-y N is formed; single period of Al x Ga 1-x The N well layer has a thickness of 3nm and a single period of Al y Ga 1-y The thickness of the N barrier layer is 10nm; the thickness of the electron blocking layer 34 is 20nm, and the aluminum component is 0.1; the thickness of the p-type doped gallium nitride layer 35 is 30nm, and the magnesium doping concentration is 10 19 cm -3 (ii) a The contact layer 36 was 10nm thick with an aluminum composition of 0.1.
As shown in fig. 2, the method for preparing the silicon-based epitaxial wafer of the present embodiment includes the following steps:
s101, providing a silicon-based substrate along a <111> crystal orientation, and carrying out in-situ annealing treatment at 1000-1200 ℃ in a hydrogen atmosphere in a vapor phase epitaxial growth technology, wherein the pressure range is 150 Torr-500 Torr, and the time is 5-10 minutes.
S102, growing a buffer layer structure on the silicon-based substrate, wherein the buffer layer structure comprises a low-temperature n-type doped aluminum nitride layer, a low-temperature undoped aluminum nitride layer, a high-temperature n-type doped aluminum nitride layer and a high-temperature undoped aluminum nitride layer which are sequentially stacked from the silicon-based substrate to one side of the epitaxial structure.
Specifically, firstly, growing a low-temperature n-type doped aluminum nitride layer on a silicon-based substrate, adopting a three-dimensional growth mode, and specifically preparing the low-temperature n-type doped aluminum nitride layer with the thickness of 30nm under the vapor deposition growth conditions that the growth temperature is 800 ℃, the growth pressure is 80torr, and the V/III ratio during growth is 500. Wherein the n-type dopant in the low-temperature n-type doped aluminum nitride layer is silicon with a doping concentration of 5 × 10 18 cm -3 ；
Secondly, growing a low-temperature undoped aluminum nitride layer on the low-temperature n-type doped aluminum nitride layer, and preparing the low-temperature undoped aluminum nitride layer with the thickness of 70nm by adopting a two-dimensional growth mode and specifically under the vapor deposition growth conditions that the growth temperature is 850 ℃, the growth pressure is 30torr and the V/III ratio during growth is 50;
and growing a high-temperature n-type doped aluminum nitride layer on the low-temperature undoped aluminum nitride layer, and preparing the high-temperature n-type doped aluminum nitride layer with the thickness of 30nm by adopting a three-dimensional growth mode and specifically under the vapor deposition growth conditions that the growth temperature is 1100 ℃, the growth pressure is 80torr and the V/III ratio during growth is 500. Wherein the n-type dopant in the high-temperature n-type doped aluminum nitride layer is silicon with a doping concentration of 5 × 10 17 cm -3 ；
And finally, growing a high-temperature undoped aluminum nitride layer on the high-temperature n-type doped aluminum nitride layer, and preparing the high-temperature undoped aluminum nitride layer with the thickness of 70nm by adopting a two-dimensional growth mode and specifically under the vapor deposition growth conditions that the growth temperature is 1150 ℃, the growth pressure is 30torr and the V/III ratio during growth is 50.
S103, growing an undoped aluminum gallium nitride layer on the high-temperature undoped aluminum nitride layer, and specifically preparing the undoped aluminum gallium nitride layer with the thickness of 1000nm by vapor deposition growth conditions of the growth temperature of 1050 ℃ and the growth pressure of 50 torr; wherein the aluminum component in the undoped aluminum gallium nitride layer is 0.3.
S104, growing an n-type doped aluminum gallium nitrogen layer on the undoped aluminum gallium nitrogen layer, and specifically preparing the n-type doped aluminum gallium nitrogen layer with the thickness of 1000nm through vapor deposition growth conditions of the growth temperature of 1100 ℃ and the growth pressure of 50 torr; wherein the doping concentration of silicon is 10 19 cm -3 The aluminum component was 0.2.
S105, growing Al on the n-type doped aluminum gallium nitride layer for 5 periods x Ga 1-x N/Al y Ga 1-y The multiple quantum well layer composed of N is prepared into single-period Al with the thickness of 3nm by vapor deposition growth conditions of the growth temperature of 1000 ℃ and the growth pressure of 40torr x Ga 1-x An N well layer; and preparing single-period Al with the thickness of 10nm by vapor deposition growth conditions with the growth temperature of 1000 ℃ and the growth pressure of 40torr y Ga 1-y And an N barrier layer.
S106, growing the electron barrier layer on the multi-quantum well layer, specifically preparing the electron barrier layer with the thickness of 20nm under the vapor deposition growth condition that the growth temperature is 1000 ℃ and the growth pressure is 50 torr; wherein the aluminum component in the electron blocking layer is 0.1.
S107, growing the p-type doped gallium nitride layer on the electron blocking layer process, and specifically preparing the p-type doped gallium nitride layer with the thickness of 30nm through the meteorological deposition growth condition that the growth temperature is 950 ℃ and the growth pressure is 50 torr; wherein the doping concentration of magnesium is 10 19 cm -3 。
S108, growing a contact layer on the p-type doped gallium nitride layer, specifically preparing the contact layer with the thickness of 10nm under the meteorological deposition growth condition that the growth temperature is 1000 ℃ and the growth pressure is 50 torr; wherein the aluminum component is 0.1.
And S109, after the epitaxial structure growth is finished, reducing the temperature of the reaction cavity, annealing in a nitrogen atmosphere, wherein the annealing temperature range is 650-850 ℃, annealing for 5-15 minutes, and finishing the epitaxial wafer growth at room temperature.
Example 2
Referring to fig. 1, the difference between the present embodiment and embodiment 1 is: the thickness of the low-temperature n-type doped aluminum nitride layer 31 is 50nm, and the silicon doping concentration is 10 18 cm -3 (ii) a The thickness of the low-temperature undoped aluminum nitride layer 33 is 50nm; the thickness of the high-temperature n-type doped aluminum nitride layer 23 is 50nm, and the silicon doping concentration is 10 17 cm -3 (ii) a The thickness of the high-temperature undoped aluminum nitride layer 24 is 50nm; the thickness of the undoped aluminum gallium nitride layer 31 is 1500nm, and the aluminum component is 0.5; the n-type doped AlGaN layer 32 has a thickness of 1500nm and a silicon doping concentration of 5 × 10 19 cm -3 The aluminum component is 0.4; the MQW layer 33 is composed of 8 periods of Al x Ga 1-x N/Al y Ga 1-y N is formed; single period Al x Ga 1-x The N well layer has a thickness of 4nm and a single period of Al y Ga 1-y The thickness of the N barrier layer is 15nm; the thickness of the electron blocking layer 34 is 50nm, and the aluminum component is 0.3; the p-type doped gallium nitride layer 35 has a thickness of 100nm and a magnesium doping concentration of 5 × 10 19 cm -3 (ii) a The contact layer 36 has a thickness of 30nm and an aluminum composition of 0.15. It should be noted that, in the preparation steps, the relevant process parameters are adjusted according to actual needs, and the silicon-based epitaxial wafer preparation process of the embodiment is not described herein again.
Comparative example 1
The difference between the silicon-based epitaxial wafer of this embodiment and embodiment 1 is the specific structure of the buffer structure, and the buffer structure of this embodiment adopts a conventional structure, specifically, an aluminum nitride/aluminum gallium nitrogen superlattice structure. And growing a buffer structure on the silicon-based substrate, specifically preparing the buffer structure with the thickness of 200nm by using a meteorological deposition growth condition that the growth temperature is 1100 ℃, the growth pressure is 50torr and the V/III ratio during growth is 200.
The measurement data of the relevant optical parameters as shown in table 1 were formed by performing the measurement of the relevant experimental data for example 1, example 2 and comparative example 1. As can be seen from table 1, in example 1 and example 2, the electroluminescence intensity and the light output efficiency are improved in comparison with comparative example 1 under the irradiation of the ultraviolet light, that is, the electroluminescence intensity and the light output efficiency can be improved by optimizing the buffer structure in example 1 and example 2. The specific reasons are that:
1. the low-temperature n-type doped aluminum nitride layer and the high-temperature n-type doped aluminum nitride layer can promote the three-dimensional island growth of aluminum nitride, the three-dimensional island aluminum nitride layer can block the extension of threading dislocation, silicon is doped in the growth process, the healing process of the aluminum nitride island can be delayed, the tensile stress formed in the healing process can be weakened, the defect inhibition effect can be enhanced, the silicon doping can play a role of a mask, the dislocation is inhibited under the mask, and the dislocation in the aluminum nitride layer is deflected and annihilated; and the high-temperature n-type doped aluminum nitride layer grows three-dimensionally at high temperature again, so that the dislocation density formed in the healing process of the low-temperature aluminum nitride island is reduced, the crystal quality of the whole aluminum nitride is improved by increasing the temperature, and the doping concentration of silicon can be reduced because the dislocation is mostly inhibited in the low-temperature aluminum nitride layer and is lower than that of the low-temperature n-type doped aluminum nitride layer.
2. The low-temperature undoped aluminum nitride layer and the high-temperature undoped aluminum nitride layer enable the low-temperature aluminum nitride island to be healed, fill the three-dimensional island-shaped low-temperature aluminum nitride layer and reduce the surface roughness of the aluminum nitride; and the high temperature undoped aluminum nitride layer improves the crystal quality of the bulk aluminum nitride by raising the temperature.
TABLE 1 measurement data of optical parameters related to example 1, example 2 and comparative example 1
Example 3
Referring to fig. 1, the difference between the present embodiment and embodiment 1 is: the thickness of the low-temperature n-type doped aluminum nitride layer 21 is 50nm, and the silicon doping concentration is 10 19 cm -3 (ii) a The low temperature undoped aluminum nitride layer22 is 100nm thick; the thickness of the high-temperature n-type doped aluminum nitride layer 23 is 50nm, and the silicon doping concentration is 10 18 cm -3 (ii) a The thickness of the high-temperature undoped aluminum nitride layer 24 is 100nm; the thickness of the undoped aluminum gallium nitride layer 31 is 3000nm, and the aluminum component is 0.5; the n-type doped AlGaN layer 32 has a thickness of 3000nm and a silicon doping concentration of 10 20 cm -3 The aluminum component is 0.6; the MQW layer 33 consists of 10 periods of Al x Ga 1-x N/Al y Ga 1-y N is formed; single period Al x Ga 1-x The N well layer has a thickness of 5nm and a single period of Al y Ga 1-y The thickness of the N barrier layer is 20nm; the thickness of the electron blocking layer 34 is 100nm, and the aluminum component is 0.5; the p-type doped gallium nitride layer 35 has a thickness of 200nm and a magnesium doping concentration of 10 20 cm -3 (ii) a The contact layer 36 was 30nm thick with an aluminum composition of 0.3. It should be noted that, in the preparation steps, relevant process parameters are correspondingly adjusted according to actual needs, and the preparation process of the silicon-based epitaxial wafer in this embodiment is not described herein again.
Comparative example 2
The silicon-based epitaxial wafer of the present example is different from comparative example 1 in that: the buffer structure is grown on a silicon-based substrate, and the buffer structure with the thickness of 300nm is prepared by the meteorological deposition growth conditions that the growth temperature is 1200 ℃, the growth pressure is 100torr and the V/III ratio during growth is 500.
The measurement data of the relevant optical parameters as shown in table 2 were formed by performing the measurement of the relevant experimental data for example 3 and comparative example 2. As can be seen from table 2, in example 3, the electroluminescent intensity and the light output efficiency are improved in comparison with comparative example 2 under the irradiation of the ultraviolet light, that is, the electroluminescent intensity and the light output efficiency can be improved by optimizing the buffer structure in example 3. The specific reasons are that:
1. the low-temperature n-type doped aluminum nitride layer and the high-temperature n-type doped aluminum nitride layer can promote the three-dimensional island-shaped growth of aluminum nitride, the three-dimensional island-shaped aluminum nitride layer can block the extension of threading dislocation, silicon is doped in the growth process, the healing process of the aluminum nitride island can be delayed, the tensile stress formed in the healing process can be weakened, the defect inhibiting effect can be enhanced, the silicon doping can play a role of a mask, the dislocation is inhibited under the mask, and the dislocation in the aluminum nitride layer is deflected and annihilated; and the high-temperature n-type doped aluminum nitride layer grows three-dimensionally at high temperature again, so that the dislocation density formed in the healing process of the low-temperature aluminum nitride island is reduced, the crystal quality of the whole aluminum nitride is improved by increasing the temperature, and the doping concentration of silicon can be reduced because the dislocation is mostly inhibited in the low-temperature aluminum nitride layer and is lower than that of the low-temperature n-type doped aluminum nitride layer.
2. The low-temperature undoped aluminum nitride layer and the high-temperature undoped aluminum nitride layer enable the low-temperature aluminum nitride island to be healed, fill the three-dimensional island-shaped low-temperature aluminum nitride layer and reduce the surface roughness of the aluminum nitride; and the high temperature undoped aluminum nitride layer improves the crystal quality of the bulk aluminum nitride by raising the temperature.
TABLE 2 measurement data of optical parameters related to example 3 and comparative example 2
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not intended to limit the present invention, and any modifications, equivalents, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of the present invention.
Claims (10)
1. A silicon-based epitaxial wafer, comprising:
a silicon-based substrate;
an epitaxial structure;
the buffer structure is arranged between the silicon-based substrate and the epitaxial structure and is used for reducing lattice mismatch between the silicon-based substrate and the epitaxial structure;
the buffer structure comprises a low-temperature n-type doped aluminum nitride layer, a low-temperature undoped aluminum nitride layer, a high-temperature n-type doped aluminum nitride layer and a high-temperature undoped aluminum nitride layer which are sequentially laminated from the silicon-based substrate to one side of the epitaxial structure; the low-temperature n-type doped aluminum nitride layer and the high-temperature n-type doped aluminum nitride layer adopt a three-dimensional growth mode, and the low-temperature undoped aluminum nitride layer and the high-temperature undoped aluminum nitride layer adopt a two-dimensional growth mode.
2. The silicon-based epitaxial wafer of claim 1 wherein the low temperature n-type doped aluminum nitride layer has a thickness of 30nm to 50nm and is prepared using vapor deposition growth conditions at a temperature of 800 ℃ to 900 ℃, a pressure of 50torr to 100torr, and a v/iii ratio of 400 to 800.
3. The silicon-based epitaxial wafer of claim 1 wherein the high temperature n-type doped aluminum nitride layer has a thickness of 30nm to 50nm and is prepared using vapor deposition growth conditions at a temperature of 1100 ℃ to 1200 ℃, a pressure of 50torr to 100torr, and a v/iii ratio of 400 to 800.
4. The silicon-based epitaxial wafer of claim 2 or 3, wherein the n-type dopant in the low temperature n-type doped aluminum nitride layer and the high temperature n-type doped aluminum nitride layer is silicon; wherein the silicon doping concentration of the low-temperature n-type doped aluminum nitride layer is 10 18 cm -3 ～10 19 cm -3 The silicon doping concentration of the high-temperature n-type doped aluminum nitride layer is 10 17 cm -3 ～10 18 cm -3 。
5. The silicon-based epitaxial wafer of claim 1 wherein the low temperature undoped aluminum nitride layer has a thickness of 50nm to 100nm and is prepared using vapor deposition growth conditions at a temperature of 800 ℃ to 900 ℃, a pressure of 30torr to 70torr, and a v/iii ratio of 40to 80.
6. The silicon-based epitaxial wafer of claim 1, wherein the high temperature undoped aluminum nitride layer has a thickness of 50nm to 100nm and is prepared by vapor deposition growth at a temperature of 1100 ℃ to 1200 ℃, a pressure of 30torr to 70torr, and a v/iii ratio of 40to 80.
7. The silicon-based epitaxial wafer of claim 1, wherein the epitaxial structure comprises an undoped aluminum gallium nitride layer, an n-type doped aluminum gallium nitride layer, a multi-quantum well layer, an electron blocking layer, a p-type doped gallium nitride layer and a contact layer, which are sequentially stacked; the undoped aluminum gallium nitride layer is arranged on the high-temperature undoped aluminum nitride layer.
8. The silicon-based epitaxial wafer of claim 7, wherein the MQW layer consists of 5-12 periods of Al x Ga 1-x N/Al y Ga 1-y N is formed; wherein, al x Ga 1-x N is a well layer, and x is more than 0 and less than 0.2; al (Al) y Ga 1-y N is a barrier layer, and y is more than 0.4 and less than 0.8.
9. The silicon-based epitaxial wafer of claim 7 wherein the p-type doped gallium nitride layer has a thickness of 30nm to 200nm and is prepared by vapor deposition growth at a temperature of 950 ℃ to 1050 ℃ and a pressure of 50torr to 300 torr; and has a Mg doping concentration of 10 19 cm -3 ～10 20 cm -3 In the meantime.
10. A semiconductor device comprising a silicon-based epitaxial wafer according to any one of claims 1 to 9.
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