CN218183310U

CN218183310U - Amplifier, radio frequency chip and electronic device

Info

Publication number: CN218183310U
Application number: CN202220767563.3U
Authority: CN
Inventors: 刘石生; 黄伟
Original assignee: Shenzhen Jingzhun Communication Technology Co ltd
Current assignee: Shenzhen Jingzhun Communication Technology Co ltd
Priority date: 2022-04-01
Filing date: 2022-04-01
Publication date: 2022-12-30
Anticipated expiration: 2032-04-01

Abstract

The embodiment of the application discloses an amplifier, a radio frequency chip and an electronic device. The amplifier includes: the field effect transistor comprises a drain electrode, a grid electrode and a source electrode, and is used for signal amplification; the first end of the drain electrode matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain electrode matching circuit is connected with the radio frequency signal output end; the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio-frequency signal input end; the source electrode feedback circuit is connected with the source electrode of the field effect transistor; the drain matching circuit comprises a first low-coupling inductance pair, and the first low-coupling inductance pair is an inductance pair with opposite induction magnetic fields. The amplifier and the radio frequency chip in the embodiment of the application have the advantages of low power consumption, small size and low cost.

Description

Amplifier, radio frequency chip and electronic device

Technical Field

The application relates to the technical field of electronics, in particular to an amplifier, a radio frequency chip and an electronic device.

Background

With the development of communication technology, especially the emergence of 5G technology, high frequency wireless communication technology is becoming an important development direction of wireless communication.

The performance of the amplifiers can have a significant impact on the performance of the rf transceiver system. Therefore, high frequency wireless communication technology puts higher demands on the performance of the amplifier, such as integration, noise performance, power consumption, and the like.

The existing radio frequency or high frequency amplifier chip is mostly composed of elements such as transistors, lumped parameter element inductors, lumped parameter element capacitors, resistors, microstrip lines and the like. In the element, an inductor, a microstrip line, a capacitor, etc. may generate electromagnetic radiation and other induced magnetic or electric fields, etc. due to signal excitation, and these physical fields may affect the arrangement and normal operation of other elements. In designing or manufacturing an amplifier, in order to solve the problem of electromagnetic compatibility between components, there is a method of achieving electromagnetic compatibility by maintaining a large arrangement pitch of the components, which results in a large size of the amplifier and inconvenience in high-density integration. In addition, electromagnetic radiation, induced magnetic fields or electric fields cause energy losses, sacrificing the performance of the amplifier. In order to realize popularization of high-frequency wireless communication technology, reduction of cost of components and improvement of performance of the components are problems which need to be solved urgently.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem or at least partially solve the technical problem, the application provides an amplifier, a radio frequency chip and an electronic device.

In a first aspect, the present application provides an amplifier comprising:

the field effect transistor comprises a drain electrode, a grid electrode and a source electrode, and is used for amplifying signals;

the first end of the drain electrode matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain electrode matching circuit is connected with the radio frequency signal output end;

the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end;

the source electrode feedback circuit is connected with the source electrode of the field effect transistor;

the drain matching circuit comprises a first low-coupling inductance pair which is an inductance pair with opposite induction magnetic fields.

In an embodiment of the present application, the first low-coupling inductor pair includes:

the first end of the first inductor is connected with the drain electrode of the field effect transistor;

a first end of the second inductor is connected with a drain bias power supply end, and a second end of the second inductor is connected with a second end of the first inductor;

wherein the first inductor and the second inductor have opposite induction magnetic field directions.

In an embodiment of the present application, the drain matching circuit further includes:

a first end of the first capacitor is connected with a second end of the first inductor, and a second end of the first capacitor is connected with the radio-frequency signal output end;

and the first end of the second capacitor is connected with the first end of the second inductor, and the second end of the second capacitor is grounded.

In an embodiment of the present application, the gate matching circuit includes:

the second end of the third inductive unit is connected with the grid electrode of the field effect transistor;

a fourth sensing unit, a first end of the fourth sensing unit being connected to a first end of the third sensing unit;

a first end of the third capacitor is connected with the radio frequency signal input end, and a second end of the third capacitor is connected with a first end of the third inductive unit;

the third inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line, and/or the fourth inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.

In this embodiment, the third inductive unit and the fourth inductive unit are a second low-coupling inductive unit pair, and the second low-coupling inductive unit pair is an inductive pair with opposite inductive magnetic fields.

In this embodiment, the amplifier further includes a gate bias circuit, and the gate bias circuit is connected to the third terminal of the gate matching circuit.

In an embodiment of the present application, the gate bias circuit includes:

and a first end of the fourth capacitor is grounded, a second end of the fourth capacitor is connected with a second end of the fourth inductor, and a second end of the fourth capacitor is also connected with a grid bias power supply end.

In an embodiment of the present application, the source feedback circuit includes:

a fifth inductive unit, wherein a first end of the fifth inductive unit is connected with the source electrode of the field effect transistor, and a second end of the fifth inductive unit is grounded;

wherein, the fifth inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.

In the embodiment of the present application, the source feedback circuit is ground.

a sixth inductive unit, wherein a first end of the sixth inductive unit is connected with the source electrode of the field effect transistor;

a fifth capacitor, wherein a first end of the fifth capacitor is connected to the second end of the sixth inductive unit, the first end of the fifth capacitor is further connected to a source bias power supply terminal, and a second end of the fifth capacitor is grounded; the sixth inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.

In the embodiment of the present application, the gate bias circuit is ground.

a first end of the seventh inductive unit is connected with the source electrode of the field effect transistor;

a sixth capacitor, a first end of the sixth capacitor being connected to the second end of the seventh inductive unit, a second end of the sixth capacitor being grounded;

a first end of the first resistor is connected to the second end of the seventh inductive unit, and a second end of the first resistor is grounded;

wherein, the seventh inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.

In the embodiment of the present application, the first inductor and the second inductor are both spiral inductors and are arranged in the amplifier such that the spiral directions are opposite.

In an embodiment of the present application, the first inductor and the second inductor are arranged in the amplifier in a mirror image arrangement with each other.

In the embodiment of the present application, the first inductor is composed of a first microstrip line, and the first microstrip line is wound into a first spiral pattern, the second inductor is composed of a second microstrip line, and the second microstrip line is wound into a second spiral pattern, wherein the first end and the second end of the first microstrip line are respectively used as the first end and the second end of the first inductor, the first end and the second end of the second microstrip line are respectively used as the first end and the second end of the second inductor, and the second end of the first microstrip line and the second end of the second microstrip line are connected together to enable the first microstrip line and the second microstrip line to form a combined microstrip line.

In an embodiment of the present application, the first and second spiral patterns do not overlap and are adjacent to but at a distance from each other in a direction parallel to the wiring layer of the amplifier.

In the embodiment of the present application, the merged microstrip line is formed by multiple layers of metal materials, where each layer of metal material is located in a different wiring layer of the amplifier.

In an embodiment of the present application, the merged microstrip line is formed by a single layer of metal material, where the single layer of metal material is located in the same or different wiring layers of the amplifier.

In a second aspect, there is provided a radio frequency chip comprising a substrate, and an amplifier as described above on the substrate.

In a third aspect, an electronic device is provided, which includes the rf chip as described above.

An embodiment of the present application provides an amplifier, including: a field effect transistor; the first end of the drain electrode matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain electrode matching circuit is connected with the radio frequency signal output end; the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end; the source electrode feedback circuit is connected with the source electrode of the field effect transistor; the drain matching circuit comprises a first low-coupling inductance pair, and the first low-coupling inductance pair is an inductance pair with opposite induction magnetic fields. In the embodiment of the application, the first low-coupling inductor pair is an inductor pair with opposite directions of the induction magnetic fields, the directions of the induction electric fields generated by the pair of inductors with opposite directions of the induction magnetic fields are also opposite, and the induction electric fields with opposite directions can be partially offset, so that the radiation generated by the induction electric fields is reduced, and the energy loss of the circuit is reduced. In addition, because the induction electric fields are mutually offset, the physical distance of the inductors in the low-coupling inductor pair can be closer, so that the size of the amplifier can be reduced, and the cost is reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.

Fig. 1 to 9 are circuit schematic diagrams of an amplifier in an embodiment of the present application;

FIG. 10 is a schematic diagram of an RF chip in an embodiment of the present application;

fig. 11 is a schematic diagram of the arrangement of a first low coupling inductance pair in an amplifier in an embodiment of the present application;

fig. 12 is a schematic diagram of an electronic device in an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The amplifier provided by the embodiment of the application can be used as an independent component, or can be applied to radio frequency chip or system integration.

As shown in fig. 1, an embodiment of the present application provides an amplifier, including:

a field effect transistor 110, which may be an enhancement mode field effect transistor or a depletion mode field effect transistor, wherein the field effect transistor 110 includes a drain, a gate and a source, the field effect transistor 110 is used for signal amplification,

a drain matching circuit 120, wherein a first end of the drain matching circuit 120 is connected to the drain of the field effect transistor 110, and a second end of the drain matching circuit 120 is connected to a radio frequency signal output end RFOUT;

a gate matching circuit 130, wherein a first end of the gate matching circuit 130 is connected to the gate of the fet 110, and a second end of the gate matching circuit 130 is connected to the radio frequency signal input terminal RFIN;

a source feedback circuit 140 connected to the source of the fet 110;

the drain matching circuit 120 includes a first low-coupling inductor pair 121, where the first low-coupling inductor pair 121 is an inductor pair with opposite directions of an induced magnetic field.

In the field effect transistor in the embodiment of the present application, the three electrodes are a Source electrode (Source, S electrode), a Gate electrode (Gate, G electrode) and a Drain electrode (Drain, D electrode), respectively, for amplifying a radio frequency signal, and details are not repeated herein.

In the embodiment of the present application, the drain matching circuit 120 is configured to match the drain output impedance of the fet 110 to a first target impedance, which is the output impedance of the amplifier rf signal output terminal RFOUT.

In the embodiment of the present application, the gate matching circuit 130 is configured to match the gate input impedance of the fet 110 to a second target impedance, which is the input impedance of the amplifier rf signal input terminal RFIN.

In the embodiment of the present application, as shown in fig. 2, the first low-coupling inductor pair 121 includes:

a first inductor L1, a first end of the first inductor L1 being connected to the drain of the field effect transistor 110;

a first end of the second inductor L2 is connected to a drain bias power supply terminal VD, and a second end of the second inductor L2 is connected to a second end of the first inductor L1;

the first inductor L1 and the second inductor L2 have opposite induction magnetic field directions.

In this embodiment, the first inductor L1 and the second inductor L2 may be planar spiral inductors, and a spiral direction of the first inductor L1 is opposite to a spiral direction of the second inductor L2.

In other embodiments of the present application, the first inductor L1 and the second inductor L2 may also be other structures and physical layouts capable of realizing opposite directions of the induced magnetic field, and are not described herein again.

When the inductor is excited by a signal, an induction magnetic field is generated, the induction magnetic field generates an induction electric field, and the induction electric field generates radiation, so that energy loss is generated. Therefore, an induced magnetic field is present in the first inductor L1 and the second inductor L2, and an energy loss is generated by an induced electric field generated by the induced magnetic field.

In the embodiment of the present application, the directions of the induction magnetic fields of the first inductor L1 and the second inductor L2 are opposite, so that the directions of the induction electric field generated by the induction magnetic field of the first inductor L1 and the induction electric field generated by the induction magnetic field of the second inductor L2 are also opposite, and the two opposite induction electric fields can be partially offset, so that the radiation generated by the induction electric fields is reduced, and the energy loss is reduced.

Because the induced electric field between the first inductor L1 and the second inductor L2 is partially offset, the physical distance between the first inductor L1 and the second inductor L2 can be closer, so that the size of the circuit can be reduced, and the cost can be reduced.

In the embodiment of the present application, the drain matching circuit includes a first low-coupling inductor pair 121, and the first low-coupling inductor pair 121 is an inductor pair with opposite directions of an induction magnetic field, and is respectively a first inductor L1 and a second inductor L2, so that mutual coupling can be reduced, and energy loss can be reduced. In addition, the physical distance between the first inductor L1 and the second inductor L2 can be closer, so that the size of the circuit can be reduced, and the cost can be reduced.

In the embodiment of the present application, as shown in fig. 2, the drain matching circuit 120 further includes:

a first end of the first capacitor C1 is connected with a second end of the first inductor L1, and a second end of the first capacitor C1 is connected with a radio frequency signal output end FROUT;

and a first end of the second capacitor C2 is connected with a first end of the second inductor L2, and a second end of the second capacitor C2 is grounded.

In the embodiment of the present application, the first capacitor C1, the second capacitor C2 and the first low-coupling inductor pair 121 form a matching network, which is used to match the drain output impedance of the fet 110 to a first target impedance.

In this embodiment, the resonant point frequency of the second capacitor C2 is close to or the same as the center frequency of the operating frequency band of the amplifier, and is used to implement the isolation of the rf signal between the amplifier and the drain bias power supply terminal VD, and simultaneously provide the rf signal ground for the first end of the second inductor L2 in the drain matching circuit 120.

As shown in fig. 2, in the embodiment of the present application, the gate matching circuit 130 includes:

a third inductive unit L3, a second end of the third inductive unit L3 being connected to the gate of the fet 110;

a fourth inductive unit L4, a first end of the fourth inductive unit L4 being connected to a first end of the third inductive unit L3;

a third capacitor C3, a first end of the third capacitor C3 is connected to the radio frequency signal input terminal RFIN, and a second end of the third capacitor C3 is connected to the first end of the third inductive unit L3;

the third inductive unit L3 is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line, and/or the fourth inductive unit L4 is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

In the embodiment of the present application, as shown in fig. 2, the amplifier further includes a gate bias circuit 150, and the gate bias circuit 150 is connected to the third terminal of the gate matching circuit 130.

As shown in fig. 2, the gate bias circuit 150 includes:

a first end of the fourth capacitor C4 is grounded, a second end of the fourth capacitor C4 is connected to a second end of the fourth inductor L4, and a second end of the fourth capacitor C4 is further connected to a gate bias power supply terminal VG.

As shown in fig. 2, the third terminal of the gate matching circuit 130 is the second terminal of the fourth inductor L4.

In the embodiment of the present application, as shown in fig. 2, the source feedback circuit 140 includes:

a fifth inductive unit L5, a first end of the fifth inductive unit L5 is connected to the source of the fet 110, and a second end of the fifth inductive unit L5 is grounded;

the fifth sensing unit L5 is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

In the embodiment of the present application, by adjusting the parameter of the fifth inductive unit L5, the optimal noise impedance of the fet 110 and the optimal gain matching impedance of the fet 110 may be adjusted to be approximately consistent, so as to reduce noise of the amplifier and improve performance of the amplifier.

In the embodiment of the present application, the third capacitor C3, the fourth capacitor C4, the third inductor L3, and the fourth inductor L4 form an amplifier input matching network, and are used to match the gate input impedance of the field effect transistor 110 to a second target impedance.

In the embodiment of the present application, the resonant point frequency of the fourth capacitor C4 is close to or the same as the center frequency of the working frequency band of the feedback amplifier, and is used for realizing the isolation of the feedback amplifier from the radio frequency signal of the gate bias power supply terminal VG and providing a radio frequency signal ground for the second terminal of the fourth inductor L4.

As shown in fig. 3, in the embodiment of the present application, the source feedback circuit 140 is a ground.

In a specific application scenario of the embodiment of the present application, in the source feedback circuit 140, the source feedback circuit 140 is a ground, that is, the source of the fet 110 may be directly grounded, as shown in fig. 3.

In the embodiment shown in fig. 2 and 3, the gate bias voltage VG is provided to the fet 110 through the gate bias power source terminal VG, and the drain bias voltage VD is provided to the fet 110 through the drain bias power source terminal VD, so as to maintain the normal operation of the fet 110. The rf signal is input through the rf signal input terminal RFIN, passes through the gate matching circuit 130, drives the gate of the fet 110, is amplified by the fet 110, passes through the drain matching circuit 120, and is output through the rf signal output terminal RFOUT.

As shown in fig. 4, in the embodiment of the present application, the source feedback circuit 140 includes:

a sixth inductive unit L6, wherein a first end of the sixth inductive unit L6 is connected to the source of the fet 110;

a fifth capacitor C5, wherein a first end of the fifth capacitor C5 is connected to the second end of the sixth inductive unit L6, the first end of the fifth capacitor C5 is further connected to the source bias power source terminal VS, and a second end of the fifth capacitor C5 is grounded.

The sixth inductive unit L6 is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

In the embodiment of the present application, by adjusting the parameter of the fifth inductive unit L6, the optimal noise impedance of the fet 110 and the optimal gain matching impedance of the fet 110 may be adjusted to be approximately consistent, so as to reduce noise of the amplifier and improve performance of the amplifier.

In the embodiment of the present application, the resonance point frequency of the fifth capacitor C5 is close to or the same as the center frequency of the operating frequency band of the amplifier, and is used to implement the isolation of the amplifier from the radio frequency signal of the source bias power supply terminal VS, and simultaneously provide a radio frequency signal ground for the second terminal of the sixth inductor L6.

As shown in fig. 4, in the embodiment, a gate bias voltage VG is provided to the amplifier through a gate bias power source terminal VG, a drain bias voltage VD is provided to the amplifier through a drain bias power source terminal VD, a source bias voltage VS is provided to the amplifier through a source bias power source terminal VS, a voltage difference between VG and VS is adjusted to be the gate-source bias power source in the normal operating state of the fet 110, a voltage difference between VD and VS is adjusted to be the drain-source bias power source in the normal operating state of the fet 110, and the fet 110 is in the normal operating state. The rf signal is input through the rf signal input terminal RFIN, passes through the gate matching circuit 130, drives the gate of the fet 110 in the amplifier core unit, is amplified by the fet 110, and is output through the rf signal output terminal RFOUT through the drain matching circuit 120.

As shown in fig. 5, the gate bias circuit 150 is ground.

In the embodiments shown in fig. 2 and 3, the gate bias voltage VG needs to be provided, and in the embodiment shown in fig. 4, a single power self-biased amplifier may be used, so that the gate bias voltage VG does not need to be provided.

As shown in fig. 5, in the embodiment of the present application, the source feedback circuit 140 includes:

a seventh inductive unit L7, wherein a first end of the seventh inductive unit L7 is connected to the source of the fet 110;

a sixth capacitor C6, wherein a first end of the sixth capacitor C6 is connected to the second end of the seventh inductive unit L7, and a second end of the sixth capacitor C6 is grounded;

a first end of the first resistor R1 is connected with a second end of the seventh inductive unit L7, and a second end of the first resistor R1 is grounded;

the seventh inductive unit L7 is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

In the embodiment of the present application, by adjusting the parameter of the fifth inductive unit L7, the optimal noise impedance of the fet 110 and the optimal gain matching impedance of the fet 110 may be adjusted to be approximately consistent, so as to reduce noise of the amplifier and improve performance of the amplifier.

In the embodiment of the present application, the sixth capacitor C6 is used to couple the rf signal output by the source of the fet 110 and passing through the seventh inductive unit L7 to ground, so as to reduce energy loss of the source feedback circuit 140.

In the embodiment of the present application, the first resistor R1 is used to raise the source potential of the fet 110, so that the gate-to-source voltage of the fet 110 is a negative value, and the normal operation of the amplifier is maintained.

In the embodiment shown in fig. 5, a drain bias voltage VD is provided to the fet 110 through the drain bias power source terminal VD, and at this time, the drain-source current of the fet 110 flows through the resistor R1 in the source feedback circuit 140 to raise the source potential of the fet 110, so that the gate-source voltage of the fet 110 is negative, thereby maintaining the normal operation of the amplifier. The rf signal is input through the rf signal input terminal RFIN, passes through the gate matching circuit 130, drives the gate of the fet 110, is amplified by the fet 110, passes through the drain matching circuit 120, and is output through the rf signal output terminal RFOUT.

In the embodiment of the present application, as shown in fig. 6 to fig. 9, the third inductive unit L3 and the fourth inductive unit L4 are a second low-coupling inductive pair 131, and the second low-coupling inductive pair 131 is an inductive pair with opposite inductive magnetic fields, where the second low-coupling inductive pair 131 includes a third inductor L3 and a fourth inductor L4.

As described above, the directions of the induced magnetic fields of the third inductor L3 and the fourth inductor L4 are opposite, so that the energy loss can be reduced, the circuit size can be reduced, and the cost can be reduced.

In the embodiment of the present application, the third capacitor C3, the fourth capacitor C4 and the second low-coupling inductor pair 131 form an amplifier input matching network, which is used to match the gate input impedance of the field effect transistor 110 to a second target impedance. The second low-coupling inductor pair 131 can reduce the impedance of the input matching network, which is beneficial to improving the noise performance of the amplifier and increasing the gain of the amplifier.

In the embodiment of the present application, the resonant point frequency of the fourth capacitor C4 is close to or the same as the center frequency of the operating frequency band of the amplifier, and is used for realizing the isolation of the amplifier from the radio frequency signal of the gate bias power supply terminal VG and providing a radio frequency signal ground for the second terminal of the fourth inductor L4.

As in the previous embodiment, the third inductor L3 and the fourth inductor L4 in the gate matching circuit 130 of the amplifier are pairs of inductors with opposite induction magnetic fields, and in this case, the amplifier may also be a self-biased amplifier or an amplifier with a bias power supply provided from the outside.

As shown in fig. 6 and 7, the amplifier is supplied with the gate bias voltage VG from the outside world and the drain bias voltage VD from the outside world.

As shown in fig. 8, the amplifier is supplied with a source bias voltage VS, a drain bias voltage VD, and a gate bias voltage VG from the outside.

As shown in fig. 9, the amplifier is provided with a drain bias voltage VD from the outside, and the source and the gate are self-biased.

In this embodiment, the drain matching circuit 120 of the amplifier includes a first low-coupling inductor pair 121, the gate matching circuit 130 includes a second low-coupling inductor pair 131, and the first low-coupling inductor pair 121 and the second low-coupling inductor pair 131 are inductor pairs with opposite directions of the induced magnetic field, respectively, which can reduce energy loss in the corresponding gate matching circuit 130 and drain matching circuit 120, reduce energy loss of the amplifier, reduce circuit size, and reduce cost.

In the embodiment of the present application, any one of the plurality of inductive units may be one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line. In the plurality of inductive units, part of the inductive units can be inductors, part of the inductive units can be microstrip lines, and part of the inductive units can be the combination of the inductors and the microstrip lines; or all of them are inductors, or all of them are microstrip lines, or all of them are a combination of inductors and microstrip lines, and are not described herein again. A low coupling inductance pair, i.e. an inductance pair with opposite induced magnetic fields, may be a pair of inductances.

In the embodiment of the present application, the power supply bias modes of the amplifier include a single power supply self-bias mode, a dual power supply bias mode, and a triple power supply bias mode, where the single power supply self-bias mode refers to a mode in which only the drain bias voltage VD is provided from the outside, as shown in fig. 5 and 9; the dual power bias means that the drain bias voltage VD and the gate bias voltage VG are supplied from the outside as shown in fig. 2, 3, 6 and 7; the three-power bias means that the drain bias voltage VD, the gate bias voltage VG and the source bias voltage VS are provided from the outside, as shown in fig. 4 and 8. The single power supply is simple in self-bias power supply, the double power supply can exert better power performance, the three power supply biases are beneficial to energy conservation, and a power supply bias mode can be configured according to practical application. The power supply bias mode of the embodiment of the present application can also be used in other circuits, and is not described herein again.

The embodiment of the application also provides a radio frequency chip, which comprises a substrate and the amplifier on the substrate.

As shown in fig. 1, the amplifier includes:

a field-effect transistor (110) is provided,

a drain matching circuit 120, wherein a first end of the drain matching circuit 120 is connected to the drain of the field effect transistor 110, and a second end of the drain matching circuit 120 is connected to the rf signal output end RFOUT;

a gate matching circuit 130, wherein a first terminal of the gate matching circuit 130 is connected to the gate of the fet 110, and a second terminal of the gate matching circuit 130 is connected to the radio frequency signal input terminal RFIN;

a source feedback circuit 140 connected to the source of the fet 110;

the drain matching circuit 120 includes a first low-coupling inductor pair 121, where the first low-coupling inductor pair 121 is an inductor pair with opposite directions of an induction magnetic field.

In the field effect transistor 110 in the embodiment of the present application, the three electrodes are a Source electrode (S), a Gate electrode (Gate, G), and a Drain electrode (Drain, D), which are not described herein again.

In the embodiment of the present application, as shown in fig. 2, the pair of first low-coupling inductors 121 includes:

a first inductor L1, a first end of the first inductor L1 being connected to the drain of the fet 110;

the first inductor L1 and the second inductor L2 have opposite directions of induced magnetic fields.

and a first end of the second capacitor C1 is connected with a first end of the second inductor L2, and a second end of the second capacitor C2 is grounded.

When the inductor is excited by a signal, an induction magnetic field can be generated, an induction electric field can be generated by the induction magnetic field, and an induction eddy current can be generated in the substrate of the chip by the induction electric field, so that energy loss is generated; therefore, there are also induced magnetic fields on the inductor L1 and the inductor L2, and the induced currents generated by the induced magnetic fields generate induced eddy currents in the substrate of the chip, thereby generating energy loss.

In the embodiment of the application, the directions of the induction magnetic fields of the first inductor L1 and the second inductor L2 are opposite, so that the directions of the induction electric fields generated by the induction magnetic fields of the first inductor L1 and the induction electric fields generated by the induction magnetic fields of the second inductor L2 are also opposite, the directions of the induction eddy currents generated by the two opposite induction electric fields are opposite, the induction eddy currents with opposite directions can be partially offset, so that the induction eddy currents are reduced, the generated energy loss is reduced, and the energy loss of the chip matching network is reduced.

Because the induced eddy current generated by the first inductor L1 and the second inductor L2 on the substrate is partially cancelled, the physical distance between the first inductor L1 and the second inductor L2 can be closer, so that the size of the circuit can be reduced, and the cost can be reduced.

In the embodiment of the present application, in the drain matching circuit 120 of the amplifier in the chip, the directions of the induced magnetic fields of the first inductor L1 and the second inductor L2 are opposite, so that the induced eddy current in the substrate can be partially cancelled, and the energy loss is reduced. In addition, the physical distance between the first inductor L1 and the second inductor L2 can be closer, so that the size of a chip can be reduced, and the cost is reduced. Similarly, the directions of the induced magnetic fields of the third inductor L3 and the fourth inductor L4 are opposite, so that the induced eddy currents in the substrate can be partially offset, and the energy loss can be reduced. In addition, the physical distance between the third inductor L3 and the fourth inductor L4 can be closer, which can reduce the size of the chip and reduce the cost.

Similarly, in the embodiment of the present application, the amplifier in the chip may include the second low-coupling inductor pair 131, and the directions of the induced magnetic fields of the third inductor L3 and the fourth inductor L4 are opposite, so that the induced eddy currents in the substrate may be partially cancelled, the energy loss is reduced, the size of the chip can be reduced, and the cost is reduced.

Other specific embodiments of the amplifier in the chip according to the embodiment of the present application are described with reference to the above embodiments and fig. 1 to 9, and are not described herein again.

Therefore, the radio frequency chip in the embodiment of the application has the advantages of low power consumption, small size and low cost.

As shown in fig. 10, the radio frequency chip 1500 may include an amplifier 1501, where the amplifier 1501 may be any of the embodiments of the amplifier described above. One amplifier 1501 may be used alone, or a plurality of amplifiers 1501 may be used in combination. In an example, the radio frequency chip 1500 may include one or more amplifiers 1501.

In embodiments of the amplifier and rf chip that employ low coupling inductance pairs, the layout of the low coupling inductance pairs greatly affects the size of the circuit dimensions. When the inductor is excited by a signal, an induction magnetic field can be generated, an induction electric field can be generated by the induction magnetic field, and the induction electric field can generate radiation, so that energy loss is generated. For example, the induced electric field may generate eddy currents in the circuit medium and electromagnetic radiation in space. If two inductors are arranged close together, mutual coupling between them will occur, which aggravates this loss. The mutual coupling between the two inductors is at least partially reduced by configuring the two inductors of the low coupling inductor pair to generate opposite induction magnetic fields, so that the directions of the induction electric fields caused by the induction magnetic fields of the two inductors are also opposite, and the induction electric fields are partially or completely offset, thereby reducing or eliminating energy loss caused by the induction electric fields, and further enabling the two inductors of the low coupling inductor pair to be arranged at a closer distance so as to further reduce the chip area occupied by the amplifier.

For example, the first inductance L1 and the second inductance L2 of the first low-coupling inductance pair 121 may be disposed to be adjacent to each other and such that the direction of the induced magnetic field generated by the first inductance L1 is opposite to the direction of the induced magnetic field generated by the second inductance L2.

In one example, the first inductor L1 and the second inductor L2 are both spiral inductors, which may be arranged in the amplifier with opposite spiral directions. For example, one inductor spirals clockwise and the other counterclockwise.

In one example, the first inductance L1 and the second inductance L2 are arranged in the amplifier as mirror image arrangements of each other.

Fig. 11 shows a schematic diagram of a first low-coupled inductor pair arrangement in an amplifier according to an embodiment of the present application. Fig. 11 is a schematic diagram of a first low-coupling inductance pair of an amplifier viewed from above from a direction perpendicular to the wiring layers of the amplifier. In one example, the amplifier may be a radio frequency chip.

As shown in fig. 11, the first low-coupled inductor pair 121 includes two inductors respectively composed of a first microstrip line 1214 and a second microstrip line 1215, wherein the first microstrip line 1214 is wound in a first spiral pattern S1, and the second microstrip line 1215 is wound in a second spiral pattern S2. The first end 1211 and the second end 1212 of the first microstrip line 1214 serve as a first end and a second end of the first inductor L1, respectively. The first end 1213 and the second end 1212 of the second microstrip line 1215 serve as the first end and the second end of the second inductance L2, respectively. The second end 1212 of the first microstrip line 1214 and the second end 1212 of the second microstrip line 1215 are connected together to form a common end 1212 of the first inductance L1 and the second inductance L2, and the first microstrip line 1214 and the second microstrip line 1215 form a merged microstrip line. The first end 1211 of the first inductor L1, the first end 1213 of the second inductor L2, and the second ends 1212 of the first inductor L1 and the second inductor L2 are respectively connected to the other parts of the amplifier through connection lines.

The merged microstrip line (first microstrip line/second microstrip line) of the embodiment of the present application may be composed of a single layer or multiple layers of metal materials. In one example, the merged microstrip line is composed of multiple layers of metallic material, where each layer of metallic material is located in a different wiring level of the amplifier. And multiple layers of metal materials in different wiring layers are overlapped together to form a combined microstrip line, and the metal materials of the layers are connected through interlayer through holes. In another example, the merged microstrip line is composed of a single layer of metallic material, which may be located in the same or different wiring layers of the amplifier. For example, a portion of a single layer of metallic material is located in one wiring level and other portions are located in a different one or more wiring levels. Similarly, the single-layer metal materials on different wiring layers are connected through the through holes.

In the example of fig. 11, both spiral patterns S1 and S2 comprise a plurality of turns, it being understood that they may also each comprise one turn, or one may comprise a plurality of turns and the other may comprise a plurality of turns.

As an example, the first microstrip line 1214 and the second microstrip line 1215 may be wound in opposite directions such that the spiral directions of the first spiral pattern S1 and the second spiral pattern S2 are opposite, so that the directions of the induced magnetic fields caused by the currents in the microstrip lines forming the two spiral patterns S1 and S2 are opposite when the first low-coupling inductance pair 121 is in the operating state. For example, one of S1 and S2 is made to have a counterclockwise spiral direction, and the other is made to have a clockwise spiral direction. Here, a direction from the first terminal of the first inductor L1 or the second inductor L2 to the common terminal may be referred to as a spiral direction, or a direction from the common terminal to the first terminal of the first inductor L1 or the second inductor L2 may be referred to as a spiral direction.

In the embodiment of fig. 11, the first microstrip line 1214 is wound in a first spiral pattern S1 in a counterclockwise direction from the first end 1211 to the common end 1212 in an inside-out manner (first inside turn then outside turn), and the second microstrip line 1215 is wound in a second spiral pattern S2 in a clockwise direction from the first end 1213 to the common end 1212 in a likewise inside-out manner (first inside turn then outside turn). It will be appreciated that one may be wound in an inside-out manner, the other in an outside-in (outer turns followed by inner turns) manner, or both in an outside-in manner. It is understood that the microstrip line need not be wound in the inside-out or outside-in direction all the time when wound in the spiral pattern S1 or S2, but may be changed in direction one or more times. For example, first is from inside to outside, halfway is from outside to inside, or vice versa.

In summary, each of the spiral patterns S1 and S2 may wind the microstrip line from the respective first end to the common end in one of the following ways:

from the inside to the outside;

from outside to inside;

a combination of the above two.

In the embodiment of fig. 11, the two spiral patterns S1 and S2 do not overlap and are adjacent but at a distance D in a direction parallel to the wiring layers of the amplifier. In the embodiment of the present application, as described above, since mutual coupling between the two inductors is low, the two spiral patterns S1 and S2 may be arranged as close as possible (but there is no overlapping portion between the two), thereby reducing the circuit size and the cost. In one example, the pitch between the two spiral patterns S1 and S2 (distance D as shown in fig. 11) may be a minimum of about 3 micrometers. The "pitch between two spiral patterns" mentioned herein refers to a distance between microstrip lines of the two spiral patterns that are closest to each other. As shown in FIG. 11, distance D is the distance between adjacent outermost turns of S1 and S2. In practice, the minimum spacing between the two spiral patterns is determined by the chip manufacturing process.

In the example of fig. 11, the first microstrip line 1214 and the second microstrip line 1215 have the same length. That is, the common terminal 1212 is located at a midpoint of the merged microstrip line. It will be appreciated that the common terminal 1212 may also be located at other positions, such as closer to S1 or S2, rather than at the midpoint of the merged microstrip line.

As shown in fig. 11, in this embodiment, the spiral patterns S1 and S2 are arranged in mirror images, and both are mirror images, which are shown in an axisymmetric arrangement in fig. 11. That is, the spiral patterns S1 and S2 have the same configuration, for example, the same number of turns, the microstrip line width, the pitch between adjacent turns, and the like, except that their patterns are opposite (winding manner is opposite), and are in a symmetrical/mirror relationship with respect to a plane perpendicular to the wiring layer located in the middle of the two. S1 and S2 may not be arranged in a mirror image, for example, S1 and S2 have different configurations, for example, S1 and S2 have different turns, microstrip line width or spacing between adjacent turns, etc., as long as the induced magnetic fields of the wound spiral patterns S1 and S2 are opposite in direction.

It is understood that the arrangement of the first spiral pattern S1 and the second spiral pattern S2 in fig. 11 may be interchanged.

In the first low-coupled inductor pair 121 according to the above-mentioned embodiment of the present application, the microstrip lines of the two inductors have a common end and are arranged in two spiral patterns with opposite spiral directions, and when an excitation signal is applied to the first low-coupled inductor pair 121 in an operating state, the excitation signal is shunted to the two spirals (microstrip lines of the two inductors) at the common end, so that the directions of the induced magnetic fields generated by the currents in the two spirals are opposite, thereby at least partially reducing mutual coupling/inductance between the two inductors.

In the above-described inductance pair embodiment, as shown in fig. 7, the inductance pair is arranged in the integrated circuit chip to have three terminals: common terminal 1212, a head end 1211 which is the first branch end of the inductive pair, and a tail end 1213 which is the second branch end of the inductive pair. As previously described, the three terminals of the pair may be connected to a stimulus signal or other circuit portion by leads. For example, a radio frequency excitation signal may be accessed from the common terminal 1212 of the pair of inductors, and the radio frequency excitation signal is shunted to the first microstrip line (first inductor) and the second microstrip line (second inductor) at the common terminal 1212. The radio frequency excitation signal is typically a periodically varying signal, for example a sinusoidal signal. Let the excitation signal switched in at the common port 1212 be i _com ＝I _com Sin ω t. The excitation signal is split into two branches at the common terminal 1212, one of which passes through the common terminal 1212 to the first spiral pattern S1 at the first branch end (head end) 1211, and the other passes through the common terminal 1212 to the second spiral pattern S2 at the second branch end (tail end) 1213. Let the excitation signal in the first spiral pattern S1 be i ₁ (t) the excitation signal in the first spiral pattern S1 is i ₂ (t) if the signal is not reflected, i ₁ (t)+i ₂ (t)＝I _com Sin ω t. If the common terminal is located at the midpoint of the combined microstrip line and S1 and S2 are axisymmetric patterns, the excitation signals in S1 and S2 are identical at any time, i.e., the excitation signals are identical

Excitation signal i in an inductive pair ₁ (t) and i ₂ (t) is a periodically-changing signal, the current magnitude of which periodically changes unevenly, so that the induced magnetic field generated also periodically changes unevenly; the changing magnetic field in turn generates an electric field, thereby generating an electromagnetic wave. When the excitation signals in S1 and S2 are identical, since the spiral directions of S1 and S2 are opposite, the magnitude of the induced magnetic field generated in S1 and the induced magnetic field generated in S2 are identical and the magnetic field direction is opposite at any time, and the directions of the induced electric fields are opposite and the directions are changed periodically. Therefore, the induced magnetic fields generated by S1 and S2 are almost completely cancelled in many regions and partially cancelled in some regions, so that the corresponding electric fields or electromagnetic waves caused by the induced magnetic fields are also cancelled, thereby reducing the loss of the inductive pair.

If the common end is not located at the middle point of the combined microstrip line, or S1 and S2 are patterns with different configurations, it may not be guaranteed that excitation signals in S1 and S2 are completely the same, so that the degree of mutual cancellation of the induced magnetic fields of S1 and S2 is reduced compared with the case that the excitation signals in S1 and S2 are completely the same, but the induced magnetic fields generated by S1 and S2 at any time still partially cancel each other, and the electromagnetic radiation intensity is weakened mutually, so that the loss of the inductance pair is reduced to some extent.

It should be noted that, theoretically, an inductance pair having three ports (a common terminal, a leading end of the merged microstrip line as a first branch terminal, and a trailing end of the merged microstrip line as a second branch terminal) as described above is a passive lossless network, and since the passive network has reciprocity, the loss of the inductance pair and its transmission characteristics are reciprocal regardless of which of the three ports an excitation signal is input from.

The first low-coupling inductor pair 121 formed by the first inductor L1 and the second inductor L2 in the amplifier may adopt the low-coupling inductor pair arrangement as described above. The above description of the low-coupling inductance pairs applies to all low-coupling inductance pairs referred to herein, and for the sake of brevity, are not repeated herein elsewhere.

In the above-described embodiments of the amplifier, the above-described pair of low coupling inductors is used, which provides the following advantages for the amplifier of the present application: by configuring the two inductors constituting the inductor pair such that their respective induced magnetic fields are opposite in direction, the inductor pair is a low-coupling inductor pair, and the loss of the amplifier input matching circuit can be reduced. In addition, the coupling between the two inductors forming the low-coupling inductor pair and the radiation ranges of the induction electric field and the induction magnetic field of the inductors can be reduced in this way, so that the inductors and other components are arranged closer to each other, and the circuit size is further reduced.

The embodiment of the application also provides an electronic device, the electronic device comprises the radio frequency chip, and the radio frequency chip comprising the amplifier embodiment of the application can be used in the electronic device.

As shown in fig. 12, the electronic device 1600 includes the rf chip 1500 shown in fig. 10. The electronic apparatus 1600 may be a wireless device or any other electronic apparatus that may use an amplifier.

A wireless device may be a User Equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a base station, etc. The wireless device may also be a cellular phone, a smart phone, a tablet, a wireless modem, a Personal Digital Assistant (PDA), a handheld device, a laptop, a smartbook, a netbook, a cordless phone, a Wireless Local Loop (WLL) station, a bluetooth device, etc. The wireless device may be capable of communicating with a wireless communication system, may be capable of receiving signals from a broadcast station, signals from one or more satellites, and the like. The wireless device may support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter wave, etc.).

The embodiment of the application provides an amplifier, a radio frequency chip and an electronic device, the amplifier includes: a field effect transistor; the first end of the drain electrode matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain electrode matching circuit is connected with the radio frequency signal output end; the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end; the source electrode feedback circuit is connected with the source electrode of the field effect transistor; the drain matching circuit comprises a first low-coupling inductance pair, and the first low-coupling inductance pair is an inductance pair with opposite induction magnetic fields. In the embodiment of the application, the first low-coupling inductor pair is an inductor pair with opposite directions of the induction magnetic fields, the directions of the induction electric fields generated by the pair of inductors with opposite directions of the induction magnetic fields are also opposite, and the induction electric fields with opposite directions can be partially offset, so that the radiation generated by the induction electric fields is reduced, and the energy loss of the circuit is reduced. In addition, because the induction electric fields are mutually offset, the physical distance of the inductors in the low-coupling inductor pair can be closer, so that the size of the amplifier can be reduced, and the cost is reduced.

The amplifiers in the embodiments of the present application may be used independently, or may be used in cascade of multiple stages, or may be applied to an integrated system, or may be applied to a multi-function chip. The radio frequency chip of the embodiment of the present application may also include an independently used amplifier, or may include a plurality of amplifiers used in cascade, or may include a plurality of independently used amplifiers.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to requirements, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to corresponding processes in the context, and are not described herein again.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described or illustrated in detail in a certain embodiment, reference may be made to related descriptions in other embodiments.

The units or modules described as separate parts may or may not be physically separate, and parts displayed as units or modules may or may not be physical units, may be located in one position, or may be distributed on multiple functional units. Some or all of the units or modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, each functional unit or module in the embodiments of the present application may be integrated into one chip unit, or each unit or module may exist alone physically, or two or more units or modules are integrated into one unit.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The previous description is only an example of the present application, and is provided to enable any person skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An amplifier, characterized in that the amplifier comprises:

the field effect transistor comprises a drain electrode, a grid electrode and a source electrode, and is used for signal amplification;

the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio-frequency signal input end;

the drain matching circuit comprises a first low-coupling inductance pair, and the first low-coupling inductance pair is an inductance pair with opposite induction magnetic fields.

2. The amplifier of claim 1, wherein the first low-coupled inductor pair comprises:

3. The amplifier of claim 2, wherein the drain matching circuit further comprises:

and a first end of the second capacitor is connected with a first end of the second inductor, and a second end of the second capacitor is grounded.

4. The amplifier of claim 1, wherein the gate matching circuit comprises:

a fourth inductive unit, a first end of the fourth inductive unit being connected to a first end of the third inductive unit;

5. The amplifier of claim 4, wherein the third inductive unit and the fourth inductive unit are a second pair of low-coupled inductive units, and the second pair of low-coupled inductive units are pairs of inductors with opposite inductive fields.

6. The amplifier of claim 4 or 5, further comprising a gate bias circuit, wherein the gate bias circuit is connected to the third terminal of the gate matching circuit.

7. The amplifier of claim 6, wherein the gate bias circuit comprises:

8. The amplifier of claim 7, wherein the source feedback circuit comprises:

the fifth inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.

9. The amplifier of claim 7, wherein the source feedback circuit is ground.

10. The amplifier of claim 7, wherein the source feedback circuit comprises:

a fifth capacitor, a first end of which is connected to the second end of the sixth inductive unit, and a first end of which is further connected to a source bias power supply terminal, and a second end of which is grounded;

the sixth inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.

11. The amplifier of claim 7, wherein the gate bias circuit is ground.

12. The amplifier of claim 11, wherein the source feedback circuit comprises:

13. The amplifier of claim 2, wherein the first and second inductors are both spiral inductors and are arranged in the amplifier with opposite spiral directions.

14. The amplifier of claim 2, wherein the first and second inductors are arranged in the amplifier as mirror images of each other.

15. The amplifier of claim 2, wherein the first inductor is composed of a first microstrip line and the first microstrip line is wound in a first spiral pattern, the second inductor is composed of a second microstrip line and the second microstrip line is wound in a second spiral pattern, wherein a first end and a second end of the first microstrip line are respectively used as a first end and a second end of the first inductor, a first end and a second end of the second microstrip line are respectively used as a first end and a second end of the second inductor, and the second end of the first microstrip line and the second end of the second microstrip line are connected together such that the first microstrip line and the second microstrip line form a merged microstrip line.

16. The amplifier of claim 15, wherein the first and second spiral patterns do not overlap and are adjacent but at a distance in a direction parallel to a routing layer of the amplifier.

17. The amplifier of claim 15, wherein the merged microstrip is comprised of multiple layers of metallic material, wherein each layer of metallic material is located in a different wiring level of the amplifier.

18. The amplifier of claim 15, wherein the merged microstrip is comprised of a single layer of metallic material, wherein the single layer of metallic material is located in the same or different wiring layers of the amplifier.

19. A radio frequency chip comprising a substrate, and the amplifier of any one of claims 1 to 18 on the substrate.

20. An electronic device comprising the radio frequency chip of claim 19.