CN116938152A

CN116938152A - Amplifier, radio frequency chip and electronic device

Info

Publication number: CN116938152A
Application number: CN202210349327.4A
Authority: CN
Inventors: 刘石生; 黄伟
Original assignee: Shenzhen Jingzhun Communication Technology Co ltd
Current assignee: Shenzhen Jingzhun Communication Technology Co ltd
Priority date: 2022-04-01
Filing date: 2022-04-01
Publication date: 2023-10-24

Abstract

The embodiment of the application discloses an amplifier, a radio frequency chip and an electronic device. The amplifier includes: the three-port transistor is used for receiving the radio frequency signal to be amplified from the third electrode of the three-port transistor, outputting an inverted amplified signal from the first electrode of the three-port transistor after amplifying the radio frequency signal to be amplified, and outputting an in-phase amplified signal from the second electrode of the three-port transistor; the first pole matching circuit comprises N branches, and a j-th branch of the first pole matching circuit is used for transmitting an inverted amplified signal to a j-th radio frequency signal output end to become a j-th amplified signal; the second pole matching circuit comprises N branches, and the j-th branch of the second pole matching circuit is used for transmitting in-phase amplified signals to the (N+j) -th radio frequency signal output end to become (N+j) -th amplified signals; where j= … … N, j is an integer of 1 or more, and N is an integer of 1 or more. The application can realize the multipath amplification of the radio frequency signals by adopting a three-port transistor.

Description

Amplifier, radio frequency chip and electronic device

Technical Field

The present application relates to the field of electronic technology, and in particular, to an amplifier, a radio frequency chip, and an electronic device.

Background

With the development of high-frequency wireless communication technology, particularly the commercial use of 5G technology and Massive MIMO technology, the high-frequency wireless communication technology has become an important development direction of wireless communication.

The radio frequency communication transceiver system in the high frequency wireless communication system comprises a plurality of amplifiers, and the performance of the amplifiers can have important influence on the performance of the radio frequency communication transceiver system. Thus, high frequency wireless communication places higher demands on the amplifier, such as the ratio of gain to power consumption.

Disclosure of Invention

In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides an amplifier, a radio frequency chip and an electronic device.

In a first aspect, the present application provides an amplifier comprising:

the three-port transistor comprises a first pole, a second pole and a third pole, and is used for receiving a radio frequency signal to be amplified from the third pole of the three-port transistor, outputting an inverted amplified signal from the first pole of the three-port transistor after amplifying the radio frequency signal to be amplified, and outputting an in-phase amplified signal from the second pole of the three-port transistor;

a first pole matching circuit comprising N branches,

The first end of the j-th branch of the first polar matching circuit is connected with the first polar of the three-port transistor, the second end of the j-th branch of the first polar matching circuit is connected with the j-th radio frequency signal output end,

the j-th branch of the first polar matching circuit is used for matching the impedance of the first polar of the three-port transistor to a j-th target impedance, wherein the j-th target impedance is the output impedance of a j-th radio frequency signal output end, and the j-th branch of the first polar matching circuit is also used for transmitting the inverse amplification signal to the j-th radio frequency signal output end to become a j-th amplification signal;

a second pole matching circuit, the second pole matching circuit comprising N branches,

the first end of the j-th branch of the second pole matching circuit is connected with the second pole of the three-port transistor, the second end of the j-th branch of the second pole matching circuit is connected with the (n+j) -th radio frequency signal output end,

the j-th branch of the second pole matching circuit is used for matching the impedance of the second pole of the three-port transistor to the (n+j) -th target impedance, wherein the (n+j) -th target impedance is the output impedance of the (n+j) -th radio frequency signal output end, and the j-th branch of the second pole matching circuit is also used for transmitting the in-phase amplified signal to the (n+j) -th radio frequency signal output end to become an (n+j) -th amplified signal;

Where j= … … N, j is an integer of 1 or more, and N is an integer of 1 or more.

In the embodiment of the application, the jth amplified signal is synthesized with the (n+j) th amplified signal;

In the embodiment of the present application, the synthesis of the jth amplified signal and the n+j amplified signal includes:

the j-th radio frequency signal output end is connected with the n+j-th radio frequency signal output end;

In an embodiment of the present application, the amplifier further includes:

a number of N impedance transformation circuits,

the first end of the j-th impedance transformation circuit is connected with the j-th radio frequency signal output end, and the second end of the j-th impedance transformation circuit is connected with the 2N+j-th radio frequency signal output end;

In the embodiment of the application, the amplifier further comprises N synthesis circuits,

the j-th amplified signal is combined with the n+j-th amplified signal, including:

the jth radio frequency signal output end is connected with the first end of the jth synthesizing circuit, and the (n+j) th radio frequency signal output end is connected with the second end of the jth synthesizing circuit so as to synthesize the jth amplified signal and the (n+j) th amplified signal;

In an embodiment of the present application, the amplifier further includes:

a number of N impedance transformation circuits,

the first end of the j-th impedance transformation circuit is connected with the third end of the j-th synthesis circuit, and the second end of the j-th impedance transformation circuit is connected with the 2N+j radio frequency signal output end;

In an embodiment of the present application, the amplifier further includes:

the first end of the third pole matching circuit is connected with the radio frequency signal input end, and the second end of the third pole matching circuit is connected with the third pole of the three-port transistor;

the third pole bias circuit is connected with a third end of the third pole matching circuit;

the first ends of the jth first pole bias circuits are connected with the jth first pole bias power supply end;

the first end of the jth second bias circuit is connected with the third end of the jth branch of the second matching circuit;

In an embodiment of the present application, the first polar matching circuit is the first polar matching circuit

The j branch comprises:

a j-th branch first inductive unit, wherein a second end of the j-th branch first inductive unit is connected with a first pole of the three-port transistor;

the first end of the jth branch second inductive unit is connected with the jth first pole bias power supply end, and the second end of the jth branch second inductive unit is connected with the first end of the jth branch first inductive unit;

a first end of the jth branch third inductive unit is connected with the first end of the jth branch first inductive unit, and a second end of the jth branch third inductive unit is connected with the jth radio frequency signal output end;

In an embodiment of the present application, a jth branch of the second pole matching circuit includes:

a first end of the j-th branch fourth inductive unit is connected with a second pole of the three-port transistor;

a fifth inductive unit of a j-th branch, wherein a first end of the fifth inductive unit of the j-th branch is connected with a second end of the fourth inductive unit of the j-th branch;

A first end of the first capacitor of the jth branch is connected with a second end of the fourth inductive unit of the jth branch, and a second end of the first capacitor of the jth branch is connected with the (n+j) th radio frequency signal output end;

In an embodiment of the present application, the third pole matching circuit includes:

a sixth inductive unit, the first end of the sixth inductive unit is connected with the third electrode of the three-port transistor;

a seventh inductive unit, wherein a first end of the seventh inductive unit is connected with a second end of the sixth inductive unit, and a second end of the seventh inductive unit is connected with the third pole bias circuit;

and the first end of the second capacitor is connected with the radio frequency signal input end, and the second end of the second capacitor is connected with the second end of the sixth inductive unit.

In the embodiment of the application, the first inductive unit of the jth branch and the second inductive unit of the jth branch are inductance pairs with opposite induction magnetic fields; and/or

The fourth inductive unit of the jth branch and the fifth inductive unit of the jth branch are inductive pairs with opposite induction magnetic fields; and/or

The sixth inductive unit and the seventh inductive unit are inductance pairs with opposite induction magnetic fields;

In an embodiment of the present application, the third pole bias circuit includes:

and the first end of the third capacitor is grounded, the second end of the third capacitor is connected with the second end of the seventh inductive unit, and the second end of the third capacitor is also connected with a third pole bias power supply end.

In an embodiment of the present application, the jth second bias circuit includes:

a first end of the jth fourth capacitor is connected with the second end of the jth branch fifth inductive unit, the first end of the jth fourth capacitor is also connected with a jth second pole bias power supply end, and the second end of the jth fourth capacitor is grounded;

In the embodiment of the application, the jth second bias circuit is ground;

In the embodiment of the present application, the third pole bias circuit is ground.

A jth sixth capacitor, wherein a first end of the jth sixth capacitor is connected to the second end of the jth branch fifth inductive unit, and a second end of the jth sixth capacitor is grounded;

a jth first resistor, wherein a first end of the jth first resistor is connected with a second end of the jth branch fifth inductive unit, and a second end of the jth first resistor is grounded;

In an embodiment of the present application, the jth first pole bias circuit includes:

a first end of the jth seventh capacitor is grounded, and a second end of the jth seventh capacitor is connected with a jth first pole bias power supply end;

In a second aspect, the application provides a radio frequency chip comprising a substrate, and an amplifier as described above on the substrate.

In a third aspect, an electronic device is provided, comprising a radio frequency chip as described above.

An embodiment of the present application provides an amplifier including: the three-port transistor comprises a first pole, a second pole and a third pole, and is used for receiving a radio frequency signal to be amplified from the third pole of the three-port transistor, outputting an inverted amplified signal from the first pole of the three-port transistor after amplifying the radio frequency signal to be amplified, and outputting an in-phase amplified signal from the second pole of the three-port transistor; the first pole matching circuit comprises N branches, the first end of a j-th branch of the first pole matching circuit is connected with the first pole of the three-port transistor, the second end of the j-th branch of the first pole matching circuit is connected with a j-th radio frequency signal output end, the j-th branch of the first pole matching circuit is used for matching the impedance of the first pole of the three-port transistor to a j-th target impedance, the j-th target impedance is the output impedance of the j-th radio frequency signal output end, and the j-th branch of the first pole matching circuit is also used for transmitting the inverse amplification signal to the j-th radio frequency signal output end to become a j-th amplification signal; the second pole matching circuit comprises N branches, the first end of the j-th branch of the second pole matching circuit is connected with the second pole of the three-port transistor, the second end of the j-th branch of the second pole matching circuit is connected with the (N+j) -th radio frequency signal output end, the j-th branch of the second pole matching circuit is used for matching the second pole output impedance of the three-port transistor to the (N+j) -th target impedance, the (N+j) -th target impedance is the output impedance of the (N+j) -th radio frequency signal output end, and the j-th branch of the second pole matching circuit is also used for transmitting the in-phase amplified signal to the (N+j) -th radio frequency signal output end to be the (N+j) -th amplified signal; where j= … … N, j is an integer of 1 or more, and N is an integer of 1 or more. The embodiment of the application can realize the multipath amplification of the radio frequency signals by adopting a three-port transistor, thereby improving the functional density of the amplifier and the ratio of gain to power consumption.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 to 26 and fig. 30 to 36 are schematic structural views of an amplifier in the embodiment of the present application;

fig. 27 to 29 are signal diagrams of an amplifier according to an embodiment of the present application;

FIG. 37 is a schematic diagram of a radio frequency chip in an embodiment of the application;

FIG. 38 is a schematic diagram of the placement of low coupling inductance pairs in an amplifier in an embodiment of the application;

fig. 39 is a schematic diagram of an electronic device according to an embodiment of the application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The amplifier provided by the embodiment of the application can be applied as an independent component or can be applied to radio frequency chips or system integration.

As shown in fig. 1, the amplifier includes:

a three-port transistor 111, including a first pole, a second pole and a third pole, where the three-port transistor 111 is configured to receive a radio frequency signal SIN to be amplified from the third pole of the three-port transistor 111, amplify the radio frequency signal SIN to be amplified, output an inverted amplified signal SO1 from the first pole of the three-port transistor 111, and output an in-phase amplified signal SO2 from the second pole of the three-port transistor 111;

a first pole matching circuit 112, said first pole matching circuit 112 comprising N branches,

a first terminal of a j-th branch 112 j of the first pole matching circuit 112 is connected to a first pole of the three-port transistor 111, a second terminal of the j-th branch 112 j of the first pole matching circuit 112 is connected to a j-th radio frequency signal output terminal RFOUT j,

the j-th branch 112_j of the first pole matching circuit 112 is configured to match the impedance of the first pole of the three-port transistor 111 to a j-th target impedance zo_j, where the j-th target impedance zo_j is an output impedance of the j-th radio frequency signal output terminal rfout_j, and the j-th branch 112_j of the first pole matching circuit 112 is further configured to transmit the inverse amplified signal SO1 to the j-th radio frequency signal output terminal rfout_j to become a j-th amplified signal s_j;

A second pole matching circuit 113, said second pole matching circuit 113 comprising N branches,

a first terminal of a j-th branch 113_j of the second pole matching circuit 113 is connected to a second pole of the three-port transistor 111, a second terminal of the j-th branch 113_j of the second pole matching circuit 113 is connected to an n+j-th radio frequency signal output terminal rfout_n+j,

the jth branch 113_j of the second matching circuit 113 is configured to match the second output impedance of the three-port transistor 111 to an n+j target impedance zo_n+j, where the n+j target impedance zo_n+j is the output impedance of the n+j rf signal output terminal rfout_n+j, and the j branch 113_j of the second matching circuit 113 is further configured to transmit the in-phase amplified signal SO2 to the n+j rf signal output terminal rfout_n+j to become a j amplified signal s_n+j;

In an embodiment of the present application, the three-port transistor 111 may be a field effect transistor 1111 or a triode 1112.

In the embodiment of the present application, the jth amplified signal s_j is synthesized with the jth amplified signal s_n+j;

In the embodiment of the present application, the j-th amplified signal s_j and the j-th amplified signal s_n+j are synthesized, which may be directly synthesized, as shown in fig. 2; or may be synthesized by a synthesis circuit, as shown in fig. 3.

As shown in fig. 2, the j-th amplified signal s_j is combined with the j-th amplified signal s_n+j, and includes:

the j-th radio frequency signal output end RFOUT_j is connected with the n+j-th radio frequency signal output end RFOUT_N+j;

As shown in fig. 2, the amplifier further includes:

n number of the impedance transforming circuits 150,

the first end of the j-th impedance transformation circuit 150_j is connected with the j-th radio frequency signal output end rfout_j, and the second end of the j-th impedance transformation circuit 150_j is connected with the 2n+j-th radio frequency signal output end rfout_2n+j;

As shown in fig. 3, the amplifier further includes N combining circuits 170,

the j-th amplified signal s_j is combined with the j-th amplified signal s_n+j, and includes:

the j-th rf signal output terminal rfout_j is connected to the first terminal of the j-th combining circuit 170_j, and the n+j-th rf signal output terminal rfout_n+j is connected to the second terminal of the j-th combining circuit 170_j, so that the j-th amplified signal s_j and the j-th amplified signal s_n+j are combined;

As shown in fig. 3, the amplifier further includes:

n number of the impedance transforming circuits 150,

a first end of the j-th impedance transformation circuit 150_j is connected to a third end of the j-th synthesis circuit 170_j, and a second end of the j-th impedance transformation circuit 150_j is connected to the 2n+j-th radio frequency signal output end rfout_2n+j;

As shown in fig. 1, the amplifier further includes:

a third pole matching circuit 130, wherein a first end of the third pole matching circuit 130 is connected to the radio frequency signal input terminal RFIN, and a second end of the third pole matching circuit 130 is connected to a third pole of the three-port transistor 111;

a third pole bias circuit 160, wherein the third pole bias circuit 160 is connected to the third terminal of the third pole matching circuit 130;

the first ends of the N first pole bias circuits 120, the j-th first pole bias circuit 120_j are connected with the j-th first pole bias power supply end v1_j;

the first end of the jth second bias circuit 140_j is connected to the third end of the jth branch 113_j of the second matching circuit 113;

In the embodiment of the present application, the jth first pole bias circuit 120_j is configured to provide a bias power v1_j to the first pole of the three-port transistor 111, and simultaneously provide a radio frequency signal ground to the third terminal of the jth branch 112_j of the first pole matching circuit 112.

The third pole matching circuit 130 is configured to match an input impedance of a third pole of the three-port transistor 111 to a third target impedance, where the third target impedance is an impedance of the radio frequency signal input terminal RFIN, so as to implement input impedance matching for the amplifier.

The jth second bias circuit 140_j is configured to provide a bias power v2_j (not shown) to the second pole of the three-port transistor 111, and simultaneously provide a radio frequency signal ground to the third terminal of the jth branch 113_j of the second pole matching circuit 113.

In the embodiment of the application, the plurality of first pole bias power supply terminals can be physically independent and electrically equivalent. Therefore, for convenience of description, in the embodiment of the present application and the drawings, the first pole bias power supply terminal v1_j may be directly referred to as the first pole bias power supply terminal V1.

In the embodiment of the present application, although there are a plurality of first pole bias power supply terminals V1, only any one of the first pole bias power supply terminals V1 needs to be connected to the first pole bias power supply. Similarly, the second polarity bias power supply V2 may be set as above.

The third pole bias circuit 160 is configured to provide a bias power V3 (not shown) to a third pole of the three-port transistor 111, and to provide a radio frequency signal ground to a third terminal of the third pole matching circuit 130.

In the embodiment of the application, the three-port transistor 111 and the j-th branch 112_j of the first pole matching circuit 112 form a first radio frequency signal amplifying link, and the three-port transistor 111 and the j-th branch 113_j of the second pole matching circuit 113 form a second radio frequency signal amplifying link, so that the amplifier of the embodiment of the application can amplify the input radio frequency signal in 2N ways, and the functional density of the amplifier is improved.

In the above description, j= … … N, j is an integer of 1 or more, and N is an integer of 1 or more.

In the embodiment of the application, the input signal, the output signal and the amplified signal are all radio frequency signals.

In the following, n=1 is taken as an example, and the three-port transistor 111 is taken as a field effect transistor 1111 as an example.

In the embodiment of the present application, when the three-port transistor 111 is the field effect transistor 1111, as shown in fig. 4, the first electrode is a Drain (Drain, D electrode), the second electrode is a Source (S electrode), and the third electrode is a Gate (G electrode). At this time, the 1 st branch 112_1 of the first pole matching circuit 112 is the 1 st branch 112_1 of the drain matching circuit 112, the 1 st branch 113_1 of the second pole matching circuit 112 is the 1 st branch 113_1 of the source matching circuit 113, the third pole matching circuit 130 is the gate matching circuit 130, the 1 st first pole bias circuit 120_1 is the 1 st drain bias circuit 120_1, the 1 st second pole bias circuit 140_1 is the 1 st source bias circuit 140_1, and the third pole bias circuit 160 is the gate bias circuit 160.

In the prior art, according to the operation principle of the fet 1111, the drain current of the fet 1111 and the source current of the fet 1111 are inverted, and in an ideal state, the drain current and the source current are equal.

In the embodiment of the present application, the amplifier shown in fig. 4 may be decomposed into two rf signal amplifiers based on the principle of amplifying rf signals by the fet 1111. When the three-port transistor 111 is the field-effect transistor 1111, it is a common source amplifier shown in fig. 5 and a source follower amplifier shown in fig. 6, respectively. The radio frequency signal is input by the grid matching circuit 130, so that the radio frequency signal SIN to be amplified becomes a 1 st amplified signal S_1 after being amplified by an equivalent common source amplifier, and is output through a 1 st radio frequency signal output end RFOUT_1; the radio frequency signal is input by the gate matching circuit 130 at the same time, so that the radio frequency signal SIN to be amplified becomes the 2 nd amplified signal s_2 after passing through the equivalent source follower amplifier, and is output through the 2 nd radio frequency signal output terminal rfout_2.

As shown in fig. 5, the fet 1111, the gate matching circuit 130, the gate bias circuit 160, the 1 st branch 112_1 of the drain matching circuit 112, the 1 st drain bias circuit 120_1 and the source equivalent impedance ZS form an equivalent common source amplifier, wherein the source equivalent impedance ZS is the equivalent impedance of the first end of the 1 st branch 113_1 of the source matching circuit 113. The rf signal is input from the gate matching circuit 130, SO that the rf signal SIN to be amplified drives the gate of the fet 1111, and the rf signal SIN is amplified by the fet 1111 to output the amplified signal SO1, and the amplified signal SO1 passes through the 1 st branch 112_1 of the drain matching circuit 112 to output the 1 st amplified signal s_1.

As shown in fig. 6, the field effect transistor 1111, the gate matching circuit 130, the gate bias circuit 160, the 1 st branch 113_1 of the source matching circuit 113, the 1 st source bias circuit 140_1 and the drain equivalent impedance ZD form an equivalent source follower amplifier, wherein the drain equivalent impedance ZD is an equivalent impedance of the first end of the 1 st branch 112_1 of the drain matching circuit 112. The rf signal is input from the gate matching circuit 130, SO that the rf signal SIN to be amplified drives the gate of the fet 1111, and the fet 1111 outputs the in-phase amplified signal SO2 after the rf signal is amplified, and the in-phase amplified signal SO2 outputs the 2 nd amplified signal s_2 through the 1 st branch 113_1 of the source matching circuit 113.

The amplifier of the embodiment of the application only adopts one field effect transistor 1111 to amplify the radio frequency input signal in two ways, namely, the two ways of amplification of the radio frequency input signal through the common source amplifier and the source follower amplifier are realized.

As shown in fig. 7, the 1 st branch 112_1 of the drain matching circuit 112 includes:

a first inductive unit l1_1 of the 1 st branch, wherein a second end of the first inductive unit l1_1 of the 1 st branch is connected with a drain electrode of the field effect transistor 1111;

the first end of the 1 st branch second inductive unit L2_1 is connected with the 1 st drain bias power supply end VD, and the second end of the 1 st branch second inductive unit L2_1 is connected with the first end of the 1 st branch first inductive unit L1_1;

The first end of the 1 st branch third inductive unit l3_1 is connected with the first end of the 1 st branch first inductive unit l1_1, and the second end of the 1 st branch third inductive unit l3_1 is connected with the 1 st radio frequency signal output end rfout_1.

In embodiments of the present application, the plurality of first pole/drain bias power terminals may be physically independent, but electrically equivalent. Therefore, for convenience of description, the first pole/drain bias power terminal vd_1 may be directly referred to as the first pole/drain bias power terminal VD in the embodiments and the drawings. Similarly, the second pole/source bias power terminal vs_1 may be set as above.

As shown in fig. 7, the 1 st branch 113_1 of the source matching circuit 113 includes:

a first end of the 1 st branch fourth inductive unit l4_1 is connected with the source electrode of the field effect tube 1111;

a first end of the fifth inductive unit L5_1 of the 1 st branch is connected with a second end of the fourth inductive unit L4_1 of the 1 st branch;

the first end of the first branch circuit 1 capacitor C1_1 is connected with the second end of the fourth inductive unit L4_1 of the 1 st branch circuit, and the second end of the first branch circuit 1 capacitor C1_1 is connected with the 2 nd radio frequency signal output end RFOUT_2.

As shown in fig. 7, the third pole matching circuit 130 includes:

a sixth inductive unit L6, wherein a first end of the sixth inductive unit L6 is connected to the gate of the fet 1111;

a seventh inductive unit L7, wherein a first end of the seventh inductive unit L7 is connected to a second end of the sixth inductive unit L6, and a second end of the seventh inductive unit L7 is connected to the third pole bias circuit 160;

and a second capacitor C2, wherein a first end of the second capacitor C2 is connected to the radio frequency signal input terminal RFIN, and a second end of the second capacitor C2 is connected to a second end of the sixth inductive unit L6.

In the embodiment of the present application, the first inductive unit l1_1 of the 1 st branch and the second inductive unit l2_1 of the 1 st branch are inductance pairs with opposite induction magnetic fields; and/or

The fourth inductive unit L4_1 of the 1 st branch and the fifth inductive unit L5_1 of the 1 st branch are inductance pairs with opposite induction magnetic fields; and/or

The sixth inductive element L6 and the seventh inductive element L7 are inductance pairs with opposite induced magnetic fields.

In the embodiment of the application, the pair of inductances with opposite induction fields is formed by a pair of inductances with opposite induction fields. That is, the first inductive unit l1_1 of the 1 st branch and the second inductive unit l2_1 of the 1 st branch are pairs of inductances opposite to each other, and can only be the first inductance l1_1 of the 1 st branch and the second inductance l2_1 of the 1 st branch. The other inductance pairs are the same as the above inductance pairs, and will not be described here again.

When the inductor is excited by a signal, an induced magnetic field is generated, an induced electric field is generated by the induced magnetic field, and radiation is generated by the induced electric field, so that energy loss is generated.

In the embodiment of the application, the first inductance L1_1 of the 1 st branch and the second inductance L2_1 of the 1 st branch are low-coupling inductance pairs, and the directions of the induction magnetic fields of the first inductance L1_1 of the 1 st branch and the second inductance L2_1 of the 1 st branch are opposite, so that the directions of the induction electric field generated by the induction magnetic field of the first inductance L1_1 of the 1 st branch and the induction electric field generated by the induction magnetic field of the second inductance L2_1 of the 1 st branch are opposite, and the two opposite induction electric fields can be partially offset, so that the radiation generated by the induction electric field is reduced, and the energy loss is reduced. Because the induced electric field between the 1 st branch first inductor l1_1 and the 1 st branch second inductor l2_1 is partially offset, the induced electric field of the 1 st branch second inductor l2_1 weakens the influence range of the induced electric field of the 1 st branch first inductor l1_1, and similarly, the induced electric field of the 1 st branch first inductor l1_1 weakens the influence range of the induced electric field of the 1 st branch second inductor l2_1, the physical distance between the 1 st branch first inductor l1_1 and the 1 st branch second inductor l2_1 can be more similar. Similarly, the physical distance between the low-coupling inductance pair and other devices can be closer, so that the size of the circuit can be reduced, and the cost can be reduced. Similarly, the directions of the induction magnetic fields of the fourth inductor L4_1 of the 1 st branch and the fifth inductor L5_1 of the 1 st branch are opposite, so that the energy loss can be reduced, the size of a circuit is reduced, and the cost is reduced, and the description is omitted.

In the embodiment of the application, any inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line. In the embodiment of the application, any one of the plurality of inductive units can be one of an inductor, a microstrip line or a combination of the inductor and the microstrip line, or part of inductive units are the inductor, part of inductive units are the microstrip line, and part of inductive units are the combination of the inductor and the microstrip line; or all the inductors, or all the microstrip lines, or all the combinations of the inductors and the microstrip lines, which are not described herein.

In the embodiment of the present application, the inductive units forming the low-coupling inductance pair can only be two inductances, which are not described herein. Therefore, in the embodiment of the present application, the 1 st branch first inductor l1_1 and the 1 st branch second inductor l2_1 with opposite induced magnetic fields may be referred to as a low-coupling inductor pair, the 1 st branch fourth inductor l4_1 and the 1 st branch fifth inductor l5_1 with opposite induced magnetic fields may be referred to as a low-coupling inductor pair, and the sixth inductor L6 and the seventh inductor L7 with opposite induced magnetic fields may be referred to as a low-coupling inductor pair.

The amplifier core unit in the embodiment of the application may not have any low coupling inductance pair, as shown in fig. 7; or may include a low coupling inductance pair formed by a 1 st branch first inductance l1_1 and a 1 st branch second inductance l2_1 with opposite induction magnetic field directions, as shown in fig. 8; or may include a low coupling inductance pair composed of a 1 st branch fourth inductance l4_1 and a 1 st branch fifth inductance l5_1 with opposite induced magnetic field directions, as shown in fig. 9; or may include a low coupling inductance pair composed of a sixth inductance L6 and the seventh inductance L7 with opposite induced magnetic fields, as shown in fig. 10; or may include any two or three of the above three pairs of low coupling inductances, as shown in fig. 11-13. In the drawings of the embodiments of the present application, not all combinations of low-coupling inductance pairs are shown, and will not be described herein.

As shown in fig. 7, the gate bias circuit 160 includes:

and the first end of the third capacitor C3 is grounded, the second end of the third capacitor C3 is connected with the second end of the seventh inductive unit L7, and the second end of the third capacitor C3 is also connected with a third pole bias power supply end VG.

In the embodiment of the present application, the frequency of the resonance point of the third capacitor C3 is close to or the same as the center frequency of the working frequency band of the amplifier, so as to isolate the rf ac signal between the amplifier and the gate bias power supply terminal VG, and simultaneously provide the rf signal ground for the second terminal of the seventh inductive unit L7.

As shown in fig. 7, the 1 st second bias circuit 140_1 includes:

and the first end of the 1 st fourth capacitor C4_1 is connected with the second end of the 1 st branch fifth inductive unit L5_1, the first end of the 1 st fourth capacitor C4_1 is also connected with the source bias power supply end VS, and the second end of the 1 st fourth capacitor C4_1 is grounded.

In the embodiment of the application, the frequency of the resonance point of the 1 st fourth capacitor C4_1 is close to or the same as the center frequency of the working frequency band of the amplifier, so as to realize the isolation of the radio frequency alternating current signal of the amplifier and the source bias power supply end VS, and simultaneously provide the radio frequency signal ground for the second end of the 1 st branch fifth inductive unit L5_1.

As shown in fig. 7, the 1 st drain bias circuit 120_1 includes:

and a first end of the 1 st seventh capacitor C7_1 is grounded, and a second end of the 1 st seventh capacitor C7_1 is connected with the 1 st drain bias power supply end VD.

In the embodiment of the application, the resonance point frequency of the seventh capacitor C7_1 of the 1 st branch is close to or the same as the center frequency of the working frequency band of the amplifier, so as to isolate the radio frequency alternating current signal of the amplifier and the bias power supply end VD of the 1 st drain, and simultaneously provide the radio frequency signal ground for the first end of the second inductive unit L2_1 of the 1 st branch.

In the embodiment shown in fig. 8 to 13, a gate bias voltage VG is provided to a field effect transistor 1111 of the amplifier through a gate bias power supply terminal VG, a drain bias voltage VD is provided to the field effect transistor 1111 of the amplifier through a drain bias power supply terminal VD, a source bias voltage VS is provided to the field effect transistor 1111 of the amplifier through a source bias power supply terminal VS, a voltage difference between VG and VS is adjusted to be a gate-source bias voltage difference in a normal operation state of the field effect transistor 1111, and a voltage difference between VD and VS is adjusted to be a drain-source bias voltage difference in a normal operation state of the field effect transistor 1111, so that the field effect transistor 1111 is in a normal operation state. The input signal is input through the rf signal input terminal RFIN, passes through the gate matching circuit 130, drives the gate of the fet 1111 in the amplifier core unit, and passes through the 1 st branch 112_1 of the drain matching circuit 112 and the 1 st branch 113_1 of the source matching circuit 113 after being amplified by the fet 1111, so as to form the 1 st amplified signal s_1 and the 2 nd amplified signal s_2.

As shown in fig. 14, in the embodiment of the application, the 1 st source bias circuit 140_1 is ground. That is, the second terminal of the fifth inductive unit l5_1 of the 1 st branch is directly grounded.

In the embodiment shown in fig. 14, when the 1 st source bias circuit 140_1 is ground, the amplifier does not include a low coupling inductance pair, and in other embodiments of the application, the 1 st source bias circuit 140_1 is ground and may further include at least one low coupling inductance pair, as shown in fig. 15 to 18, and the detailed description will be omitted herein with reference to the above embodiments and the drawings.

In the embodiment of the present application shown in fig. 14 to 18, the gate bias voltage VG is supplied to the field effect transistor 1111 of the amplifier through the gate bias power terminal VG, and the drain bias voltage VD is supplied to the field effect transistor 1111 of the amplifier through the drain bias power terminal VD. The rf signal is input through the rf signal input terminal RFIN, passes through the gate matching circuit 130, drives the gate of the fet 1111 in the amplifier core unit, and passes through the 1 st branch 112_1 of the drain matching circuit 112 and the 1 st branch 113_1 of the source matching circuit 113 after being amplified by the fet 1111, thereby forming the 1 st amplified signal s_1 and the 2 nd amplified signal s_2.

In the embodiments of the present application shown in fig. 14 to 18, the low coupling inductance pair may not be included as shown in fig. 14, or at least one low coupling inductance pair may be included as shown in fig. 15 to 18; the drawings of the present application do not show the combination of all low-coupling inductance pairs, and are not described herein.

In another embodiment of the present application, as shown in fig. 19, the gate bias circuit 160 and the 1 st source bias circuit 140_1 are further provided, and the gate bias circuit 160 is grounded, i.e. the second end of the seventh sensing unit L7 is directly grounded.

As shown in fig. 19, the 1 st source bias circuit 140_1 includes:

a 1 st sixth capacitor c6_1, wherein a first end of the 1 st sixth capacitor c6_1 is connected to a second end of the 1 st branch fifth inductive unit l5_1, and a second end of the 1 st sixth capacitor c6_1 is grounded;

the first end of the 1 st first resistor R1_1 is connected with the second end of the 1 st branch fifth inductive unit L5_1, and the second end of the 1 st first resistor R1_1 is grounded.

In the embodiment of the present application, the 1 st sixth capacitor c6_1 is configured to couple the signal output by the source electrode of the field effect transistor 1111 and passing through the inductor to ground, so as to form a radio frequency signal ground, thereby reducing the energy loss of the source electrode circuit.

In the embodiment of the present application, the 1 st resistor r1_1 is used to raise the source potential of the fet 1111, so that the gate-to-source voltage of the fet 1111 (depletion type fet) is negative, and the normal operation of the amplifier is maintained.

In the embodiment of the present application shown in fig. 19 to 23, the drain bias voltage VD is provided to the fet 1111 through the 1 st drain bias power terminal VD, and at this time, the drain-source current of the fet 1111 flows through the 1 st first resistor r1_1 in the 1 st source bias circuit 140_1, so as to increase the source potential of the fet 1111, and make the gate-source voltage of the fet 1111 negative, so as to maintain the normal operation of the amplifier. The rf signal is input through the rf signal input terminal RFIN, passes through the gate matching circuit 130, drives the gate of the fet 1111 in the amplifier core unit, and passes through the 1 st branch 112_1 of the drain matching circuit 112 and the 1 st branch 113_1 of the source matching circuit 113 after being amplified by the fet 1111, thereby forming the 1 st amplified signal s_1 and the 2 nd amplified signal s_2.

In the embodiments of the present application shown in fig. 19-23, the low coupling inductance pair may not be included, as shown in fig. 19, or at least one low coupling inductance pair may be included, as shown in fig. 20-23; the drawings of the present application do not show the combination of all low-coupling inductance pairs, and are not described herein.

In the embodiment of n=1 shown in fig. 19 to 23, the 1 st source bias circuit 140_1 includes a resistor and a capacitor, and in other embodiments of N >1 of the present application, a plurality of source bias circuits each having to include a capacitor, but at least one of the plurality of source bias circuits may include a resistor.

In one embodiment of the present application, the 1 st branch 112_1 of the source matching circuit 112 may not include the 1 st branch first capacitor c1_1, and the 1 st branch 113_1 of the drain matching circuit 113 may be provided with a capacitor, i.e. the 1 st branch third inductive capacitor l3_1 and the 1 st branch first capacitor c1_1 in fig. 7 are interchanged. The connection manner of other parts of the interchanged circuit can be referred to the above embodiment and the drawings, and the working principle and the working flow are similar or the same as those of the above embodiment, and are not repeated here.

In the embodiment of the application, the power supply bias mode of the amplifier comprises single power supply self-bias, double power supply bias and three power supply bias, wherein the single power supply self-bias refers to that only the drain bias voltage VD is provided by the outside, as shown in fig. 19 to 23; the dual power bias refers to the supply of the drain bias voltage VD and the gate bias voltage VG from the outside as shown in fig. 14 to 18; the three-power bias refers to the supply of the pole bias voltage VD, the gate bias voltage VG, and the source bias voltage VS from the outside, as shown in fig. 7 to 13. The single power supply self-bias power supply is simple, the double power supply bias can exert better power performance, the three power supply bias is beneficial to energy conservation, and the power supply bias mode can be configured according to practical application. The power supply bias mode of the embodiment of the application can also be used in other circuits, and is not repeated here.

In the embodiment of the present application, the 1 st amplified signal s_1 and the 2 nd amplified signal s_2 are synthesized. The synthesis may be direct synthesis as shown in fig. 24, or may be synthesized by a synthesis circuit as shown in fig. 25.

As shown in fig. 24, the 1 st amplified signal s_1 and the 2 nd amplified signal s_2 are synthesized, including:

the 1 st radio frequency signal output end RFOUT_1 is connected with the 2 nd radio frequency signal output end RFOUT_2.

As shown in fig. 24, the amplifier further includes a 1 st impedance transformation circuit 150_1, wherein a first end of the 1 st impedance transformation circuit 150_1 is connected to the 1 st radio frequency signal output terminal rfout_1, and at this time, a first end of the 1 st impedance transformation circuit 150_1 is also connected to the 2 nd radio frequency signal output terminal rfout_2, and a second end of the 1 st impedance transformation circuit 150_1 is connected to the 3 rd radio frequency signal output terminal rfout_3.

The 1 st impedance transformation circuit 150_1 in the embodiment of the present application has a function of blocking the first end of the 1 st impedance transformation circuit 150_1 from the ground, and a function of blocking the first end of the 1 st impedance transformation circuit 150_1 from the second end of the 1 st impedance transformation circuit 150_1.

The 1 st impedance transformation circuit 150_1 in the embodiment of the present application may be a λ/4 impedance transformation circuit in the prior art, or may be any impedance matching circuit in the prior art that can realize the requirements of the amplifier in the embodiment of the present application.

The 1 st impedance transformation circuit 150_1 is configured to transform the synthesized impedance of the 1 st target impedance zo_1 and the 2 nd target impedance zo_2 to the output impedance of the amplifier.

In the embodiment of the present application, the rf signal input terminals of the amplifiers of fig. 5 and 6 are connected and can be equivalently the circuit shown in fig. 26, and the 1 st amplified signal s_1 and the 2 nd amplified signal s_2 outputted at this time are superimposed on each other.

The phase of the inverted amplified signal SO1 output from the common source amplifier shown in fig. 5 and the phase of the in-phase amplified signal SO2 output from the source follower amplifier shown in fig. 6 are inverted, and if SO1 and SO2 are directly synthesized, the amplitudes cancel each other, SO1 and SO2 are completely cancelled after being synthesized under ideal conditions, and the synthesized state after complete cancellation is shown with reference to fig. 27 (c), at this time, the amplifier after synthesizing the two amplified signals cannot effectively amplify the radio frequency signal.

In the embodiment of the present application, the amplifier of fig. 5 and the amplifier of fig. 6 adopt corresponding matching circuits, so that the phase difference between the 1 st amplified signal s_1 and the 2 nd amplified signal s_2 is 2npi in an ideal state, where n is an integer, as shown in fig. 28 (a) and 28 (b). After two continuous, periodic signals with phase difference of 2npi are overlapped, corresponding wave peaks and wave peaks are overlapped, wave troughs and wave troughs are overlapped, and the signal amplitude is enhanced. One possible case is that the phase difference between the peaks of the two signals is 0, and the two signals are superimposed as shown in fig. 28 (c).

The effect of the matching circuit on the phase of the amplified signal is described below.

In the embodiment of the present application, the 1 st branch 112_1 of the drain matching circuit 112 and the 1 st branch 113_1 of the source matching circuit 113 include an inductive unit and a capacitor, so that the phase of the rf signal of the drain of the three-port transistor and the phase of the rf signal of the source of the three-port transistor are shifted correspondingly, for example, the inductive unit is connected in series to cause phase lag, and the capacitor is connected in series to cause phase lead. The 1 st branch 112_1 of the drain matching circuit 112 and the like shift the phase of the signal of s_1 with respect to the signal of SO1 by ΔΦ1, and the 1 st branch 113_1 of the source matching circuit 113 and the like shift the phase of the signal of s_2 with respect to the signal of SO2 by ΔΦ2, as shown in fig. 29. Wherein the absolute value of the difference between Δφ1 and Δφ2 is (2 n-1) pi, and n is an integer. Since SO1 and SO2 are inverted and have a phase difference of pi, the phase difference of S_1 and S_2 is 2npi, and n is an integer. In the schematic diagram shown in fig. 29, only one period of signals of SO1, SO2, s_1, and s_2 is shown, and in fact, SO1, SO2, s_1, and s_2 are all periodic continuous signals. Fig. 29 shows only a case where the phase difference is a specific difference, and in practice, the phase difference between s_1 and s_2 is 2npi, and n is an integer.

In the embodiment of the present application, s_1 and s_2 are combined and added at the first end of the 1 st impedance transformation circuit 150_1, and the signal amplitude is enhanced, so that the gain of the amplifier in the embodiment of the present application is greater than that of the single common source amplifier or source follower amplifier. Ideally, the gain of the amplifier of the embodiments of the present application is 2 times that of the common source amplifier or the source follower amplifier alone when n=1.

In addition, in the embodiment of the present application, optimization for gain, power and noise can be also achieved by adjusting the 1 st branch 112_1 of the drain matching circuit 112 and the 1 st branch 113_1 of the source matching circuit 113.

In the embodiment of the present application, the 1 st amplified signal s_1 and the second amplified circuit s_2 may be synthesized by a synthesizing circuit. As shown in fig. 25, the 1 st amplified signal s_1 and the 2 nd amplified signal s_2 are synthesized, including:

the 1 st rf signal output terminal rfout_1 is connected to a first terminal of the 1 st synthesizing circuit 170_1, and the 2 nd rf signal output terminal rfout_2 is connected to a second terminal of the 1 st synthesizing circuit 170_1, where the 1 st synthesizing circuit 170_1 is configured to synthesize the 1 st amplified signal s_1 and the 2 nd amplified signal s_2.

The amplifier further includes a 1 st impedance transforming circuit 150_1, a first end of the 1 st impedance transforming circuit 150_1 is connected to a third end of the 1 st synthesizing circuit 170_1, a second end of the 1 st impedance transforming circuit 150_1 is connected to the 3 rd radio frequency signal output terminal rfout_3, and the 1 st impedance transforming circuit 150_1 is configured to transform the synthesized impedance of the third end of the 1 st synthesizing circuit 170_1 to the output impedance of the amplifier.

In the embodiment of the present application, the 1 st synthesizing circuit 170_1 may be a coupler, or may be a synthesizer with a phase shifting function, or may be another circuit capable of synthesizing a radio frequency signal.

The 1 st synthesizing circuit 170_1 may perform certain phase shifting on the 1 st amplified signal s_1 and the 2 nd amplified signal s_2, and then synthesize the 1 st amplified signal s_1 and the 2 nd amplified signal s_2, respectively, and make the output signal enter the 1 st impedance transforming circuit 150_1.

The 1 st synthesizing circuit 170_1 may shift only one of the 1 st amplified signal s_1 and the 2 nd amplified signal s_2 and synthesize the same, and make the output signal enter the 1 st impedance transforming circuit 150_1.

As described in the above embodiment, the 1 st combining circuit 170_1 shifts the 1 st amplified signal s_1 and/or the 2 nd amplified signal s_2 so that the phase difference between the two signals is 2npi, where n is an integer, and the combined amplitudes of the two amplified signals of the amplifier may be superimposed, so that the amplifier has a higher gain.

In the embodiment of the present application, the 1 st synthesizing circuit 170_1 may be split into two sub-circuits, where the two sub-circuits can both implement phase shifting of the radio frequency signal, and the two sub-circuits are respectively integrated with the 1 st branch 112_1 of the drain matching circuit 112 and the 1 st branch 113_1 of the source matching circuit 113, so as to implement phase shifting of the 1 st amplified signal s_1 and/or the 2 nd amplified signal s_2, and the 1 st amplified signal s_1 and the 2 nd amplified signal s_2 after phase shifting are directly synthesized; alternatively, the 1 st synthesizing circuit 170_1 may be integrated with the 1 st impedance transforming circuit 150_1, and the 1 st amplifying signal s_1 and/or the 2 nd amplifying signal s_2 may be phase-shifted and synthesized in the 1 st impedance transforming circuit 150_1. Both embodiments described above may be practically equivalent to the circuit of fig. 24.

In the embodiment of the present application, as shown in fig. 30 to 35, a circuit of an amplifier combining the 1 st amplified signal s_1 and the 2 nd amplified signal s_2 is schematically shown. Fig. 30 and 31 show a three-bias amplifier, in which two amplified signals are synthesized, and the synthesized amplified signal is output through the 1 st impedance transformation circuit 150_1 and the 3 rd radio frequency signal output terminal rfout_3; fig. 32 and 33 are double-bias amplifiers, in which two amplified signals are combined, and the combined amplified signal is output through the 1 st impedance transformation circuit 150_1 and the 3 rd radio frequency signal output terminal rfout_3; fig. 34 and 35 are single-bias amplifiers, in which two amplified signals are combined, and the combined amplified signal is output through the 1 st impedance transformation circuit 150_1 and the 3 rd radio frequency signal output terminal rfout_3.

The structures and functions of the functional blocks of other circuits in fig. 30 to 35, such as the 1 st drain bias circuit 120_1, the 1 st source bias circuit 140_1, the gate matching circuit 130, and the gate bias circuit 160, are the same as those of the above-described embodiments, and are not repeated here.

In the embodiment of the application, the amplifier only comprises one three-port transistor, and the power consumption of the three-port transistor determines the power consumption of the amplifier, so that the amplifier of the embodiment of the application realizes the gain superposition of two paths of amplifiers without multiplying the power consumption, thereby improving the gain and power consumption ratio of the amplifier. That is, the power consumption of the amplifier of the embodiment of the present application is equivalent to only one common source amplifier or one source follower amplifier, but the gain is larger, and thus has a larger gain to power consumption ratio.

In the prior art, if two amplifiers are simply combined, that is, two amplifiers amplify and output the same input signal at the same time and then directly overlap, the power consumption of the combining circuit is multiplied because the two amplifiers respectively comprise a three-port transistor. The amplifier of the embodiment of the application ensures that the gains of the amplifiers are overlapped, but the power consumption is not multiplied due to the adoption of only one three-port transistor, thereby improving the power-to-power consumption ratio of the amplifiers. That is, the gain of the embodiment of the application is equivalent to the gain of the superimposed signal after the two amplifiers are simply combined and amplified, but the power consumption is only half of that of the combined amplifier, so that the gain-to-power consumption ratio is larger.

In other embodiments of the present application, the three-port transistor 111 may be a transistor 1112, and then the first pole of the transistor 111 is the collector (C pole), the second pole is the emitter (E pole), and the third pole is the base (B pole).

In the application scenario when the circuit shown in fig. 36 is n=1, the first pole matching circuit 112_1 of the amplifier is the collector matching circuit 112_1, the second pole matching circuit 113_1 is the emitter matching circuit 113_1, the 1 st first pole biasing circuit 120_1 is the 1 st collector biasing circuit 120_1, the 1 st second pole biasing circuit 140_1 is the 1 st emitter biasing circuit 140_1, the third pole biasing circuit 160 is the base biasing circuit 160, and the amplifier further includes the impedance transformation circuit 150.

As shown in fig. 36, the amplifier can be divided into two amplifiers, a common emitter amplifier and an emitter follower amplifier, respectively, based on the amplification principle of the radio frequency signal of the transistor 1112. At this time, there may be different power supply modes according to different bias modes.

The single power supply can be that a collector bias power supply end VC supplies voltage VC to a collector, a collector bias power supply end VC supplies power voltage of a current mirror, a current mirror generates base bias current IB, an emitter bias power supply end VE is grounded, and the collector voltage VC and the base current IB jointly provide bias for a triode; or by an emitter bias supply terminal VE, which supplies the current mirror with a base current IB, which together provide the bias for the transistor (PNP) (VE and IB are not shown in the figure).

The dual supply may provide a voltage VC to the collector from a collector bias supply terminal VC and a base current IB (IB not shown in the figures) to the base from a base bias supply terminal IB.

The three power supplies are collector voltage VC from collector bias supply terminal VC, emitter bias supply terminal VE from emitter voltage VE from emitter, and base current IB from base bias supply terminal IB from base (VE and IB are not shown).

When the amplifier adopts the triode 1112, the synthesis of the amplified signals can be direct synthesis; or may be synthesized using a synthesis circuit, which is not described in detail herein.

When the amplifier adopts the triode 1112, the working principle, the circuit configuration mode, the generated beneficial effects and the like are the same as or similar to those of the above embodiment, but part of the circuits can be adjusted according to the actual application scene, and are not repeated here.

As described above, the amplifier according to the embodiment of the present application adopts the triode 1112 to amplify the radio frequency input signal in two ways, that is, two ways of amplification of the radio frequency signal through the common emitter amplifier and the emitter follower amplifier are realized; in addition, the amplifier of the embodiment of the application can synthesize the two paths of amplified signals, so that the signal amplitude of the amplifier is overlapped, and the amplifier has higher gain.

As described above, in the amplifier of the present application, when N is an integer greater than or equal to 1, the amplifier includes a three-port transistor, and the first pole matching circuit includes N branches, and the second pole matching circuit also includes N branches, which can output 2N amplified signals, respectively, and one amplified signal output by the first pole matching circuit is combined with one amplified signal output by the second pole matching circuit, so that N combined amplified signals can be output, and the functional density of the amplifier is improved; in addition, the gain of the amplifier can be overlapped, so that the amplifier has higher gain; in the embodiment of the application, the amplifier only comprises one three-port transistor, and the power consumption of the three-port transistor determines the power consumption of the amplifier, so that the gain superposition of the multipath amplifier is realized without the power consumption being multiplied, and the power-to-power consumption ratio of the amplifier is improved.

Embodiments of the present application provide an amplifier and a radio frequency chip, the amplifier comprising a substrate, and an amplifier as described above on the substrate.

The chip can realize multipath amplification of radio frequency signals, and is not described herein.

The chip can realize multipath amplification of radio frequency signals and synthesis of amplified signals, and is not described herein.

The chip described above is still described by taking n=1 and a field effect transistor as an example. The low coupling inductance pair may not be included in the 1 st branch 112_1 of the first pole matching circuit 112, the 1 st branch 113_1 of the second pole matching circuit 113, and the third pole matching circuit 130; or at least one pair may be a low-coupling inductance pair, for example, a low-coupling inductance pair formed by the first inductance l1_1 of the 1 st branch and the second inductance l2_1 of the 1 st branch, a low-coupling inductance pair formed by the fourth inductance l4_1 of the 1 st branch and the fifth inductance l5_1 of the 1 st branch, or any one pair, or any two pairs, or three pairs of low-coupling inductance pairs formed by the sixth inductance L6 and the seventh inductance L7, and the specific structure is described with reference to the above embodiment and will not be repeated here.

In the embodiment of the application, the inductance in the low-coupling inductance pair can be a single-layer wiring spiral inductance or a multi-layer wiring spiral inductance.

When a signal is excited on the inductor, an induced magnetic field is generated, an induced electric field is generated by the induced magnetic field, and an induced eddy current is generated in the substrate of the chip by the induced electric field, so that energy loss is generated.

The chip in the embodiment of the application includes the amplifier, and the amplifier may include a low-coupling inductance pair, for example, the first inductance l1_1 of the 1 st branch and the second inductance l2_1 of the 1 st branch are low-coupling inductance pairs, and the directions of the induced magnetic fields on the first inductance l1_1 of the 1 st branch and the second inductance l2_1 of the 1 st branch are opposite, so that the directions of the induced electric field generated by the induced magnetic field of the first inductance l1_1 of the 1 st branch and the induced electric field generated by the induced magnetic field of the second inductance l2_1 of the 1 st branch are opposite, the directions of induced eddy currents generated by the two opposite induced electric fields are opposite, and the induced eddy currents with opposite directions can be partially offset, so that the induced eddy currents are reduced, the generated energy loss is reduced, and the energy loss of the chip matching network is reduced.

In the embodiment of the application, in the 1 st branch 112_1 of the drain matching circuit 112 of the amplifying circuit in the chip, the directions of the induced magnetic fields of the 1 st branch first inductor L1_1 and the 1 st branch second inductor L2_1 are opposite, so that the induced eddy current in the substrate can be partially counteracted, and the energy loss is reduced. In addition, the physical distance between the 1 st branch first inductor L1_1 and the 1 st branch second inductor L2_1 can be closer, and the physical distance between the low-coupling inductor pair and other devices can be closer, so that the size of a chip can be reduced, and the cost is reduced.

In the chip of the embodiment of the present application, the effects of the low coupling inductance pair formed by the inductance pair with opposite induced magnetic fields are as described above, and are not described herein.

As shown in fig. 37, the radio frequency chip 2000 may include an amplifier 2001, wherein the amplifier 2001 may be any embodiment of an amplifier as described above. One amplifier 2001 may be used alone, or a plurality of amplifiers 2001 may be used in combination. In an example, the radio frequency chip 2000 may include one or more amplifiers 2001.

In embodiments of amplifiers and radio frequency chips employing low coupling inductance pairs, the layout of the low coupling inductance pairs greatly affects the size of the circuit dimensions. When the inductor is excited by a signal, an induced magnetic field is generated, an induced electric field is generated by the induced magnetic field, and radiation is generated by the induced electric field, so that energy loss is generated. For example, an induced electric field may generate eddy currents in a circuit medium and electromagnetic radiation in space. This loss is exacerbated if two inductors are placed in close proximity, which can create mutual coupling between them. According to the embodiment of the application, the mutual coupling between the two inductors is at least partially reduced by configuring the two inductors of the low-coupling inductor pair to have opposite directions of the generated induced magnetic fields, so that the directions of the induced electric fields caused by the induced magnetic fields of the two inductors are also opposite, and the induced electric fields are partially or completely counteracted, thereby reducing or eliminating the energy loss caused by the induced electric fields, and further reducing the chip area occupied by the amplifier by arranging the two inductors of the low-coupling inductor pair to be closer.

For example, the 1 st branch first inductor l1_1 and the 1 st branch second inductor l2_1 of the low coupling inductance pair may be disposed to be adjacent to each other such that the direction of the induced magnetic field generated by the 1 st branch first inductor l1_1 is opposite to the direction of the induced magnetic field generated by the 1 st branch second inductor l2_1.

In one example, the 1 st branch first inductor l1_1 and the 1 st branch second inductor l2_1 are spiral inductors, which may be arranged in the amplifier with opposite spiral directions. For example, the spiral direction of one inductor is clockwise and the other is counter-clockwise.

In one example, the 1 st branch first inductance l1_1 and the 1 st branch second inductance l2_1 are arranged as mirror images of each other in the amplifier.

Fig. 38 shows a schematic diagram of the placement of low coupling inductance pairs in an amplifier according to an embodiment of the application. Fig. 38 is a schematic diagram of a low coupling inductance pair of an amplifier looking down from a direction perpendicular to the wiring layers of the amplifier. In one example, the amplifier may be a radio frequency chip.

As shown in fig. 38, the low-coupling inductance pair includes two inductances, which are respectively composed of a first microstrip line 1314 and a second microstrip line 1315, and the first microstrip line 1314 is wound into a first spiral pattern W1 and the second microstrip line 1315 is wound into a second spiral pattern W2. The first end 1311 and the second end 1312 of the first microstrip line 1314 are respectively the first end and the second end of the 1 st branch first inductor l1_1. The first end 1313 and the second end 1312 of the second microstrip 1315 are respectively the first end and the second end of the 1 st branch second inductor l2_1. The second end 1312 of the first microstrip line 1314 and the second end 1312 of the second microstrip line 1315 are connected together to form a common end 1312 of the 1 st branch first inductor l1_1 and the 1 st branch second inductor l2_1, and the first microstrip line 1314 and the second microstrip line 1315 form a combined microstrip line. The first end 1311 of the 1 st branch first inductor l1_1, the first end 1313 of the 1 st branch second inductor l2_1, the second ends 1312 of the 1 st branch first inductor l1_1 and the 1 st branch second inductor l2_1 are connected to the other parts of the amplifier by connecting wires, respectively.

The combined microstrip line (first microstrip line/second microstrip line) of the embodiment of the present application may be composed of a single layer or multiple layers of metal materials. In one example, the merged microstrip line is composed of multiple layers of metallic materials, with each layer of metallic material being located in a different wiring layer of the amplifier. And multiple layers of metal materials positioned in different wiring layers are overlapped together to form a combined microstrip line, and the metal materials of the layers are connected through interlayer through holes. In another example, the combined microstrip line is composed of a single layer of metal material, which may be located in the same or different wiring layers of the amplifier. For example, a portion of the single layer of metal material is located in one wiring layer and the other portion is located in a different wiring layer or layers. Likewise, the single layers of metal material located in the different wiring layers are connected by vias.

In the example of fig. 38, both spiral patterns W1 and W2 include multiple turns, it being understood that they may also each include one turn, or one include multiple turns and the other include multiple turns.

As an example, the first microstrip line 1314 and the second microstrip line 1315 may be wound in opposite directions such that the spiral directions of the first spiral pattern W1 and the second spiral pattern W2 are opposite, so that the directions of induced magnetic fields caused by currents in the microstrip lines forming the two spiral patterns W1 and W2 are opposite when the low coupling inductance pair is in an operating state. For example, one of W1 and W2 is made to spiral counterclockwise and the other is made to spiral clockwise. The direction from the first end of the 1 st branch first inductor l1_1 or the 1 st branch second inductor l2_1 to the common terminal may be referred to herein as a spiral direction, or the direction from the common terminal to the first end of the 1 st branch first inductor l1_1 or the 1 st branch second inductor l2_1 may be referred to herein as a spiral direction.

In the embodiment of fig. 38, the first microstrip line 1314 is wound in a first spiral pattern W1 in a counterclockwise direction from the first end 1311 to the common end 1312 in an inside-out manner (turns inside first and turns outside) and the second microstrip line 1315 is wound in a second spiral pattern W2 in a clockwise direction from the first end 1313 to the common end 1312 in an inside-out manner (turns inside first and turns outside) during winding. It will be appreciated that both may also be wound one inside-out, the other outside-in (outside-in turns then inside turns), or both. It will be appreciated that the microstrip line need not always be wound in an inside-out or outside-in direction when wound into a spiral pattern W1 or W2, but may be redirected one or more times. For example, it is first from inside to outside, and halfway from outside to inside, or vice versa.

In summary, each of the spiral patterns W1 and W2 may wind the microstrip line from the respective first end to the common end in one of the following manners:

from inside to outside;

from outside to inside;

a combination of the two.

In the embodiment of fig. 38, the two spiral patterns W1 and W2 do not overlap and are adjacent but at a distance D in a direction parallel to the wiring layer of the amplifier. In the embodiment of the present application, since the mutual coupling between the two inductors is low as described above, the two spiral patterns W1 and W2 can be arranged as close as possible (but without overlapping portions), thereby reducing the circuit size and the cost. In one example, the spacing between the two spiral patterns W1 and W2 (distance D as shown in fig. 38) may be at least about 3 microns. The "distance between two spiral patterns" as referred to herein refers to the distance between the microstrip lines of the two spiral patterns closest to each other. As shown in fig. 38, the distance D is the distance between adjacent outermost turns of W1 and W2. In practice, the minimum spacing between the two spiral patterns is determined by the chip manufacturing process.

In the example of fig. 38, the first microstrip line 1314 is equal in length to the second microstrip line 1315. That is, the common terminal 1312 is located at the midpoint of the combined microstrip line. It will be appreciated that the common terminal 1312 may be located at other locations, such as closer to W1 or W2, instead of at the midpoint of the combined microstrip line.

As shown in fig. 38, in this embodiment, the spiral patterns W1 and W2 are arranged in mirror images, both of which are mirror images, and are shown in axisymmetric arrangement in fig. 38. I.e. the spiral patterns W1 and W2 have the same configuration, e.g. the same number of turns, microstrip line linewidths, spacing between adjacent turns, etc., except that their patterns are reversed (winding wise reversed), both in a symmetrical/mirrored relationship with respect to a plane perpendicular to the wiring layer in between. W1 and W2 may not be arranged in mirror image, for example, W1 and W2 may have different configurations, for example, W1 and W2 may have different numbers of turns, microstrip line widths, or pitches between adjacent turns, etc., as long as the induced magnetic fields of the wound spiral patterns W1 and W2 are opposite in direction.

It will be appreciated that the arrangement of the first spiral pattern W1 and the second spiral pattern W2 in fig. 38 is interchangeable.

In the low-coupling inductor pair according to the above embodiment of the present application, the microstrip lines of the two inductors have a common terminal and are arranged in two spiral patterns with opposite spiral directions, and when an excitation signal is applied to the low-coupling inductor pair in an operating state, the excitation signal is shunted to the two spirals (microstrip lines of the two inductors) at the common terminal, so that the directions of induced magnetic fields generated by currents in the two spirals are opposite, thereby reducing mutual coupling/mutual inductance between the two inductors at least partially.

In the above-described inductor pair embodiment, as shown in fig. 38, the inductor pair is arranged in an integrated circuit chip to have three terminals: a common terminal 1312, a head terminal 1311 which is a first branch terminal of the inductor pair, and a tail terminal 1313 which is a second branch terminal of the inductor pair. As previously described, the three ends of the pair of inductors may be connected to an excitation signal or other circuit portion by leads. For example, a radio frequency excitation signal may be accessed from the common terminal 1312 of the pair of inductors, the radio frequency excitation signal being split at the common terminal 1312 to a first microstrip line (first inductor) and a second microstrip line (second inductor). The radio frequency excitation signal is typically a periodically varying signal, for example a sinusoidal signal. Let the excitation signal accessed at the common terminal 1312 be i _com ＝I _com Sin ωt. The excitation signal splits into two branches at the common terminal 1312, one flowing through the common terminal 1312 to a first spiral pattern W1 of a first branch terminal (head terminal) 1311 and the other flowing through the common terminal 1312 to a second spiral pattern W2 of a second branch terminal (tail terminal) 1313. Let the excitation signal in the first spiral pattern W1 be i ₁ (t) the excitation signal in the first spiral pattern W1 is i ₂ (t) assuming no reflection of the signal, i ₁ (t)+i ₂ (t)＝I _com Sin ωt. If the common terminal is located at the midpoint of the combined microstrip line, and W1 and W2 are axisymmetric graphs In this case, the excitation signals at any time W1 and W2 are identical, i.eExcitation signal i in an inductor pair ₁ (t) and i ₂ (t) is a periodically varying signal whose current magnitude varies periodically and thus the induced magnetic field produced is also periodically varying unevenly; the changing magnetic field in turn generates an electric field, thereby generating electromagnetic waves. When the excitation signals in W1 and W2 are identical, since the spiral directions of W1 and W2 are opposite, the induced magnetic field generated by W1 at any time is the same as the induced magnetic field generated by W2 in the opposite direction, and the corresponding induced electric field is also in the opposite direction and periodically changes direction. Therefore, the induced magnetic fields generated by W1 and W2 are almost completely cancelled in many areas and partially cancelled in some areas, so that the corresponding electric fields or electromagnetic waves caused by the induced magnetic fields are cancelled, thereby reducing the loss of the inductance pair.

If the common terminal is not located at the midpoint of the combined microstrip line, or if W1 and W2 are patterns with different configurations, it may not be ensured that the excitation signals in W1 and W2 are identical, so that the degree of mutual cancellation of the induced magnetic fields of W1 and W2 is reduced compared with the case where the excitation signals in W1 and W2 are identical, but the induced magnetic fields generated by W1 and W2 still partially cancel each other at any moment, so that the electromagnetic radiation intensity is weakened mutually, and the loss of the inductance pair is reduced to some extent.

It should be noted that, theoretically, the pair of inductors having three ports (the common port, the head end of the combined microstrip line as the first branch port, and the tail end of the combined microstrip line as the second branch port) as described above is a passive lossless network, and since the passive network has reciprocity, the loss of the pair of inductors and the transmission characteristics thereof are reciprocal regardless of which one of the three ports the excitation signal is input from.

The low coupling inductance pair consisting of the 1 st branch first inductance l1_1 and the 1 st branch second inductance l2_1 in the amplifier may be arranged as described above. The above description of the low coupling inductance pairs applies to all low coupling inductance pairs referred to herein and will not be repeated elsewhere herein for brevity.

In the various amplifier embodiments described above, the low coupling inductance pair described above is used, which gives the amplifier of the present application the following advantages: by configuring the two inductors making up the inductor pair such that their respective induced magnetic fields are opposite in direction, making the inductor pair a low coupling inductor pair, the loss of the amplifier input matching circuit can be reduced. In addition, since the coupling between the two inductors constituting the low-coupling inductor pair and the radiation ranges of the induced electric field and the induced magnetic field of the inductors can be reduced in this way, the inductors and other components are disposed closer together, further reducing the circuit size.

The embodiment of the application also provides an electronic device, which comprises the radio frequency chip, and the radio frequency chip comprising the amplifier embodiment of the application can be used in the electronic device.

As shown in fig. 39, the electronic device 3000 includes a radio frequency chip 2000 as shown in fig. 37. The electronic device 3000 may be a wireless device or any other electronic device that may use an amplifier.

The wireless device may be a User Equipment (UE), mobile station, terminal, access terminal, subscriber unit, base station, or the like. The wireless device may also be a cellular telephone, a smart phone, a tablet computer, a wireless modem, a Personal Digital Assistant (PDA), a handheld device, a laptop computer, a smart book, a netbook, a cordless telephone, a Wireless Local Loop (WLL) station, a bluetooth device, etc. The wireless device may be capable of communicating with a wireless communication system, may be capable of receiving signals from a broadcast station, signals from one or more satellites, and the like. A wireless device may support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter waves, etc.).

The embodiment of the application provides an amplifier, a radio frequency chip and an electronic device, wherein the amplifier comprises: the three-port transistor further comprises a first pole matching circuit, a second pole matching circuit and the like, wherein the first pole matching circuit comprises N branches, and the second pole matching circuit also comprises N branches. The branch of each first pole matching circuit and the three-port transistor can form an amplifying link to output N paths of amplifying signals; the branch of each second pole matching circuit and the three-port transistor can also form an amplifying link to output N amplified signals, so that the amplifier can output 2N amplified signals in total. In the embodiment of the application, one amplified signal output by the first pole matching circuit is combined with one amplified signal output by the second pole matching circuit, so that N combined amplified signals can be output, and the functional density of the amplifier is improved; in addition, the gain of the amplifier can be overlapped, so that the amplifier has higher gain. In the embodiment of the application, the amplifier only comprises one three-port transistor, and the power consumption of the three-port transistor determines the power consumption of the amplifier, so that the amplifier of the embodiment of the application realizes the gain superposition of the multipath amplifier without the power consumption being multiplied, thereby improving the power-to-power consumption ratio of the amplifier.

In the embodiment of the present application, the functional units with the same reference numerals in the drawings have the same or similar functions, and are not described herein.

The amplifier in the embodiment of the application can be independently used or can be used in multi-stage cascade connection or can be used in cascade connection with circuits with other various functions; the radio frequency chip of the embodiment of the application can also comprise an independently used amplifier, or can comprise a plurality of amplifiers used in combination, or can comprise a plurality of independently used amplifiers; the radio frequency chip of this embodiment of the application may be used independently, or may be used in a multi-stage combination, or may be used in combination with other chips/circuits of various functions.

In the embodiment of the present application, the bias circuits of the poles of the three-port transistor respectively include multiple implementation forms, and these implementation forms may also be applied in other circuits, or may be combined with other implementation forms, or combined with each other, which are not described herein again.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to requirements, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the functions described above. The functional units and modules in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. In addition, the specific names of the functional units and modules are only for convenience of distinguishing each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the context, and will not be described herein.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any embodiment, reference is made to the related descriptions of other embodiments.

The units or modules described as separate components may or may not be physically separate, and components shown as units or modules may or may not be physical units, may be located in one place, or may be distributed over a plurality of functional units. Some or all of the units or modules may be selected according to actual needs to achieve the purpose of the embodiment.

In addition, each functional unit or module in each embodiment of the present application may be integrated in one chip unit, or each unit or module may exist alone physically, or two or more units or modules may be integrated in one unit.

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing is only a specific embodiment of the application to enable those skilled in the art to understand or practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An amplifier, the amplifier comprising:

a first pole matching circuit comprising N branches,

2. The amplifier of claim 1, wherein the jth amplified signal is combined with the n+j amplified signal;

3. The amplifier of claim 2, wherein the j-th amplified signal is combined with the n+j-th amplified signal, comprising:

4. The amplifier of claim 3, further comprising:

a number of N impedance transformation circuits,

5. The amplifier of claim 2, wherein the amplifier further comprises N combining circuits,

6. The amplifier of claim 5, further comprising:

a number of N impedance transformation circuits,

7. The amplifier of claim 1, wherein the amplifier further comprises:

8. The amplifier of claim 1, wherein the j-th branch of the first polar matching circuit comprises:

9. The amplifier of claim 8, wherein the j-th branch of the second stage matching circuit comprises:

10. The amplifier of claim 7, wherein the third pole matching circuit comprises:

11. The amplifier of claim 10, the j-th leg first inductive element and the j-th leg second inductive element being an inductive pair with opposing induced magnetic fields; and/or

12. The amplifier of claim 10, wherein the third pole bias circuit comprises:

13. The amplifier of claim 12, wherein the j-th second stage bias circuit comprises:

14. The amplifier of claim 12, wherein the j-th second bias circuit is ground;

15. The amplifier of claim 10, wherein the third pole bias circuit is ground.

16. The amplifier of claim 15, wherein the j-th second stage bias circuit comprises:

17. The amplifier of claim 7, wherein the j-th first pole bias circuit comprises:

18. A radio frequency chip comprising a substrate, and the amplifier of any one of claims 1 to 17 on the substrate.

19. An electronic device comprising the radio frequency chip of claim 18.