CN218071442U

CN218071442U - Amplifier, radio frequency chip and electronic device

Info

Publication number: CN218071442U
Application number: CN202220770479.7U
Authority: CN
Inventors: 刘石生; 黄伟
Original assignee: Shenzhen Jingzhun Communication Technology Co ltd
Current assignee: Shenzhen Jingzhun Communication Technology Co ltd
Priority date: 2022-04-01
Filing date: 2022-04-01
Publication date: 2022-12-16
Anticipated expiration: 2032-04-01

Abstract

The embodiment of the application discloses an amplifier, a radio frequency chip and an electronic device. The amplifier includes: the field effect transistor comprises a drain electrode, a grid electrode and a source electrode, and is used for amplifying signals; the first end of the drain electrode matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain electrode matching circuit is connected with the radio frequency signal output end; the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end; the grid biasing circuit is connected with the third end of the grid matching circuit; the source electrode matching circuit is connected with the source electrode of the field effect transistor; the grid matching circuit comprises a low coupling inductance pair, and the coupling inductance pair is an inductance pair with opposite induction magnetic field directions. The power consumption of the embodiment of the application is small, the size is small, the cost is low, and the noise is low.

Description

Amplifier, radio frequency chip and electronic device

Technical Field

The application relates to the technical field of electronics, in particular to an amplifier, a radio frequency chip and an electronic device.

Background

With the development of communication technology, especially the emergence of 5G technology, high frequency wireless communication technology is becoming an important development direction of wireless communication.

The performance of the amplifier can have a significant impact on the performance of the rf transceiver system. Therefore, the high frequency wireless communication technology puts higher demands on the performance and cost of the amplifier, such as integration, noise performance, power consumption, and the like.

The existing radio frequency or high frequency amplifier chip is mostly composed of elements such as transistors, lumped parameter element inductors, lumped parameter element capacitors, resistors, microstrip lines and the like. In the element, an inductor, a microstrip line, a capacitor, etc. may generate electromagnetic radiation and other induced magnetic or electric fields, etc. due to signal excitation, and these physical fields may affect the arrangement and normal operation of other elements. In designing or manufacturing an amplifier, in order to solve the problem of electromagnetic compatibility between elements, there is a method of achieving electromagnetic compatibility by maintaining a large arrangement pitch of the elements, which results in a large size of the amplifier, inconvenience in high-density integration, and inconvenience in cost reduction. In addition, electromagnetic radiation, induced magnetic fields or electric fields can cause energy losses, sacrificing amplifier performance. In order to realize popularization of high-frequency wireless communication technology, reduction of cost of components and improvement of performance of the components are problems which need to be solved urgently.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problems or at least partially solve the technical problems, an amplifier, a radio frequency chip and an electronic device are provided.

In a first aspect, the present application provides an amplifier comprising:

the field effect transistor comprises a drain electrode, a grid electrode and a source electrode, and is used for amplifying signals;

the first end of the drain electrode matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain electrode matching circuit is connected with the radio frequency signal output end;

the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end;

the grid biasing circuit is connected with the third end of the grid matching circuit;

the source electrode matching circuit is connected with the source electrode of the field effect transistor;

the grid matching circuit comprises a low coupling inductance pair, and the coupling inductance pair is an inductance pair with opposite induction magnetic field directions.

In an embodiment of the present application, the low coupling inductor pair includes:

a second end of the third inductor is connected with the grid electrode of the field effect transistor;

a first end of the fourth inductor is connected with a first end of the third inductor, and a second end of the fourth inductor is connected with the gate bias circuit;

wherein the third inductor and the fourth inductor have opposite induction magnetic field directions.

In an embodiment of the present application, the gate matching circuit further includes:

and the first end of the third capacitor is connected with the radio-frequency signal input end, and the second end of the third capacitor is connected with the first end of the third inductor.

In an embodiment of the present application, the gate bias circuit includes:

and a first end of the fourth capacitor is grounded, and a second end of the fourth capacitor is connected with a grid bias power supply end.

In an embodiment of the present application, the source matching circuit includes:

a fifth inductive unit, wherein a first end of the fifth inductive unit is connected with the source electrode of the field effect transistor, and a second end of the fifth inductive unit is grounded;

wherein, the fifth inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.

In the embodiment of the present application, the source matching circuit is a ground.

In the embodiment of the present application, the gate bias circuit is ground.

a sixth inductive unit, a first end of which is connected with the source electrode of the field effect transistor;

a fifth capacitor, a first end of the fifth capacitor being connected to the second end of the sixth inductive unit, a second end of the fifth capacitor being grounded;

a first resistor, a first end of which is connected to the second end of the sixth inductive unit, and a second end of which is grounded;

the sixth inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.

a first end of the seventh inductive unit is connected with the source electrode of the field effect transistor;

a sixth capacitor, a first end of which is connected to the second end of the seventh inductive unit, and a first end of which is further connected to the source bias power supply terminal, and a second end of which is grounded;

the seventh inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.

In an embodiment of the present application, the drain matching circuit includes:

the first end of the first inductive unit is connected with the drain electrode of the field effect transistor;

a second inductive unit, a second end of the second inductive unit is connected with a second end of the first inductive unit, and a second end of the second inductive unit is connected with a drain electrode bias power supply end;

a first end of the first capacitor is connected with a second end of the first inductive unit, and a second end of the first capacitor is connected with the radio frequency signal output end;

a second capacitor, a first end of the second capacitor being connected to a second end of the second inductive unit, a second end of the second capacitor being grounded;

the first inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line, and/or the second inductive unit is one of the inductor, the microstrip line or the combination of the inductor and the microstrip line.

In the embodiment of the present application, the third inductor and the fourth inductor are both spiral inductors and are arranged in the amplifier so that the spiral directions are opposite.

In an embodiment of the present application, the third inductor and the fourth inductor are arranged in the amplifier in a mirror image arrangement with each other.

In this application embodiment, the third inductance comprises first microstrip line and first microstrip line is coiled into first spiral pattern, the fourth inductance comprises second microstrip line and second microstrip line is coiled into second spiral pattern, wherein the first end and the second end of first microstrip line are regarded as respectively the first end and the second end of third inductance, the first end and the second end of second microstrip line are regarded as respectively the first end and the second end of fourth inductance, the second end of first microstrip line with the second end of second microstrip line links together and makes first microstrip line with the second microstrip line forms a merge microstrip line.

In an embodiment of the present application, the first and second spiral patterns do not overlap and are adjacent to but at a distance from each other in a direction parallel to the wiring layers of the amplifiers.

In the embodiment of the present application, the merged microstrip line is formed by multiple layers of metal materials, where each layer of metal material is located in a different wiring layer of the amplifier.

In an embodiment of the present application, the merged microstrip line is formed by a single layer of metal material, where the single layer of metal material is located in the same or different wiring layers of the amplifier.

In a second aspect, there is provided a radio frequency chip comprising a substrate, and an amplifier as described above on the substrate.

In a third aspect, an electronic device is provided, which includes the rf chip as described above.

An embodiment of the present application provides an amplifier, including: the field effect transistor comprises a drain electrode, a grid electrode and a source electrode, and is used for signal amplification; the first end of the drain electrode matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain electrode matching circuit is connected with the radio frequency signal output end; the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end; the grid biasing circuit is connected with the third end of the grid matching circuit; the source electrode matching circuit is connected with the source electrode of the field effect transistor; the grid matching circuit comprises a low coupling inductance pair, and the coupling inductance pair is an inductance pair with opposite induction magnetic field directions. In the embodiment of the application, the low coupling inductance pair is an inductance pair with opposite directions of the induction magnetic fields, the directions of the induction electric fields generated by the pair of inductances with opposite directions of the induction magnetic fields are also opposite, and the induction electric fields with opposite directions can be partially offset, so that the radiation generated by the induction electric fields is reduced, and the energy loss of the circuit is reduced. In addition, because the induction electric fields are mutually offset, the physical distance of the inductors in the low-coupling inductor pair can be closer, so that the size of the amplifier can be reduced, the cost is reduced, and the noise is reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

FIG. 1 is a circuit schematic of an amplifier in an embodiment of the present application;

FIG. 2 is a circuit schematic of an amplifier in an embodiment of the present application;

FIG. 3 is a circuit schematic of an amplifier in an embodiment of the present application;

FIG. 4 is a circuit schematic of an amplifier in an embodiment of the present application;

FIG. 5 is a circuit schematic of an amplifier in an embodiment of the present application;

FIG. 6 is a diagram of an RF chip in an embodiment of the present application;

FIG. 7 is a schematic diagram of the arrangement of low coupled inductor pairs in an amplifier in an embodiment of the present application;

fig. 8 is a schematic diagram of an electronic device in an embodiment of the application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The amplifier provided by the embodiment of the application can be used as an independent component, or can be applied to radio frequency chip or system integration.

As shown in fig. 1, an embodiment of the present application provides an amplifier, including:

the field effect transistor 110 comprises an enhancement type field effect transistor and a depletion type field effect transistor, the field effect transistor 110 comprises a drain electrode, a grid electrode and a source electrode, and the field effect transistor 110 is used for signal amplification;

a drain matching circuit 120, wherein a first end of the drain matching circuit 120 is connected to the drain of the field effect transistor 110, and a second end of the drain matching circuit 120 is connected to a radio frequency signal output end RFOUT;

a gate matching circuit 130, wherein a first terminal of the gate matching circuit 130 is connected to the gate of the fet 110, and a second terminal of the gate matching circuit 130 is connected to the radio frequency signal input terminal RFIN;

a source matching circuit 140 connected to the source of the fet 110;

a gate bias circuit 150, wherein the gate bias circuit 150 is connected to the third terminal of the gate matching circuit 130;

the gate matching circuit 130 includes a pair of low-coupling inductors 131, and the pair of low-coupling inductors 131 is an inductor pair with opposite directions of an induced magnetic field.

In the field effect transistor 110 in the embodiment of the present application, the three electrodes are a Source electrode (Source, S electrode), a Gate electrode (Gate, G electrode) and a Drain electrode (Drain, D electrode), respectively, for amplifying a radio frequency signal, and details are not repeated herein.

In the embodiment of the present application, the drain matching circuit 120 is configured to match the drain output impedance of the fet 110 to a first target impedance, which is the output impedance of the amplifier rf signal output terminal RFOUT.

In the embodiment of the present application, the gate matching circuit 130 is configured to match the gate input impedance of the fet 110 to a second target impedance, which is the input impedance of the amplifier rf signal input terminal RFIN.

In the embodiment of the present application, as shown in fig. 1 and fig. 2, the low-coupling inductor pair 131 includes:

a second end of the third inductor L3 is connected to the gate of the fet 110;

a first end of the fourth inductor L4 is connected to the first end of the third inductor L3, and a second end of the fourth inductor L4 is connected to the gate bias circuit 150;

wherein, the induced magnetic field directions of the third inductor L3 and the fourth inductor L4 are opposite.

In the embodiment of the present application, the third inductor L3 and the fourth inductor L4 may be planar spiral inductors, and a spiral direction of the third inductor L3 is opposite to a spiral direction of the fourth inductor L4.

In other embodiments of the present application, the third inductor L3 and the fourth inductor L4 may also be other structures and physical layouts capable of realizing opposite directions of the induced magnetic field, and are not described herein again.

When the inductor is excited by a signal, an induction magnetic field can be generated, an induction electric field can be generated by the induction magnetic field, and radiation can be generated by the induction electric field, so that energy loss is generated; therefore, the third inductor L3 and the fourth inductor L4 also have an induced magnetic field, and an induced electric field generated by the induced magnetic field generates energy loss.

In the embodiment of the present application, the directions of the induction magnetic fields of the third inductor L3 and the fourth inductor L4 are opposite, so that the directions of the induction electric field generated by the induction magnetic field of the third inductor L3 and the induction electric field generated by the induction magnetic field of the fourth inductor L4 are also opposite, and the two opposite induction electric fields can be partially offset, so that the radiation generated by the induction electric fields is reduced, and the energy loss is reduced.

Because the induced electric field between the third inductor L3 and the fourth inductor L4 is partially offset, the physical distance between the third inductor L3 and the fourth inductor L4 can be closer, so that the size of the circuit can be reduced, and the cost can be reduced.

In the embodiment of the present application, the gate matching circuit 130 includes a pair of low-coupling inductors 131, and the pair of low-coupling inductors 131 is a pair of inductors L3 and L4 with opposite directions of the induced magnetic field, so as to reduce mutual coupling and reduce energy loss. In addition, the physical distance between the third inductor L3 and the fourth inductor L4 can be closer, which can reduce the size of the circuit and the cost.

In this embodiment, as shown in fig. 2, the gate matching circuit 130 further includes:

a third capacitor C3, a first end of the third capacitor C3 is connected to the radio frequency signal input terminal RFIN, and a second end of the third capacitor C3 is connected to the first end of the third inductor L3.

The gate bias circuit 150 includes:

and a first end of the fourth capacitor C4 is grounded, and a second end of the fourth capacitor C4 is connected with a gate bias power supply end VG.

In the embodiment of the present application, the third capacitor C3, the fourth capacitor C4 and the low-coupling inductor pair 131 form an amplifier input matching network, which is used to match the gate input impedance of the field effect transistor 110 to a second target impedance.

In the embodiment of the present application, the resonant point frequency of the fourth capacitor C4 is close to or the same as the center frequency of the operating frequency band of the amplifier, and is used for realizing the isolation of the amplifier from the radio frequency signal of the gate bias power supply terminal VG and providing a radio frequency signal ground for the second terminal of the fourth inductor L4.

In the embodiment of the present application, as shown in fig. 2, the source matching circuit 140 includes:

a fifth inductive unit L5, a first end of the fifth inductive unit L5 is connected to the source of the fet 110, and a second end of the fifth inductive unit L5 is grounded;

the fifth sensing unit L5 is one of an inductor, a microstrip, or a combination of an inductor and a microstrip.

In the embodiment of the present application, by adjusting the parameter of the fifth sensing unit L5, the optimal noise impedance of the fet 110 and the optimal gain matching impedance of the fet 110 can be adjusted to be approximately consistent, so as to reduce the noise of the amplifier and improve the performance of the amplifier.

In the embodiment shown in fig. 2, the gate bias voltage VG is provided to the fet 110 through the gate bias power source terminal VG, and the drain bias voltage VD is provided to the fet 110 through the drain bias power source terminal VD, so as to maintain the fet 110 working normally. The rf signal is input through the rf signal input terminal RFIN, passes through the gate matching circuit 130, drives the gate of the fet 110, is amplified by the fet 110, passes through the drain matching circuit 120, and is output through the rf signal output terminal RFOUT.

In the embodiment of the present application, the low-coupling inductor pair 131 is an inductor pair with opposite directions of the induced magnetic field, which can reduce energy loss in the corresponding gate matching circuit 130, reduce the circuit size, and reduce the cost. In addition, in the embodiment of the present application, the low coupling inductor pair 131 is adopted, so that the area is reduced, and the noise of the amplifier is favorably reduced.

In the embodiment of the present application, as shown in fig. 3, the source matching circuit 140 is a ground.

In a specific application scenario of the embodiment of the present application, in the source matching circuit 140, the source matching circuit 140 is ground, i.e., the source of the fet 110 may be directly grounded, as shown in fig. 3.

In the embodiment shown in fig. 3, the gate bias voltage VG is provided to the fet 110 through the gate bias power source terminal VG, and the drain bias voltage VD is provided to the fet 110 through the drain bias power source terminal VD, so as to maintain the fet 110 working normally. The rf signal is input through the rf signal input terminal RFIN, passes through the gate matching circuit 130, drives the gate of the fet 110, is amplified by the fet 110, passes through the drain matching circuit 120, and is output through the rf signal output terminal RFOUT.

In the embodiment of the present application, the low-coupling inductor pair 131 is an inductor pair with opposite directions of the induced magnetic field, which can reduce energy loss in the corresponding gate matching circuit 130, reduce the circuit size, and reduce the cost.

In the embodiments shown in fig. 2 and 3 of the present application, the gate bias voltage VG needs to be provided, and in the embodiment shown in fig. 4 of the present application, a single power supply self-bias amplifier may be used, so that the gate bias voltage VG does not need to be provided.

As shown in fig. 4, in the embodiment of the present application, the gate bias circuit 150 is a ground.

As shown in fig. 4, in the embodiment of the present application, the source matching circuit 140 includes:

a sixth inductive unit L6, wherein a first end of the sixth inductive unit L6 is connected to the source of the fet 110;

a fifth capacitor C5, a first end of the fifth capacitor C5 being connected to the second end of the sixth inductive unit L6, and a second end of the fifth capacitor C5 being grounded;

a first resistor R1, a first end of the first resistor R1 being connected to the second end of the sixth inductive unit L6, and a second end of the first resistor R1 being grounded;

the sixth inductive unit L6 is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

In the embodiment of the present application, by adjusting the parameter of the sixth inductive unit L6, the optimal noise impedance of the fet 110 and the optimal gain matching impedance of the fet 110 can be adjusted to be approximately consistent, so as to reduce the noise of the amplifier and improve the performance of the amplifier.

In the embodiment of the present application, the fifth capacitor C5 couples the rf signal output by the source of the fet 110 and passing through the sixth inductive unit L6 to the ground, so as to reduce the energy loss of the source matching circuit 140.

In the embodiment of the present application, the first resistor R1 is used to raise the source potential of the fet 110, so that the gate-to-source voltage of the fet 110 is a negative value, and the normal operation of the amplifier is maintained.

In the embodiment shown in fig. 4, a drain bias voltage VD is provided to the fet 110 through the drain bias power source terminal VD, and at this time, the drain-source current of the fet 110 flows through the resistor R1 in the source matching circuit 140, so as to raise the source potential of the fet 110, so that the gate-source voltage of the fet 110 is negative, and the normal operation of the fet 110 is maintained. The rf signal is input through the rf signal input terminal RFIN, passes through the gate matching circuit 130, drives the gate of the fet 110, is amplified by the fet 110, passes through the drain matching circuit 120, and is output through the rf signal output terminal RFOUT.

In the embodiment of the present application, the gate matching circuit 130 includes the low coupling inductor pair 131, and the low coupling inductor pair 131 is an inductor pair with opposite directions of the induced magnetic field, so that energy loss in the corresponding gate matching circuit 130 can be reduced, the circuit size is reduced, the cost is reduced, and noise is reduced.

In the embodiment of the present application, an implementation of an amplifier is also provided, as shown in fig. 5.

The gate bias circuit 150 is connected to a gate bias supply terminal VG, i.e. the second terminal of the capacitor C4 is connected to the gate bias supply terminal VG.

As shown in fig. 5, in this case, the source matching circuit 140 includes:

a seventh inductive unit L7, wherein a first end of the seventh inductive unit L7 is connected to the source of the fet 110;

a sixth capacitor C6, a first end of the sixth capacitor C6 is connected to the second end of the seventh inductive unit L7, the first end of the sixth capacitor C6 is further connected to the source bias power supply terminal VS, and a second end of the sixth capacitor C6 is grounded;

the seventh inductive unit L7 is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

In the embodiment of the present application, by adjusting the parameter of the seventh sensing unit L7, the optimal noise impedance of the fet 110 and the optimal gain matching impedance of the fet 110 can be adjusted to be approximately consistent, so as to reduce the noise of the amplifier and improve the performance of the amplifier.

In this embodiment, the resonant point frequency of the sixth capacitor C6 is close to or the same as the center frequency of the operating frequency band of the amplifier, and is used to implement isolation of the amplifier from the rf signal of the source bias power source terminal VS, and provide an rf signal ground for the second terminal of the seventh inductive unit L7.

In the embodiment shown in fig. 5, a gate bias voltage VG is provided to the amplifier through a gate bias power supply terminal VG, a drain bias voltage VD is provided to the amplifier through a drain bias power supply terminal VD, a source bias voltage VS is provided to the amplifier through a source bias power supply terminal VS, a voltage difference between VG and VS is adjusted to be the gate-source bias power supply in the normal operating state of the field-effect transistor 110, a voltage difference between VD and VS is adjusted to be the drain-source bias power supply in the normal operating state of the field-effect transistor 110, and the field-effect transistor 110 is in the normal operating state. The rf signal is input through the rf signal input terminal RFIN, passes through the gate matching circuit 130, drives the gate of the fet 110 in the amplifier, is amplified by the fet 110, passes through the drain matching circuit 120, and is output through the rf signal output terminal RFOUT.

In the embodiment of the present application, the gate matching circuit 130 includes the low coupling inductance pair 131, and the low coupling inductance pair 131 is an inductance pair with opposite directions of the induction magnetic field, so that energy loss in the corresponding gate matching circuit 130 can be reduced, the circuit size is reduced, the cost is reduced, and the noise is reduced.

As shown in fig. 2 to 5, the drain matching circuit 120 includes:

a first inductive unit L1, a first end of the first inductive unit L1 being connected to the drain of the fet 110;

a second inductive unit L2, a second end of the second inductive unit L2 being connected to a second end of the first inductive unit L1, a second end of the second inductive unit L2 being connected to the drain bias power supply terminal VD;

a first capacitor C1, a first end of the first capacitor C1 is connected to a second end of the first inductive unit L1, and a second end of the first capacitor C1 is connected to the rf signal output terminal RFOUT;

a second capacitor C2, a first end of the second capacitor C2 being connected to a second end of the second inductive unit L2, a second end of the second capacitor C2 being grounded;

the first inductive unit L1 is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line, and/or the second inductive unit L2 is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line.

In this embodiment, the resonant point frequency of the second capacitor C2 is close to or the same as the center frequency of the operating frequency band of the amplifier, and is used to achieve the isolation of the amplifier from the rf signal of the drain bias power source terminal VD, and simultaneously provide the rf signal ground for the second end of the second inductive unit L2.

In the embodiment of the application, the power supply bias modes of the amplifier include single power supply self-bias, double power supply bias and triple power supply bias, and the single power supply self-bias refers to that only a drain bias power supply VD is provided from the outside, as shown in fig. 4; the dual power bias means that a drain bias power supply VD and a gate bias power supply VG are provided by the outside, as shown in FIGS. 2 and 3; the three-power bias means that a gate bias power supply VD, a gate bias power supply VG, and a source bias power supply VS are supplied from the outside, as shown in fig. 5. The single power supply is simple in self-bias power supply, the double power supply can exert better power performance, the three power supply biases are beneficial to energy conservation, and a power supply bias mode can be configured according to practical application. The power supply bias mode of the embodiment of the present application may also be used in other circuits, and is not described herein again.

In some application scenarios, the sixth inductive unit L6 and the seventh inductive unit L7 may be omitted in the embodiments shown in fig. 4 and 5, without affecting the operation and function of the amplifier in the embodiments.

The embodiment of the application also provides a radio frequency chip, which comprises a substrate and the amplifier on the substrate.

As shown in fig. 1, the amplifier includes:

a field effect transistor 110;

a source matching circuit 140 connected to the source of the fet 110;

the gate matching circuit 130 includes a low-coupling inductor pair 131, and the coupling inductor pair 131 is an inductor pair with opposite directions of an induced magnetic field.

a second end of the third inductor L3 is connected to the gate of the fet 110;

In other embodiments of the present application, the third inductor L3 and the fourth inductor L4 may also be other structures and physical layouts capable of realizing opposite directions of the induced magnetic field, which are not described herein again.

When the inductor is excited by a signal, an induction magnetic field can be generated, the induction magnetic field can generate an induction electric field, and the induction electric field can generate induction eddy current in the substrate of the chip, so that energy loss is generated; therefore, there are also induced magnetic fields on the inductors L3 and L4, and the induced electric field generated by the induced magnetic fields generates induced eddy currents in the substrate of the chip, thereby generating energy loss.

In the embodiment of the present application, the directions of the induced magnetic fields of the third inductor L3 and the fourth inductor L4 are opposite, so that the directions of the induced electric fields generated by the induced magnetic fields of the third inductor L3 and the induced electric fields generated by the induced magnetic fields of the fourth inductor L4 are also opposite, the directions of the induced eddy currents generated by the two opposite induced electric fields are opposite, the induced eddy currents with opposite directions can be partially offset, so that the induced eddy currents are reduced, the generated energy loss is reduced, and the energy loss of the chip matching network is reduced.

Because the induced eddy current generated by the third inductor L3 and the fourth inductor L4 on the substrate is partially cancelled, the physical distance between the third inductor L3 and the fourth inductor L4 can be closer, so that the size of the circuit can be reduced, and the cost can be reduced.

In the embodiment of the present application, in the gate matching circuit 130 of the amplifying circuit in the chip, the directions of the induced magnetic fields of the third inductor L3 and the fourth inductor L4 are opposite, so that the induced eddy current in the substrate can be partially cancelled, and the energy loss can be reduced. In addition, the physical distance between the third inductor L3 and the fourth inductor L4 can be closer, which can reduce the size of the chip and reduce the cost.

The specific implementation of the amplifier in the chip according to the embodiment of the present application is described with reference to the above embodiment and fig. 1 to 5, and is not described herein again.

Therefore, the radio frequency chip in the embodiment of the application has the advantages of low power consumption, low noise, small volume and low cost.

As shown in fig. 6, the radio frequency chip 1500 may include an amplifier 1501, where the amplifier 1501 may be any embodiment of the amplifier described above. One amplifier 1501 may be used alone, or a plurality of amplifiers 1501 may be used in combination. In an example, the radio frequency chip 1500 may include one or more amplifiers 1501.

In embodiments of the amplifier and rf chip that employ low coupling inductance pairs, the layout of the low coupling inductance pairs greatly affects the size of the circuit dimensions. When the inductor is excited by a signal, an induction magnetic field can be generated, the induction magnetic field can generate an induction electric field, and the induction electric field can generate radiation, so that energy loss is generated. For example, the induced electric field may generate eddy currents in the circuit medium and electromagnetic radiation in space. If two inductors are arranged close together, mutual coupling between them will occur, which aggravates this loss. The mutual coupling between the two inductors is at least partially reduced by configuring the two inductors of the low coupling inductor pair to generate opposite induction magnetic fields, so that the directions of the induction electric fields caused by the induction magnetic fields of the two inductors are also opposite, and the induction electric fields are partially or completely offset, thereby reducing or eliminating energy loss caused by the induction electric fields, and further enabling the two inductors of the low coupling inductor pair to be arranged at a closer distance so as to further reduce the chip area occupied by the amplifier.

For example, the third inductor L3 and the fourth inductor L4 of the low-coupling inductor pair 131 may be disposed to be adjacent to each other and such that the direction of the induced magnetic field generated by the third inductor L3 is opposite to the direction of the induced magnetic field generated by the fourth inductor L4.

In one example, the third inductor L3 and the fourth inductor L4 are both spiral inductors, which may be arranged in the amplifier with opposite spiral directions. For example, one inductor spirals clockwise and the other counterclockwise.

In one example, the third inductance L3 and the fourth inductance L4 are arranged in the amplifier as mirror image arrangements of each other.

Fig. 7 shows a schematic diagram of a low coupling inductance pair arrangement in an amplifier according to an embodiment of the present application. Fig. 7 is a schematic diagram of a low coupling inductance pair looking down the amplifier from a direction perpendicular to the wiring layers of the amplifier. In one example, the amplifier may be a radio frequency chip.

As shown in fig. 7, the low-coupling inductor pair 131 includes two inductors respectively formed by a first microstrip line 1314 and a second microstrip line 1315, wherein the first microstrip line 1314 is wound in a first spiral pattern S1, and the second microstrip line 1315 is wound in a second spiral pattern S2. The first end 1311 and the second end 1312 of the first microstrip line 1314 serve as a first end and a second end of the third inductance L3, respectively. The first end 1313 and the second end 1312 of the second microstrip line 1315 serve as a first end and a second end of the fourth inductance L4, respectively. The second end 1312 of the first microstrip line 1314 and the second end 1312 of the second microstrip line 1315 are coupled together to form the common terminal 1312 of the third inductance L3 and the fourth inductance L4, and so that the first microstrip line 1314 and the second microstrip line 1315 form a combined microstrip line. The first terminal 1311 of the third inductor L3, the first terminal 1313 of the fourth inductor L4, the third inductor L3, and the second terminal 1312 of the fourth inductor L4 are respectively connected to the other parts of the amplifier through connection lines.

The merged microstrip line (first microstrip line/second microstrip line) of the embodiment of the present application may be formed of a single layer or multiple layers of metal materials. In one example, the merged microstrip line is composed of multiple layers of metallic material, where each layer of metallic material is located in a different wiring layer of the amplifier. And multiple layers of metal materials in different wiring layers are overlapped together to form a combined microstrip line, and the metal materials of the layers are connected through interlayer through holes. In another example, the merged microstrip line is composed of a single layer of metallic material, which may be located in the same or different wiring layers of the amplifier. For example, a portion of the single layer of metal material is located in one wiring layer and the other portion is located in a different one or more wiring layers. Similarly, the single-layer metal materials on different wiring layers are connected through the through holes.

In the example of fig. 7, both spiral patterns S1 and S2 comprise a plurality of turns, it being understood that they may also each comprise one turn, or one comprise a plurality of turns and the other a plurality of turns.

As an example, the first microstrip line 1314 and the second microstrip line 1315 may be wound in opposite directions such that the spiral directions of the first spiral pattern S1 and the second spiral pattern S2 are opposite, so that the directions of the induced magnetic fields caused by the currents in the microstrip lines forming the two spiral patterns S1 and S2 are opposite when the low-coupling inductance pair 131 is in an operating state. For example, one of S1 and S2 is made to have a counterclockwise spiral direction and the other is made to have a clockwise spiral direction. Here, a direction from the first terminal of the third inductor L3 or the fourth inductor L4 to the common terminal may be referred to as a spiral direction, or a direction from the common terminal to the first terminal of the third inductor L3 or the fourth inductor L4 may be referred to as a spiral direction.

In the embodiment of fig. 7, the first microstrip line 1314 is wound in a first spiral pattern S1 in a counterclockwise direction from the first end 1311 to the common end 1312 in an inside-out manner (first inside turn and then outside turn), and the second microstrip line 1315 is wound in a second spiral pattern S2 in a clockwise direction from the first end 1313 to the common end 1312 in a likewise inside-out manner (first inside turn and then outside turn) in a winding manner. It will be appreciated that one may be wound in an inside-out manner, the other in an outside-in manner (outer turns followed by inner turns), or both in an outside-in manner. It is understood that the microstrip line need not be wound in the inside-out or outside-in direction all the time when wound in the spiral pattern S1 or S2, but may be changed in direction one or more times. For example, first is from inside to outside, halfway is from outside to inside, or vice versa.

In summary, each of the spiral patterns S1 and S2 may wind the microstrip line from the respective first end to the common end in one of the following ways:

from the inside to the outside;

from outside to inside;

a combination of the above two.

In the embodiment of fig. 7, the two spiral patterns S1 and S2 do not overlap and are adjacent but at a distance D in a direction parallel to the wiring layers of the amplifier. In the embodiment of the present application, as described above, since mutual coupling between the two inductors is low, the two spiral patterns S1 and S2 may be arranged as close as possible (but there is no overlapping portion between the two), thereby reducing the circuit size and the cost. In one example, the pitch between the two spiral patterns S1 and S2 (distance D as shown in fig. 7) may be a minimum of about 3 microns. The "pitch between two spiral patterns" mentioned herein refers to a distance between microstrip lines of the two spiral patterns that are closest to each other. As shown in FIG. 7, distance D is the distance between adjacent outermost turns of S1 and S2. In practice, the minimum spacing between the two spiral patterns is determined by the chip manufacturing process.

In the example of fig. 7, the first microstrip line 1314 and the second microstrip line 1315 are equal in length. That is, the common terminal 1312 is located at the midpoint of the merged microstrip line. It will be appreciated that the common terminal 1312 may also be located not at the midpoint of the merged microstrip line, but at other locations, for example, closer to S1 or S2.

As shown in fig. 7, in this embodiment, the spiral patterns S1 and S2 are arranged in mirror images, and both are mirror images, which are shown in an axisymmetric arrangement in fig. 7. That is, the spiral patterns S1 and S2 have the same configuration, for example, the same number of turns, the microstrip line width, the pitch between adjacent turns, and the like, except that their patterns are opposite (winding manner is opposite), and are in a symmetrical/mirror relationship with respect to a plane perpendicular to the wiring layer located in the middle of the two. S1 and S2 may not be arranged in a mirror image, for example, S1 and S2 have different configurations, for example, S1 and S2 have different turns, microstrip line width or spacing between adjacent turns, etc., as long as the induced magnetic fields of the wound spiral patterns S1 and S2 are opposite in direction.

It is understood that the arrangement of the first spiral pattern S1 and the second spiral pattern S2 in fig. 7 may be interchanged.

In the low-coupling inductance pair 131 according to the above-mentioned embodiment of the present application, the microstrip lines of the two inductances have a common end and are arranged in two spiral patterns with opposite spiral directions, and when an excitation signal is applied to the low-coupling inductance pair 131 in an operating state, the excitation signal is shunted to the two spirals (microstrip lines of the two inductances) at the common end, so that the directions of the induced magnetic fields generated by the currents in the two spirals are opposite, thereby at least partially reducing the mutual coupling/inductance between the two inductances.

In the above-described inductance pair embodiment, as shown in fig. 7, the inductance pair is arranged in the integrated circuit chip to have three terminals: common terminal 1312, a head terminal 1311 as a first branch terminal of the inductor pair and a tail terminal 1313 as a second branch terminal of the inductor pair. As previously described, the three terminals of the pair may be connected to a stimulus signal or other circuit portion by leads. For example, a radio frequency excitation signal may be accessed from the common terminal 1312 of the pair of inductors, where the radio frequency excitation signal is shunted to the first microstrip line (first inductor) and the second microstrip line (second inductor). The radio frequency excitation signal is typically a periodically varying signal, for example a sinusoidal signal. Let the excitation signal switched in at the common terminal 1312 be i _com ＝I _com Sin ω t. The excitation signal is split into two branches at the common terminal 1312, one of which flows through the first spiral pattern S1 from the common terminal 1312 to the first branch terminal (head end) 1311, and the other of which flows through the second spiral pattern S2 from the common terminal 1312 to the second branch terminal (tail end) 1313. Let the excitation signal in the first spiral pattern S1 be i ₁ (t) the excitation signal in the first spiral pattern S1 is i ₂ (t), assuming no signal is reflected, i ₁ (t)+i ₂ (t)＝I _com Sin ω t. If the common terminal is located at the midpoint of the combined microstrip line and S1 and S2 are axisymmetric patterns, the excitation signals in S1 and S2 are identical at any time, i.e., the excitation signals are identical

Excitation signal i in inductive pairs ₁ (t) and i ₂ (t) is a periodically varying signal whose current level varies in a periodically non-uniform manner, and therefore the induced magnetic field generated is also periodically non-uniformUniformly changing; the changing magnetic field in turn generates an electric field, thereby generating an electromagnetic wave. When the excitation signals in S1 and S2 are identical, since the spiral directions of S1 and S2 are opposite, the magnitude of the induced magnetic field generated in S1 and the induced magnetic field generated in S2 are identical and the magnetic field direction is opposite at any time, and the directions of the induced electric fields are opposite and the directions are changed periodically. Therefore, the induced magnetic fields generated by S1 and S2 are almost completely cancelled in many regions and partially cancelled in some regions, so that the corresponding electric fields or electromagnetic waves caused by the induced magnetic fields are also cancelled, thereby reducing the loss of the inductive pair.

If the common end is not located at the middle point of the combined microstrip line, or S1 and S2 are patterns with different configurations, it may not be guaranteed that the excitation signals in S1 and S2 are completely the same, so the degree of mutual cancellation of the induced magnetic fields of S1 and S2 is reduced compared with the case that the excitation signals in S1 and S2 are completely the same, but the induced magnetic fields generated by S1 and S2 at any time are still partially mutually cancelled, and the electromagnetic radiation intensity is mutually weakened, thereby reducing the loss of the inductance pair to a certain extent.

It should be noted that, theoretically, an inductor pair having three ports (a common terminal, a leading end of the merged microstrip line as a first branch terminal, and a trailing end of the merged microstrip line as a second branch terminal) as described above is a passive lossless network, and since the passive network has reciprocity, the loss of the inductor pair and its transmission characteristic are reciprocal regardless of which of the three ports an excitation signal is input.

The low coupling inductance pair 131 formed by the third inductance L3 and the fourth inductance L4 in the amplifier may adopt the low coupling inductance pair arrangement as described above. The above description of the low-coupling inductance pairs applies to all low-coupling inductance pairs referred to herein, and for the sake of brevity, are not repeated herein elsewhere.

In the above-described embodiments of the amplifier, the above-described pair of low coupling inductors is used, which provides the following advantages for the amplifier of the present application: by configuring the two inductors constituting the inductor pair such that their respective induced magnetic fields are in opposite directions, the inductor pair is a low coupling inductor pair, and the loss of the amplifier input matching circuit can be reduced. In addition, the coupling between the two inductors forming the low-coupling inductor pair and the radiation ranges of the induction electric field and the induction magnetic field of the inductors can be reduced in this way, so that the inductors and other components are arranged closer to each other, and the circuit size is further reduced.

The embodiment of the present application further provides an electronic device, where the electronic device includes the radio frequency chip, and the radio frequency chip including the amplifier embodiment of the present application can be used in an electronic device.

As shown in fig. 8, the electronic device 1600 includes the rf chip 1500 shown in fig. 6. The electronic device 1600 may be a wireless device or any other electronic device that may use an amplifier.

A wireless device may be a User Equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a base station, etc. The wireless device may also be a cellular phone, a smart phone, a tablet, a wireless modem, a Personal Digital Assistant (PDA), a handheld device, a laptop, a smartbook, a netbook, a cordless phone, a Wireless Local Loop (WLL) station, a bluetooth device, etc. The wireless device may be capable of communicating with a wireless communication system, and may also be capable of receiving signals from a broadcast station, signals from one or more satellites, and the like. The wireless device may support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter wave, etc.).

The embodiment of the application provides an amplifier, a radio frequency chip and an electronic device, the amplifier includes: a field effect transistor; the first end of the drain electrode matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain electrode matching circuit is connected with the radio frequency signal output end; the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end; the grid biasing circuit is connected with the third end of the grid matching circuit; the source electrode matching circuit is connected with the source electrode of the field effect transistor; the grid matching circuit comprises a low coupling inductance pair, and the coupling inductance pair is an inductance pair with opposite induction magnetic field directions. In the embodiment of the application, the low coupling inductance pair is an inductance pair with opposite directions of the induction magnetic fields, the directions of the induction electric fields generated by the pair of inductances with opposite directions of the induction magnetic fields are also opposite, the induction electric fields with opposite directions can be partially offset, and the offset induction electric fields cannot generate radiation, so that the energy loss of the circuit is reduced. In addition, the physical distance of the inductors in the low-coupling inductor pair can be closer because the induced electric fields are partially offset, so that the size of the circuit can be reduced, and the cost is reduced. The radio frequency chip provided by the application comprises a substrate and the amplifier on the substrate. The radio frequency chip in the embodiment of the application has the advantages of low power consumption, low noise, small volume and low cost.

The amplifiers in the embodiments of the present application may be used independently, or may be used in a cascade of a plurality of stages, or may be applied to an integrated system, or may be applied to a multifunctional chip. The radio frequency chip of the embodiment of the present application may also include an independently used amplifier, or may include a plurality of amplifiers used in cascade, or may include a plurality of independently used amplifiers.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to requirements, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to corresponding processes in the context, and are not described herein again.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described or illustrated in detail in a certain embodiment, reference may be made to related descriptions in other embodiments.

The units or modules described as separate parts may or may not be physically separate, and parts displayed as units or modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of functional units. Some or all of the units or modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, each functional unit or module in the embodiments of the present application may be integrated into one chip unit, or each unit or module may exist alone physically, or two or more units or modules are integrated into one unit.

It is noted that, in this document, relational terms such as "first" and "second," and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An amplifier, characterized in that the amplifier comprises:

the field effect transistor comprises a drain electrode, a grid electrode and a source electrode, and is used for signal amplification;

2. The amplifier of claim 1, wherein the low coupling inductance pair comprises:

wherein the third inductor and the fourth inductor have opposite directions of induced magnetic fields.

3. The amplifier of claim 2, wherein the gate matching circuit further comprises:

4. The amplifier of claim 3, wherein the gate bias circuit comprises:

5. The amplifier of claim 4, wherein the source matching circuit comprises:

6. The amplifier of claim 4, wherein the source matching circuit is ground.

7. The amplifier of claim 3, wherein the gate bias circuit is ground.

8. The amplifier of claim 7, wherein the source matching circuit comprises:

a sixth inductive unit, wherein a first end of the sixth inductive unit is connected with the source electrode of the field effect transistor;

a fifth capacitor, a first end of the fifth capacitor being connected to the second end of the sixth inductive unit, and a second end of the fifth capacitor being grounded;

a first end of the first resistor is connected to the second end of the sixth inductive unit, and a second end of the first resistor is grounded;

9. The amplifier of claim 4, wherein the source matching circuit comprises:

10. The amplifier of claim 1, wherein the drain matching circuit comprises:

the second end of the second inductive unit is connected with the second end of the first inductive unit, and the second end of the second inductive unit is connected with the drain electrode bias power supply end;

the first inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line, and/or the second inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.

11. The amplifier of claim 2, wherein the third and fourth inductors are both spiral inductors and are arranged in the amplifier with opposite spiral directions.

12. The amplifier of claim 2, wherein the third and fourth inductors are arranged in the amplifier as mirror image arrangements of each other.

13. The amplifier of claim 2, wherein the third inductor is formed of a first microstrip line wound in a first spiral pattern, and the fourth inductor is formed of a second microstrip line wound in a second spiral pattern, wherein the first end and the second end of the first microstrip line are respectively used as the first end and the second end of the third inductor, the first end and the second end of the second microstrip line are respectively used as the first end and the second end of the fourth inductor, and the second end of the first microstrip line and the second end of the second microstrip line are connected together such that the first microstrip line and the second microstrip line form a merged microstrip line.

14. The amplifier of claim 13, wherein the first and second spiral patterns do not overlap and are adjacent but at a distance in a direction parallel to a routing layer of the amplifier.

15. The amplifier of claim 13, wherein the merged microstrip is comprised of multiple layers of metallic material, wherein each layer of metallic material is located in a different wiring level of the amplifier.

16. The amplifier of claim 13, wherein the merged microstrip is comprised of a single layer of metallic material, wherein the single layer of metallic material is located in the same or different wiring layers of the amplifier.

17. A radio frequency chip comprising a substrate, and the amplifier of any one of claims 1 to 16 on the substrate.

18. An electronic device comprising the radio-frequency chip according to claim 17.