CN116938153A - Amplifier, radio frequency chip and electronic device - Google Patents
Amplifier, radio frequency chip and electronic device Download PDFInfo
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- CN116938153A CN116938153A CN202210349333.XA CN202210349333A CN116938153A CN 116938153 A CN116938153 A CN 116938153A CN 202210349333 A CN202210349333 A CN 202210349333A CN 116938153 A CN116938153 A CN 116938153A
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- 230000005669 field effect Effects 0.000 claims abstract description 59
- 238000010168 coupling process Methods 0.000 claims abstract description 57
- 238000005859 coupling reaction Methods 0.000 claims abstract description 57
- 230000006698 induction Effects 0.000 claims abstract description 40
- 230000008878 coupling Effects 0.000 claims abstract description 28
- 230000003321 amplification Effects 0.000 claims abstract description 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 5
- 230000001939 inductive effect Effects 0.000 claims description 66
- 239000003990 capacitor Substances 0.000 claims description 54
- 239000010410 layer Substances 0.000 claims description 20
- 239000007769 metal material Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 12
- 239000002356 single layer Substances 0.000 claims description 8
- 230000005684 electric field Effects 0.000 description 34
- 230000005284 excitation Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 238000004891 communication Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 230000005855 radiation Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000005670 electromagnetic radiation Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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Abstract
The embodiment of the application discloses an amplifier, a radio frequency chip and an electronic device. The amplifier includes: the field effect transistor comprises a drain electrode, a grid electrode and a source electrode, and is used for signal amplification; the first end of the drain matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain matching circuit is connected with the radio frequency signal output end; the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end; the grid bias circuit is connected with the third end of the grid matching circuit; the source electrode matching circuit is connected with the source electrode of the field effect transistor; the grid matching circuit comprises a low-coupling inductance pair, wherein the coupling inductance pair is an inductance pair with opposite induction magnetic field directions. The embodiment of the application has the advantages of small power consumption, small size, low cost and low noise.
Description
Technical Field
The present application relates to the field of electronic technology, and in particular, to an amplifier, a radio frequency chip, and an electronic device.
Background
With the development of communication technology, particularly the emergence of 5G technology, high-frequency wireless communication technology is an important development direction of wireless communication.
The transceiver system for high-frequency wireless communication comprises a large number of amplifiers, and the performance of the amplifiers can have important influence on the performance of the radio frequency transceiver system. Therefore, the high frequency wireless communication technology puts higher demands on the performance and cost of the amplifier, such as integration level, noise performance, power consumption, etc.
The existing radio frequency or high frequency amplifier chip is mostly formed by elements such as transistors, concentrated parameter element inductances, concentrated parameter element capacitances, resistances, microstrip lines and the like. In the element, inductance, microstrip line, capacitance and the like can generate electromagnetic radiation and other induced magnetic fields or electric fields and the like due to signal excitation, and the physical fields can influence the arrangement and normal operation of other elements. In the design or manufacture of an amplifier, in order to solve the problem of electromagnetic compatibility between elements, an existing method is to implement electromagnetic compatibility by maintaining a large arrangement pitch of elements, which results in a large size of the amplifier, which is inconvenient for high density integration, and inconvenient for cost reduction. In addition, electromagnetic radiation, induced magnetic or electric fields can cause energy losses, sacrificing the performance of the amplifier. In order to realize popularization of high-frequency wireless communication technology, reducing the cost of components and improving the performance of the components are urgent problems to be solved.
Disclosure of Invention
In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides an amplifier, a radio frequency chip and an electronic device.
In a first aspect, the present application provides an amplifier comprising:
the field effect transistor comprises a drain electrode, a grid electrode and a source electrode, and is used for signal amplification;
the first end of the drain matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain matching circuit is connected with the radio frequency signal output end;
the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end;
the grid bias circuit is connected with the third end of the grid matching circuit;
the source electrode matching circuit is connected with the source electrode of the field effect transistor;
the grid matching circuit comprises a low-coupling inductance pair, wherein the coupling inductance pair is an inductance pair with opposite induction magnetic field directions.
In an embodiment of the present application, the low coupling inductance pair includes:
the second end of the third inductor is connected with the grid electrode of the field effect transistor;
A fourth inductor, wherein a first end of the fourth inductor is connected with a first end of the third inductor, and a second end of the fourth inductor is connected with the grid bias circuit;
and the induction magnetic fields of the third inductor and the fourth inductor are opposite in direction.
In an embodiment of the present application, the gate matching circuit further includes:
and the first end of the third capacitor is connected with the radio frequency signal input end, and the second end of the third capacitor is connected with the first end of the third inductor.
In an embodiment of the present application, the gate bias circuit includes:
and the first end of the fourth capacitor is grounded, and the second end of the fourth capacitor is connected with the grid bias power supply end.
In an embodiment of the present application, the source matching circuit includes:
the first end of the fifth inductive unit is connected with the source electrode of the field effect transistor, and the second end of the fifth inductive unit is grounded;
the fifth inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.
In the embodiment of the application, the source matching circuit is ground.
In the embodiment of the application, the grid bias circuit is ground.
In an embodiment of the present application, the source matching circuit includes:
the first end of the sixth inductive unit is connected with the source electrode of the field effect transistor;
a fifth capacitor, wherein a first end of the fifth capacitor is connected with a second end of the sixth inductive unit, and a second end of the fifth capacitor is grounded;
the first end of the first resistor is connected with the second end of the sixth inductive unit, and the second end of the first resistor is grounded;
the sixth inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.
In an embodiment of the present application, the source matching circuit includes:
the first end of the seventh inductive unit is connected with the source electrode of the field effect transistor;
a sixth capacitor, wherein a first end of the sixth capacitor is connected to the second end of the seventh inductive unit, the first end of the sixth capacitor is further connected to the source bias power supply end, and a second end of the sixth capacitor is grounded;
the seventh inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.
In an embodiment of the present application, the drain matching circuit includes:
The first end of the first inductive unit is connected with the drain electrode of the field effect transistor;
the second end of the second inductive unit is connected with the second end of the first inductive unit, and the second end of the second inductive unit is connected with the drain bias power supply end;
the first end of the first capacitor is connected with the second end of the first inductive unit, and the second end of the first capacitor is connected with the radio frequency signal output end;
the first end of the second capacitor is connected with the second end of the second inductive unit, and the second end of the second capacitor is grounded;
the first inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line, and/or the second inductive unit is one of the inductor, the microstrip line or the combination of the inductor and the microstrip line.
In an embodiment of the application, the third inductance and the fourth inductance are both spiral inductances and are arranged in opposite spiral directions in the amplifier.
In an embodiment of the application, the third inductance and the fourth inductance are arranged in the amplifier as mirror images of each other.
In the embodiment of the application, the third inductor is formed by a first microstrip line, the first microstrip line is wound into a first spiral pattern, the fourth inductor is formed by a second microstrip line, the second microstrip line is wound into a second spiral pattern, the first end and the second end of the first microstrip line are respectively used as the first end and the second end of the third inductor, the first end and the second end of the second microstrip line are respectively used as the first end and the second end of the fourth inductor, and the second end of the first microstrip line and the second end of the second microstrip line are connected together so that the first microstrip line and the second microstrip line form a combined microstrip line.
In an embodiment of the application, the first and second spiral patterns do not overlap and are adjacent but at a distance in a direction parallel to the wiring layer of the amplifier.
In an embodiment of the present application, the combined microstrip line is formed of multiple layers of metal materials, where each layer of metal material is located in a different wiring layer of the amplifier.
In an embodiment of the present application, the combined microstrip line is formed of a single layer of metal material, wherein the single layer of metal material is located in the same or different wiring layers of the amplifier.
In a second aspect, there is provided a radio frequency chip comprising a substrate, and an amplifier as described above on the substrate.
In a third aspect, an electronic device is provided, comprising a radio frequency chip as described above.
An embodiment of the present application provides an amplifier including: the field effect transistor comprises a drain electrode, a grid electrode and a source electrode, and is used for signal amplification; the first end of the drain matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain matching circuit is connected with the radio frequency signal output end; the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end; the grid bias circuit is connected with the third end of the grid matching circuit; the source electrode matching circuit is connected with the source electrode of the field effect transistor; the grid matching circuit comprises a low-coupling inductance pair, wherein the coupling inductance pair is an inductance pair with opposite induction magnetic field directions. In the embodiment of the application, the low-coupling inductance pair is an inductance pair with opposite induction magnetic field directions, the induction electric fields generated by a pair of inductances with opposite induction magnetic fields are opposite in directions, and the induction electric fields with opposite directions can be partially counteracted, so that the radiation generated by the induction electric fields is reduced, and the energy loss of the circuit is reduced. In addition, the physical distance of the inductors in the low-coupling inductor pair can be closer because the induction electric fields cancel each other, so that the size of the amplifier can be reduced, the cost can be reduced, and the noise can be reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic circuit diagram of an amplifier in an embodiment of the application;
FIG. 2 is a schematic circuit diagram of an amplifier in an embodiment of the application;
FIG. 3 is a schematic circuit diagram of an amplifier in an embodiment of the application;
FIG. 4 is a schematic circuit diagram of an amplifier in an embodiment of the application;
FIG. 5 is a schematic circuit diagram of an amplifier in an embodiment of the application;
FIG. 6 is a schematic diagram of a radio frequency chip according to an embodiment of the present application;
FIG. 7 is a schematic diagram of the placement of low coupling inductance pairs in an amplifier in an embodiment of the application;
fig. 8 is a schematic diagram of an electronic device according to an embodiment of the application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The amplifier provided by the embodiment of the application can be applied as an independent component or can be applied to radio frequency chips or system integration.
As shown in fig. 1, an embodiment of the present application provides an amplifier including:
a field effect transistor 110 including an enhancement mode field effect transistor and a depletion mode field effect transistor, the field effect transistor 110 including a drain, a gate and a source, the field effect transistor 110 being for signal amplification;
the first end of the drain matching circuit 120 is connected with the drain of the field effect transistor 110, and the second end of the drain matching circuit 120 is connected with the radio frequency signal output end RFOUT;
The first end of the gate matching circuit 130 is connected with the gate of the field effect transistor 110, and the second end of the gate matching circuit 130 is connected with the radio frequency signal input end RFIN;
the source matching circuit 140 is connected with the source of the field effect transistor 110;
a gate bias circuit 150, the gate bias circuit 150 being connected to the third terminal of the gate matching circuit 130;
the gate matching circuit 130 includes a low-coupling inductance pair 131, where the low-coupling inductance pair 131 is an inductance pair with opposite induced magnetic field directions.
In the field effect transistor 110 of the embodiment of the present application, the three poles are a Source (S pole), a Gate (G pole) and a Drain (Drain, D pole) respectively, which are used for amplifying the radio frequency signal, and are not described herein.
In the embodiment of the present application, the drain matching circuit 120 is configured to match the drain output impedance of the field effect transistor 110 to a first target impedance, where the first target impedance is the output impedance of the rf signal output terminal RFOUT of the amplifier.
In the embodiment of the present application, the gate matching circuit 130 is configured to match the gate input impedance of the fet 110 to a second target impedance, where the second target impedance is the input impedance of the rf signal input terminal RFIN of the amplifier.
In the embodiment of the present application, as shown in fig. 1 and 2, the low-coupling inductance pair 131 includes:
a third inductor L3, wherein a second end of the third inductor L3 is connected to the gate of the field effect transistor 110;
a fourth inductor L4, wherein a first end of the fourth inductor L4 is connected to the first end of the third inductor L3, and a second end of the fourth inductor L4 is connected to the gate bias circuit 150;
wherein, the induction magnetic fields of the third inductor L3 and the fourth inductor L4 are opposite in direction.
In the embodiment of the present application, the third inductor L3 and the fourth inductor L4 may be planar spiral inductors, and the spiral direction of the third inductor L3 is opposite to the spiral direction of the fourth inductor L4.
In other embodiments of the present application, the third inductor L3 and the fourth inductor L4 may be other structures and physical layouts capable of implementing the opposite direction of the induced magnetic field, which are not described herein.
When the inductor is excited by a signal, an induced magnetic field is generated, an induced electric field is generated by the induced magnetic field, and radiation is generated by the induced electric field, so that energy loss is generated; therefore, the third inductor L3 and the fourth inductor L4 also have induced magnetic fields, and the induced electric field generated by the induced magnetic fields generates energy loss.
In the embodiment of the application, the directions of the induction magnetic fields of the third inductor L3 and the fourth inductor L4 are opposite, so that the direction of the induction electric field generated by the induction magnetic field of the third inductor L3 and the direction of the induction electric field generated by the induction magnetic field of the fourth inductor L4 are opposite, and the two opposite induction electric fields can be partially offset, so that the radiation generated by the induction electric fields is reduced, and the energy loss is reduced.
Since the induced electric field between the third inductor L3 and the fourth inductor L4 is partially cancelled, the physical distance between the third inductor L3 and the fourth inductor L4 can be closer, so that the size of the circuit can be reduced and the cost can be reduced.
In the embodiment of the present application, the gate matching circuit 130 includes a low-coupling inductance pair 131, where the low-coupling inductance pair 131 is a pair of inductances L3 and L4 with opposite directions of the induced magnetic field, so that mutual coupling can be reduced, and energy loss can be reduced. In addition, the physical distance between the third inductor L3 and the fourth inductor L4 can be closer, so that the size of the circuit can be reduced, and the cost can be reduced.
In an embodiment of the present application, as shown in fig. 2, the gate matching circuit 130 further includes:
and a first end of the third capacitor C3 is connected with the radio frequency signal input end RFIN, and a second end of the third capacitor C3 is connected with the first end of the third inductor L3.
The gate bias circuit 150 includes:
and the first end of the fourth capacitor C4 is grounded, and the second end of the fourth capacitor C4 is connected with the grid bias power supply end VG.
In the embodiment of the present application, the third capacitor C3, the fourth capacitor C4 and the low coupling inductance pair 131 form an amplifier input matching network for matching the gate input impedance of the fet 110 to the second target impedance.
In the embodiment of the application, the resonance point frequency of the fourth capacitor C4 is close to or the same as the center frequency of the working frequency band of the amplifier, so as to isolate the radio frequency signal of the amplifier from the gate bias power supply end VG, and simultaneously provide the second end of the fourth inductor L4 with the radio frequency signal ground.
In an embodiment of the present application, as shown in fig. 2, the source matching circuit 140 includes:
a fifth inductive unit L5, wherein a first end of the fifth inductive unit L5 is connected to the source of the field effect transistor 110, and a second end of the fifth inductive unit L5 is grounded;
the fifth inductive unit L5 is one of an inductance, a microstrip line, or a combination of the inductance and the microstrip line.
In the embodiment of the present application, by adjusting the parameter of the fifth inductive unit L5, the optimal noise impedance of the fet 110 and the optimal gain matching impedance of the fet 110 tend to be consistent, thereby reducing the noise of the amplifier and improving the performance of the amplifier.
In the embodiment of the present application shown in fig. 2, the gate bias voltage VG is provided to the fet 110 through the gate bias power terminal VG, and the drain bias voltage VD is provided to the fet 110 through the drain bias power terminal VD, so as to maintain the normal operation of the fet 110. The radio frequency signal is input through the radio frequency signal input end RFIN, passes through the grid matching circuit 130, drives the grid of the field effect tube 110, and is output through the drain matching circuit 120 and the radio frequency signal output end RFOUT after being amplified by the field effect tube 110.
In the embodiment of the present application, the low-coupling inductance pair 131 is an inductance pair with opposite induced magnetic field directions, so that energy loss in the corresponding gate matching circuit 130 can be reduced, circuit volume is reduced, and cost is reduced. In addition, in the embodiment of the application, the low coupling inductance pair 131 is adopted, so that the area is reduced, and the noise of the amplifier is reduced.
In the embodiment of the present application, as shown in fig. 3, the source matching circuit 140 is ground.
In a specific application scenario of the embodiment of the present application, in the source matching circuit 140, the source matching circuit 140 is ground, that is, the source of the fet 110 may be directly grounded, as shown in fig. 3.
In the embodiment of the present application shown in fig. 3, the gate bias voltage VG is provided to the fet 110 through the gate bias power terminal VG, and the drain bias voltage VD is provided to the fet 110 through the drain bias power terminal VD, so as to maintain the normal operation of the fet 110. The radio frequency signal is input through the radio frequency signal input end RFIN, passes through the grid matching circuit 130, drives the grid of the field effect tube 110, and is output through the drain matching circuit 120 and the radio frequency signal output end RFOUT after being amplified by the field effect tube 110.
In the embodiment of the present application, the low-coupling inductance pair 131 is an inductance pair with opposite induced magnetic field directions, so that energy loss in the corresponding gate matching circuit 130 can be reduced, circuit volume is reduced, and cost is reduced.
In the embodiments of the present application shown in fig. 2 and 3, the gate bias voltage VG needs to be provided, and in the embodiment of the present application shown in fig. 4, a single power self-bias amplifier is possible, so that the gate bias voltage VG does not need to be provided.
As shown in fig. 4, in the embodiment of the present application, the gate bias circuit 150 is ground.
As shown in fig. 4, in the embodiment of the present application, the source matching circuit 140 includes:
a sixth inductive unit L6, wherein a first end of the sixth inductive unit L6 is connected to the source of the fet 110;
a fifth capacitor C5, wherein a first end of the fifth capacitor C5 is connected to a second end of the sixth inductive unit L6, and a second end of the fifth capacitor C5 is grounded;
a first resistor R1, wherein a first end of the first resistor R1 is connected to a second end of the sixth inductive unit L6, and a second end of the first resistor R1 is grounded;
the sixth inductive unit L6 is one of an inductance, a microstrip line, or a combination of the inductance and the microstrip line.
In the embodiment of the present application, by adjusting the parameter of the sixth inductive unit L6, the optimal noise impedance of the fet 110 and the optimal gain matching impedance of the fet 110 tend to be consistent, thereby reducing the noise of the amplifier and improving the performance of the amplifier.
In the embodiment of the present application, the fifth capacitor C5 couples the rf signal output by the source of the fet 110 and passing through the sixth inductive unit L6 to ground, so as to reduce the energy loss of the source matching circuit 140.
In the embodiment of the present application, the first resistor R1 is used to raise the source potential of the fet 110, so that the voltage from the gate to the source of the fet 110 is negative, and the normal operation of the amplifier is maintained.
In the embodiment shown in fig. 4, the drain bias voltage VD is provided to the fet 110 through the drain bias power terminal VD, and at this time, the drain-source current of the fet 110 flows through the resistor R1 in the source matching circuit 140, so as to increase the source potential of the fet 110, and make the gate-source voltage of the fet 110 negative, so as to maintain the normal operation of the fet 110. The radio frequency signal is input through the radio frequency signal input end RFIN, passes through the grid matching circuit 130, drives the grid of the field effect tube 110, and is output through the drain matching circuit 120 and the radio frequency signal output end RFOUT after being amplified by the field effect tube 110.
In the embodiment of the present application, the gate matching circuit 130 includes a low-coupling inductance pair 131, where the low-coupling inductance pair 131 is an inductance pair with opposite induced magnetic field directions, so that energy loss in the corresponding gate matching circuit 130 can be reduced, circuit volume can be reduced, cost can be reduced, and noise can be reduced.
In an embodiment of the present application, an implementation of an amplifier is further provided, as shown in fig. 5.
The gate bias circuit 150 is connected to the gate bias power supply terminal VG, i.e., the second terminal of the capacitor C4 is connected to the gate bias power supply terminal VG.
As shown in fig. 5, at this time, the source matching circuit 140 includes:
a seventh inductive unit L7, wherein a first end of the seventh inductive unit L7 is connected to the source of the fet 110;
a sixth capacitor C6, where a first end of the sixth capacitor C6 is connected to the second end of the seventh inductive unit L7, the first end of the sixth capacitor C6 is further connected to the source bias power supply end VS, and a second end of the sixth capacitor C6 is grounded;
the seventh inductive unit L7 is one of an inductance, a microstrip line, or a combination of an inductance and a microstrip line.
In the embodiment of the present application, by adjusting the parameter of the seventh inductive unit L7, the optimal noise impedance of the fet 110 and the optimal gain matching impedance of the fet 110 can be adjusted to be consistent, thereby reducing the noise of the amplifier and improving the performance of the amplifier.
In the embodiment of the present application, the frequency of the resonance point of the sixth capacitor C6 is close to or the same as the center frequency of the working frequency band of the amplifier, so as to isolate the rf signal between the amplifier and the source bias power supply terminal VS, and simultaneously provide the rf signal ground for the second terminal of the seventh inductive unit L7.
In the embodiment shown in fig. 5 of the present application, a gate bias voltage VG is provided to the amplifier through a gate bias power supply terminal VG, a drain bias voltage VD is provided to the amplifier through a drain bias power supply terminal VD, a source bias voltage VS is provided to the amplifier through a source bias power supply terminal VS, a voltage difference between VG and VS is adjusted to be a gate-source bias power supply in a normal operation state of the field effect transistor 110, and a voltage difference between VD and VS is adjusted to be a drain-source bias power supply in a normal operation state of the field effect transistor 110, so that the field effect transistor 110 is in a normal operation state. The radio frequency signal is input through the radio frequency signal input end RFIN, passes through the grid matching circuit 130, drives the grid of the field effect tube 110 in the amplifier, and passes through the drain matching circuit 120 after being amplified by the field effect tube 110, and is output by the radio frequency signal output end RFOUT.
In the embodiment of the present application, the gate matching circuit 130 includes a low-coupling inductance pair 131, where the low-coupling inductance pair 131 is an inductance pair with opposite induced magnetic field directions, so that energy loss in the corresponding gate matching circuit 130 can be reduced, circuit volume can be reduced, cost can be reduced, and noise can be reduced.
As shown in fig. 2 to 5, the drain matching circuit 120 includes:
a first inductive unit L1, wherein a first end of the first inductive unit L1 is connected to a drain of the field effect transistor 110;
The second end of the second inductive unit L2 is connected with the second end of the first inductive unit L1, and the second end of the second inductive unit L2 is connected with the drain bias power supply end VD;
a first capacitor C1, where a first end of the first capacitor C1 is connected to a second end of the first inductive unit L1, and a second end of the first capacitor C1 is connected to the radio frequency signal output terminal RFOUT;
a second capacitor C2, wherein a first end of the second capacitor C2 is connected to a second end of the second inductive unit L2, and a second end of the second capacitor C2 is grounded;
the first inductive unit L1 is one of an inductance, a microstrip line, or a combination of an inductance and a microstrip line, and/or the second inductive unit L2 is one of an inductance, a microstrip line, or a combination of an inductance and a microstrip line.
In the embodiment of the present application, the frequency of the resonance point of the second capacitor C2 is close to or the same as the center frequency of the working frequency band of the amplifier, so as to isolate the rf signal of the amplifier from the drain bias power supply terminal VD, and simultaneously provide the rf signal ground for the second terminal of the second inductive unit L2.
In the embodiment of the application, the power supply bias mode of the amplifier comprises single power supply self-bias, double power supply bias and three power supply bias, wherein the single power supply self-bias refers to that only a drain bias power supply VD is provided by the outside, as shown in fig. 4; the dual power bias refers to the provision of a drain bias power VD and a gate bias power VG from the outside, as shown in fig. 2 and 3; the three-power bias means that the pole bias power VD, the gate bias power VG, and the source bias power VS are supplied from the outside as shown in fig. 5. The single power supply self-bias power supply is simple, the double power supply bias can exert better power performance, the three power supply bias is beneficial to energy conservation, and the power supply bias mode can be configured according to practical application. The power supply bias mode of the embodiment of the application can also be used in other circuits, and is not repeated here.
In some application scenarios, the sixth inductive unit L6 and the seventh inductive unit L7 may be omitted from the embodiments shown in fig. 4 and fig. 5, and do not affect the operation and function of the amplifier according to the embodiments of the present application.
The embodiment of the application also provides a radio frequency chip, which comprises a substrate and the amplifier on the substrate.
As shown in fig. 1, the amplifier includes:
a field effect transistor 110;
the first end of the drain matching circuit 120 is connected with the drain of the field effect transistor 110, and the second end of the drain matching circuit 120 is connected with the radio frequency signal output end RFOUT;
the first end of the gate matching circuit 130 is connected with the gate of the field effect transistor 110, and the second end of the gate matching circuit 130 is connected with the radio frequency signal input end RFIN;
a gate bias circuit 150, the gate bias circuit 150 being connected to the third terminal of the gate matching circuit 130;
the source matching circuit 140 is connected with the source of the field effect transistor 110;
the gate matching circuit 130 includes a low-coupling inductance pair 131, where the coupling inductance pair 131 is an inductance pair with opposite induced magnetic field directions.
In the embodiment of the present application, as shown in fig. 1 and 2, the low-coupling inductance pair 131 includes:
a third inductor L3, wherein a second end of the third inductor L3 is connected to the gate of the field effect transistor 110;
a fourth inductor L4, wherein a first end of the fourth inductor L4 is connected to the first end of the third inductor L3, and a second end of the fourth inductor L4 is connected to the gate bias circuit 150;
wherein, the induction magnetic fields of the third inductor L3 and the fourth inductor L4 are opposite in direction.
In the embodiment of the present application, the third inductor L3 and the fourth inductor L4 may be planar spiral inductors, and the spiral direction of the third inductor L3 is opposite to the spiral direction of the fourth inductor L4.
In other embodiments of the present application, the third inductor L3 and the fourth inductor L4 may be other structures and physical layouts capable of implementing the opposite direction of the induced magnetic field, which are not described herein.
When the inductor is excited by a signal, an induced magnetic field is generated, an induced electric field is generated by the induced magnetic field, and an induced eddy current is generated in the substrate of the chip by the induced electric field, so that energy loss is generated; therefore, the inductor L3 and the inductor L4 also have induced magnetic fields, and an induced electric field generated by the induced magnetic fields generates induced eddy currents in the substrate of the chip, thereby generating energy loss.
In the embodiment of the application, the directions of the induction magnetic fields of the third inductor L3 and the fourth inductor L4 are opposite, so that the directions of the induction electric field generated by the induction magnetic field of the third inductor L3 and the induction electric field generated by the induction magnetic field of the fourth inductor L4 are also opposite, the directions of induction eddy currents respectively generated by the two opposite induction electric fields are opposite, the induction eddy currents with opposite directions can be partially counteracted, the induction eddy currents are reduced, the generated energy loss is reduced, and the energy loss of a chip matching network is reduced.
Since the induced eddy currents generated on the substrate by the third inductor L3 and the fourth inductor L4 are partially cancelled, the physical distance between the third inductor L3 and the fourth inductor L4 can be closer, so that the size of the circuit can be reduced and the cost can be reduced.
In the embodiment of the application, in the gate matching circuit 130 of the amplifying circuit in the chip, the directions of the induced magnetic fields of the third inductor L3 and the fourth inductor L4 are opposite, so that the induced eddy current in the substrate can be partially counteracted, and the energy loss is reduced. In addition, the physical distance between the third inductor L3 and the fourth inductor L4 can be closer, so that the size of the chip can be reduced, and the cost can be reduced.
The specific implementation of the amplifier in the chip according to the embodiment of the present application is described with reference to the above embodiment and fig. 1 to 5, and will not be described herein.
Therefore, the radio frequency chip in the embodiment of the application has low power consumption, low noise, small volume and lower cost.
As shown in fig. 6, the radio frequency chip 1500 may include an amplifier 1501, wherein the amplifier 1501 may be any embodiment of an amplifier as described above. One amplifier 1501 may be used alone, or a plurality of amplifiers 1501 may be used in combination. In an example, the radio frequency chip 1500 may include one or more amplifiers 1501.
In embodiments of amplifiers and radio frequency chips employing low coupling inductance pairs, the layout of the low coupling inductance pairs greatly affects the size of the circuit dimensions. When the inductor is excited by a signal, an induced magnetic field is generated, an induced electric field is generated by the induced magnetic field, and radiation is generated by the induced electric field, so that energy loss is generated. For example, an induced electric field may generate eddy currents in a circuit medium and electromagnetic radiation in space. This loss is exacerbated if two inductors are placed in close proximity, which can create mutual coupling between them. According to the embodiment of the application, the mutual coupling between the two inductors is at least partially reduced by configuring the two inductors of the low-coupling inductor pair to have opposite directions of the generated induced magnetic fields, so that the directions of the induced electric fields caused by the induced magnetic fields of the two inductors are also opposite, and the induced electric fields are partially or completely counteracted, thereby reducing or eliminating the energy loss caused by the induced electric fields, and further reducing the chip area occupied by the amplifier by arranging the two inductors of the low-coupling inductor pair to be closer.
For example, the third inductor L3 and the fourth inductor L4 of the low-coupling inductor pair 131 may be disposed to be adjacent to each other such that the direction of the induced magnetic field generated by the third inductor L3 is opposite to the direction of the induced magnetic field generated by the fourth inductor L4.
In one example, the third inductance L3 and the fourth inductance L4 are spiral inductances, which may be arranged in the amplifier with the spiral directions being opposite. For example, the spiral direction of one inductor is clockwise and the other is counter-clockwise.
In one example, the third inductance L3 and the fourth inductance L4 are arranged as mirror images of each other in the amplifier.
Fig. 7 shows a schematic diagram of the arrangement of low coupling inductance pairs in an amplifier according to an embodiment of the application. Fig. 7 is a schematic diagram of a low coupling inductance pair of an amplifier looking down from a direction perpendicular to the wiring layers of the amplifier. In one example, the amplifier may be a radio frequency chip.
As shown in fig. 7, the low-coupling inductance pair 131 includes two inductances, which are respectively composed of a first microstrip line 1314 and a second microstrip line 1315, and the first microstrip line 1314 is wound into a first spiral pattern S1 and the second microstrip line 1315 is wound into a second spiral pattern S2. The first end 1311 and the second end 1312 of the first microstrip line 1314 serve as the first end and the second end of the third inductance L3, respectively. The first end 1313 and the second end 1312 of the second microstrip line 1315 are respectively the first end and the second end of the fourth inductance L4. The second end 1312 of the first microstrip line 1314 and the second end 1312 of the second microstrip line 1315 are connected together to form a common end 1312 of the third inductance L3 and the fourth inductance L4, and the first microstrip line 1314 and the second microstrip line 1315 form a combined microstrip line. The first end 1311 of the third inductor L3, the first end 1313 of the fourth inductor L4, the third inductor L3 and the second end 1312 of the fourth inductor L4 are connected to the other parts of the amplifier by connecting wires, respectively.
The combined microstrip line (first microstrip line/second microstrip line) of the embodiment of the present application may be composed of a single layer or multiple layers of metal materials. In one example, the merged microstrip line is composed of multiple layers of metallic materials, with each layer of metallic material being located in a different wiring layer of the amplifier. And multiple layers of metal materials positioned in different wiring layers are overlapped together to form a combined microstrip line, and the metal materials of the layers are connected through interlayer through holes. In another example, the combined microstrip line is composed of a single layer of metal material, which may be located in the same or different wiring layers of the amplifier. For example, a portion of the single layer of metal material is located in one wiring layer and the other portion is located in a different wiring layer or layers. Likewise, the single layers of metal material located in the different wiring layers are connected by vias.
In the example of fig. 7, both spiral patterns S1 and S2 comprise a plurality of turns, it being understood that they may also each comprise one turn, or one comprising a plurality of turns and the other comprising a plurality of turns.
As an example, the first microstrip line 1314 and the second microstrip line 1315 may be wound in opposite directions such that the spiral directions of the first spiral pattern S1 and the second spiral pattern S2 are opposite, so that the directions of induced magnetic fields caused by currents in the microstrip lines forming the two spiral patterns S1 and S2 are opposite when the low coupling inductance pair 131 is in an operating state. For example, one of S1 and S2 is made to spiral counterclockwise and the other is made to spiral clockwise. The direction from the first end of the third inductor L3 or the fourth inductor L4 to the common end may be referred to herein as a spiral direction, or the direction from the common end to the first end of the third inductor L3 or the fourth inductor L4 may also be referred to as a spiral direction.
In the embodiment of fig. 7, the first microstrip line 1314 is wound in a first spiral pattern S1 in a counter-clockwise direction from the first end 1311 to the common end 1312 in an inside-out manner (turns inside then outside), and the second microstrip line 1315 is wound in a second spiral pattern S2 in a clockwise direction from the first end 1313 to the common end 1312 in an inside-out manner (turns inside then outside). It will be appreciated that both may also be wound one inside-out, the other outside-in (outside-in turns then inside turns), or both. It will be appreciated that the microstrip line need not always be wound in an inside-out or outside-in direction when wound into a spiral pattern S1 or S2, but may be redirected one or more times. For example, it is first from inside to outside, and halfway from outside to inside, or vice versa.
In summary, each of the spiral patterns S1 and S2 may wind the microstrip line from the respective first end to the common end in one of the following manners:
from inside to outside;
from outside to inside;
a combination of the two.
In the embodiment of fig. 7, the two spiral patterns S1 and S2 do not overlap and are adjacent but at a distance D in a direction parallel to the wiring layer of the amplifier. In the embodiment of the present application, since the mutual coupling between the two inductors is low as described above, the two spiral patterns S1 and S2 can be arranged as close as possible (but without overlapping portions), thereby reducing the circuit size and the cost. In one example, the spacing between the two spiral patterns S1 and S2 (distance D as shown in fig. 7) may be at least about 3 microns. The "distance between two spiral patterns" as referred to herein refers to the distance between the microstrip lines of the two spiral patterns closest to each other. As shown in fig. 7, the distance D is the distance between adjacent outermost turns of S1 and S2. In practice, the minimum spacing between the two spiral patterns is determined by the chip manufacturing process.
In the example of fig. 7, the first microstrip line 1314 is equal in length to the second microstrip line 1315. That is, the common terminal 1312 is located at the midpoint of the combined microstrip line. It will be appreciated that the common terminal 1312 may be located at other locations, such as closer to S1 or S2, than at the midpoint of the combined microstrip line.
In this embodiment, the spiral patterns S1 and S2 are mirror images, as shown in fig. 7, and both are mirror images, which are shown as axisymmetric in fig. 7. I.e. the spiral patterns S1 and S2 have the same configuration, e.g. the same number of turns, microstrip line linewidths, spacing between adjacent turns, etc., except that their patterns are reversed (winding wise reversed), both in a symmetrical/mirrored relationship with respect to a plane perpendicular to the wiring layer in between. S1 and S2 may not be arranged in mirror image, for example, S1 and S2 may have different configurations, for example, S1 and S2 may have different numbers of turns, microstrip line widths, or pitches between adjacent turns, so long as the induced magnetic fields of the wound spiral patterns S1 and S2 are opposite in direction.
It will be appreciated that the arrangement of the first spiral pattern S1 and the second spiral pattern S2 in fig. 7 is interchangeable.
In the low-coupling inductance pair 131 according to the above embodiment of the present application, the microstrip lines of the two inductors have a common terminal and are arranged in two spiral patterns with opposite spiral directions, and when the excitation signal is applied to the low-coupling inductance pair 131 in an operation state, the excitation signal is split to the two spirals (microstrip lines of the two inductors) at the common terminal, so that the directions of induced magnetic fields generated by currents in the two spirals are opposite, thereby reducing mutual coupling/mutual inductance between the two inductors at least partially.
In the above described inductor pair embodiment, as shown in fig. 7, the inductor pair is arranged in an integrated circuit chip to have three terminals: a common terminal 1312, a head terminal 1311 which is a first branch terminal of the inductor pair, and a tail terminal 1313 which is a second branch terminal of the inductor pair. As previously described, the three ends of the pair of inductors may be connected to an excitation signal or other circuit portion by leads. For example, a radio frequency excitation signal may be accessed from the common terminal 1312 of the pair of inductors, the radio frequency excitation signal being split at the common terminal 1312 to a first microstrip line (first inductor) and a second microstrip line (second inductor). The radio frequency excitation signal is typically a periodically varying signal, for example a sinusoidal signal. Let the excitation signal accessed at the common terminal 1312 be i com ＝I com Sin ωt. The excitation signal splits into two branches at the common terminal 1312, one flowing through the common terminal 1312 to a first spiral pattern S1 of a first branch terminal (head terminal) 1311 and the other flowing through the common terminal 1312 to a second spiral pattern S2 of a second branch terminal (tail terminal) 1313. Let the excitation signal in the first spiral pattern S1 be i 1 (t) the excitation signal in the first spiral pattern S1 is i 2 (t) assuming no reflection of the signal, i 1 (t)+i 2 (t)＝I com Sin ωt. If the common terminal is located at the midpoint of the combined microstrip line and S1 and S2 are axisymmetric patterns, the excitation signals in S1 and S2 are identical at any time, i.e Excitation signal i in an inductor pair 1 (t) and i 2 (t) is a periodically varying signal whose current magnitude varies periodically and thus the induced magnetic field produced is also periodically varying unevenly; the changing magnetic field in turn generates an electric field, thereby generating electromagnetic waves. In the case where the excitation signals in S1 and S2 are identical, since the spiral directions of S1 and S2 are opposite, the induced magnetic field generated at any time S1 is identical in magnitude and opposite in direction to the induced magnetic field generated at S2, and the corresponding induced electric field is also opposite in direction and periodically changes direction. Thus S1 and S2 resultThe induction magnetic fields of the induction magnetic field pair are almost completely counteracted in a plurality of areas and partially counteracted in some areas, so that corresponding electric fields or electromagnetic waves caused by the induction magnetic field are counteracted, and the loss of the induction pair is reduced.
If the common terminal is not located at the midpoint of the combined microstrip line, or if the S1 and S2 are patterns with different configurations, it may not be ensured that the excitation signals in the S1 and S2 are identical, so that the degree of mutual cancellation of the induced magnetic fields of the S1 and S2 is reduced compared with the case that the excitation signals in the S1 and S2 are identical, but the induced magnetic fields generated by the S1 and S2 still partially cancel each other at any moment, so that the electromagnetic radiation intensity is weakened mutually, and the loss of the inductance pair is reduced to a certain extent.
It should be noted that, theoretically, the pair of inductors having three ports (the common port, the head end of the combined microstrip line as the first branch port, and the tail end of the combined microstrip line as the second branch port) as described above is a passive lossless network, and since the passive network has reciprocity, the loss of the pair of inductors and the transmission characteristics thereof are reciprocal regardless of which one of the three ports the excitation signal is input from.
The low coupling inductance pair 131 composed of the third inductance L3 and the fourth inductance L4 in the amplifier may employ the low coupling inductance pair arrangement as described above. The above description of the low coupling inductance pairs applies to all low coupling inductance pairs referred to herein and will not be repeated elsewhere herein for brevity.
In the various amplifier embodiments described above, the low coupling inductance pair described above is used, which gives the amplifier of the present application the following advantages: by configuring the two inductors making up the inductor pair such that their respective induced magnetic fields are opposite in direction, making the inductor pair a low coupling inductor pair, the loss of the amplifier input matching circuit can be reduced. In addition, since the coupling between the two inductors constituting the low-coupling inductor pair and the radiation ranges of the induced electric field and the induced magnetic field of the inductors can be reduced in this way, the inductors and other components are disposed closer together, further reducing the circuit size.
The embodiment of the application also provides an electronic device, which comprises the radio frequency chip, and the radio frequency chip comprising the amplifier embodiment of the application can be used in the electronic device.
As shown in fig. 8, the electronic device 1600 includes the radio frequency chip 1500 shown in fig. 6. The electronic device 1600 may be a wireless device or any other electronic device that may use an amplifier.
The wireless device may be a User Equipment (UE), mobile station, terminal, access terminal, subscriber unit, base station, or the like. The wireless device may also be a cellular telephone, a smart phone, a tablet computer, a wireless modem, a Personal Digital Assistant (PDA), a handheld device, a laptop computer, a smart book, a netbook, a cordless telephone, a Wireless Local Loop (WLL) station, a bluetooth device, etc. The wireless device may be capable of communicating with a wireless communication system, may be capable of receiving signals from a broadcast station, signals from one or more satellites, and the like. A wireless device may support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter waves, etc.).
The embodiment of the application provides an amplifier, a radio frequency chip and an electronic device, wherein the amplifier comprises: a field effect transistor; the first end of the drain matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain matching circuit is connected with the radio frequency signal output end; the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end; the grid bias circuit is connected with the third end of the grid matching circuit; the source electrode matching circuit is connected with the source electrode of the field effect transistor; the grid matching circuit comprises a low-coupling inductance pair, wherein the coupling inductance pair is an inductance pair with opposite induction magnetic field directions. In the embodiment of the application, the low-coupling inductance pair is an inductance pair with opposite induction magnetic field directions, the induction electric fields generated by a pair of inductances with opposite induction magnetic fields are opposite in directions, the induction electric fields with opposite directions can be partially counteracted, and the counteracted induction electric fields can not generate radiation, so that the energy loss of the circuit is reduced. In addition, the physical distance of the inductors in the low-coupling inductor pair can be closer due to the partial cancellation of the induced electric field, so that the size of the circuit can be reduced, and the cost can be reduced. The radio frequency chip provided by the application comprises a substrate and the amplifier on the substrate. The radio frequency chip in the embodiment of the application has low power consumption, low noise, small volume and lower cost.
The amplifier in the embodiment of the application can be independently used, can be used in multistage cascade connection, can be applied to an integrated system, or can be applied to a multifunctional chip. The radio frequency chip of the embodiment of the application can also comprise an independently used amplifier, or can comprise a plurality of amplifiers used in cascade connection, or can comprise a plurality of independently used amplifiers.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to requirements, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the functions described above. The functional units and modules in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. In addition, the specific names of the functional units and modules are only for convenience of distinguishing each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the context, and will not be described herein.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any embodiment, reference is made to the related descriptions of other embodiments.
The units or modules described as separate components may or may not be physically separate, and components shown as units or modules may or may not be physical units, may be located in one place, or may be distributed over a plurality of functional units. Some or all of the units or modules may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit or module in each embodiment of the present application may be integrated in one chip unit, or each unit or module may exist alone physically, or two or more units or modules may be integrated in one unit.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is only a specific embodiment of the application to enable those skilled in the art to understand or practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (18)
1. An amplifier, the amplifier comprising:
the field effect transistor comprises a drain electrode, a grid electrode and a source electrode, and is used for signal amplification;
the first end of the drain matching circuit is connected with the drain electrode of the field effect transistor, and the second end of the drain matching circuit is connected with the radio frequency signal output end;
the first end of the grid matching circuit is connected with the grid of the field effect transistor, and the second end of the grid matching circuit is connected with the radio frequency signal input end;
the grid bias circuit is connected with the third end of the grid matching circuit;
The source electrode matching circuit is connected with the source electrode of the field effect transistor;
the grid matching circuit comprises a low-coupling inductance pair, wherein the coupling inductance pair is an inductance pair with opposite induction magnetic field directions.
2. The amplifier of claim 1, wherein the low coupling inductance pair comprises:
the second end of the third inductor is connected with the grid electrode of the field effect transistor;
a fourth inductor, wherein a first end of the fourth inductor is connected with a first end of the third inductor, and a second end of the fourth inductor is connected with the grid bias circuit;
and the induction magnetic fields of the third inductor and the fourth inductor are opposite in direction.
3. The amplifier of claim 2, wherein the gate matching circuit further comprises:
and the first end of the third capacitor is connected with the radio frequency signal input end, and the second end of the third capacitor is connected with the first end of the third inductor.
4. The amplifier of claim 3, wherein the gate bias circuit comprises:
and the first end of the fourth capacitor is grounded, and the second end of the fourth capacitor is connected with the grid bias power supply end.
5. The amplifier of claim 4, wherein the source matching circuit comprises:
the first end of the fifth inductive unit is connected with the source electrode of the field effect transistor, and the second end of the fifth inductive unit is grounded;
the fifth inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.
6. The amplifier of claim 4, wherein the source matching circuit is ground.
7. The amplifier of claim 3, wherein the gate bias circuit is ground.
8. The amplifier of claim 7, wherein the source matching circuit comprises:
the first end of the sixth inductive unit is connected with the source electrode of the field effect transistor;
a fifth capacitor, wherein a first end of the fifth capacitor is connected with a second end of the sixth inductive unit, and a second end of the fifth capacitor is grounded;
the first end of the first resistor is connected with the second end of the sixth inductive unit, and the second end of the first resistor is grounded;
the sixth inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.
9. The amplifier of claim 4, wherein the source matching circuit comprises:
the first end of the seventh inductive unit is connected with the source electrode of the field effect transistor;
a sixth capacitor, wherein a first end of the sixth capacitor is connected to the second end of the seventh inductive unit, the first end of the sixth capacitor is further connected to the source bias power supply end, and a second end of the sixth capacitor is grounded;
the seventh inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line.
10. The amplifier of claim 1, wherein the drain matching circuit comprises:
the first end of the first inductive unit is connected with the drain electrode of the field effect transistor;
the second end of the second inductive unit is connected with the second end of the first inductive unit, and the second end of the second inductive unit is connected with the drain bias power supply end;
the first end of the first capacitor is connected with the second end of the first inductive unit, and the second end of the first capacitor is connected with the radio frequency signal output end;
the first end of the second capacitor is connected with the second end of the second inductive unit, and the second end of the second capacitor is grounded;
The first inductive unit is one of an inductor, a microstrip line or a combination of the inductor and the microstrip line, and/or the second inductive unit is one of the inductor, the microstrip line or the combination of the inductor and the microstrip line.
11. An amplifier according to claim 2, characterized in that the third inductance and the fourth inductance are both spiral inductances and are arranged in the amplifier with opposite spiral directions.
12. The amplifier of claim 2, wherein the third inductance and fourth inductance are arranged in the amplifier as mirror images of each other.
13. The amplifier of claim 2, wherein the third inductor is comprised of a first microstrip line and the first microstrip line is wound in a first spiral pattern, and the fourth inductor is comprised of a second microstrip line and the second microstrip line is wound in a second spiral pattern, wherein the first and second ends of the first microstrip line are respectively the first and second ends of the third inductor, the first and second ends of the second microstrip line are respectively the first and second ends of the fourth inductor, and the second ends of the first microstrip line and the second microstrip line are connected together such that the first microstrip line and the second microstrip line form a combined microstrip line.
14. The amplifier of claim 13, wherein the first and second spiral patterns do not overlap and are adjacent but spaced apart in a direction parallel to a wiring layer of the amplifier.
15. The amplifier of claim 13, wherein the merged microstrip line is comprised of multiple layers of metallic material, wherein each layer of metallic material is located in a different wiring layer of the amplifier.
16. The amplifier of claim 13, wherein the merged microstrip line is comprised of a single layer of metal material, wherein the single layer of metal material is located in the same or different wiring layers of the amplifier.
17. A radio frequency chip comprising a substrate, and the amplifier of any one of claims 1 to 16 on the substrate.
18. An electronic device comprising the radio frequency chip of claim 17.
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| CN202210349333.XA CN116938153A (en) | 2022-04-01 | 2022-04-01 | Amplifier, radio frequency chip and electronic device |
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| CN202210349333.XA CN116938153A (en) | 2022-04-01 | 2022-04-01 | Amplifier, radio frequency chip and electronic device |
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