CN218071445U

CN218071445U - Amplifier, radio frequency chip and electronic device

Info

Publication number: CN218071445U
Application number: CN202220775378.9U
Authority: CN
Inventors: 刘石生; 黄伟
Original assignee: Shenzhen Jingzhun Communication Technology Co ltd
Current assignee: Shenzhen Jingzhun Communication Technology Co ltd
Priority date: 2022-04-01
Filing date: 2022-04-01
Publication date: 2022-12-16
Anticipated expiration: 2032-04-01

Abstract

The embodiment of the application discloses an amplifier, a radio frequency chip and an electronic device. The amplifier includes: a three-port transistor for outputting an inverted amplified signal from the first pole and an in-phase amplified signal from the second pole; the first pole matching circuit comprises 2M branches, wherein the 2i-1 branch is used for transmitting the inverted amplified signal to the 2i-1 radio frequency signal output end to become a 2i-1 amplified signal, and the 2i branch is also used for transmitting the inverted amplified signal to the 2i radio frequency signal output end to become a 2i amplified signal; the second pole matching circuit comprises M branches, wherein the ith branch is used for transmitting the in-phase amplification signal to the 2M +2i-1 radio-frequency signal output end to be the 2M +2i-1 amplification signal, and the ith branch is also used for transmitting the in-phase amplification signal to the 2M +2i radio-frequency signal output end to be the 2M +2i amplification signal; wherein i =1, 8230, M, i is an integer greater than or equal to 1, and M is an integer greater than or equal to 1. The method and the device have higher gain on the premise of not increasing power consumption.

Description

Amplifier, radio frequency chip and electronic device

Technical Field

The application relates to the technical field of electronics, in particular to an amplifier, a radio frequency chip and an electronic device.

Background

With the development of communication technology, especially the emergence of 5G technology, high frequency wireless communication technology is becoming an important development direction of wireless communication.

High frequency wireless communication technology requires a transceiver system including a large number of amplifiers, and the performance of the amplifiers can have a significant impact on the performance of the radio frequency communication transceiver system. Therefore, high frequency wireless communication technology places higher demands on amplifiers, such as gain to power consumption ratio and functional density.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem or at least partially solve the technical problem, the application provides an amplifier, a radio frequency chip and an electronic device.

In a first aspect, the present application provides an amplifier comprising: a three-port transistor including a first pole, a second pole, and a third pole, the three-port transistor being configured to receive a radio frequency signal to be amplified from the third pole of the three-port transistor, amplify the radio frequency signal to be amplified, output an anti-phase amplified signal from the first pole of the three-port transistor, and output an in-phase amplified signal from the second pole of the three-port transistor;

a first pole matching circuit comprising 2M branches,

the first end of the 2i-1 branch of the first pole matching circuit is connected with the first pole of the three-port transistor, the second end of the 2i-1 branch of the first pole matching circuit is connected with the 2i-1 radio frequency signal output end,

the 2i-1 branch of the first pole matching circuit is used for matching the impedance of the first pole of the three-port transistor to a 2i-1 target impedance, the 2i-1 target impedance is the output impedance of the 2i-1 radio frequency signal output end, the 2i-1 branch of the first pole matching circuit is also used for transmitting the inverted amplified signal to the 2i-1 radio frequency signal output end to become a 2i-1 amplified signal,

the first end of the 2i branch of the first pole matching circuit is connected with the first pole of the three-port transistor, the second end of the 2i branch of the first pole matching circuit is connected with the 2i radio frequency signal output end,

the 2i branch of the first pole matching circuit is used for matching the impedance of the first pole of the three-port transistor to a 2i target impedance, the 2i target impedance is the output impedance of a 2i radio frequency signal output end, and the 2i branch of the first pole matching circuit is also used for transmitting the inverted amplified signal to the 2i radio frequency signal output end to become a 2i amplified signal;

a second pole matching circuit, the second pole matching circuit includes M branches, a first end of an ith branch of the second pole matching circuit is connected with a second pole of the three-port crystal, a second end of the ith branch of the second pole matching circuit is connected with a 2M +2i-1 radio frequency signal output end, a third end of the ith branch of the second pole matching circuit is connected with a 2M +2i radio frequency signal output end,

the ith branch of the second pole matching circuit is used for matching second pole output impedance of the three-port transistor to 2M +2i-1 target impedance and 2M +2i target impedance respectively, the 2M +2i-1 target impedance is output impedance of a 2M +2i-1 radio frequency signal output end, the 2M +2i target impedance is output impedance of a 2M +2i radio frequency signal output end, the ith branch of the second pole matching circuit is also used for transmitting the in-phase amplified signal to the 2M +2i-1 radio frequency signal output end to be a 2M +2i-1 amplified signal, and the ith branch of the second pole matching circuit is also used for transmitting the in-phase amplified signal to the 2M +2i radio frequency signal output end to be a 2M +2i-1 amplified signal;

wherein i =1 \ 8230, wherein M is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.

In the embodiment of the present application, the 2i-1 th amplified signal is combined with the 2M +2i-1 th amplified signal, the 2i th amplified signal is combined with the 2M +2i th amplified signal,

wherein i =1, 8230, M, i is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.

In the embodiment of the present application, the combining of the 2i-1 st amplified signal and the 2M +2i-1 st amplified signal, and the combining of the 2i amplified signal and the 2M +2i amplified signal include:

the 2i-1 radio frequency signal output end is connected with the 2M +2i-1 radio frequency signal output end;

the 2i radio frequency signal output end is connected with the 2M +2i radio frequency signal output end;

In an embodiment of the present application, the amplifier further includes:

2M impedance transformation circuits are arranged in the circuit,

the first end of the 2i-1 impedance conversion circuit is connected with the 2i-1 radio frequency signal output end, and the second end of the 2i-1 impedance conversion circuit is connected with the 4M +2i-1 radio frequency signal output end;

the first end of the 2i impedance conversion circuit is connected with the 2i radio frequency signal output end, and the second end of the 2i impedance conversion circuit is connected with the 4M +2i radio frequency signal output end;

In the embodiment of the application, the amplifier also comprises 2M synthesis circuits,

the 2i-1 amplified signal is synthesized with the 2M +2i-1 amplified signal, and the 2i amplified signal is synthesized with the 2M +2i amplified signal, including:

the 2i-1 radio frequency signal output end is connected with a first end of a 2i-1 synthesis circuit, and the 2M +2i-1 radio frequency signal output end is connected with a second end of the 2i-1 synthesis circuit, so that the 2i-1 amplified signal and the 2M +2i-1 amplified signal are synthesized;

the 2i radio frequency signal output end is connected with the first end of the 2i synthesis circuit, and the 2M +2i radio frequency signal output end is connected with the second end of the 2i synthesis circuit, so that the 2i amplified signal and the 2M +2i amplified signal are synthesized;

In an embodiment of the present application, the amplifier further includes:

2M impedance transformation circuits;

the first end of the 2i-1 impedance transformation circuit is connected with the third end of the 2i-1 synthesis circuit, and the second end of the 2i-1 impedance transformation circuit is connected with the output end of the radio frequency signal of the 4M + 2i-1;

the first end of the 2i impedance transformation circuit is connected with the third end of the 2i synthesis circuit, and the second end of the 2i impedance transformation circuit is connected with the output end of the radio frequency signal of 4M +2i;

In an embodiment of the present application, the amplifier further includes:

a third pole matching circuit, wherein a first end of the third pole matching circuit is connected with a radio frequency signal input end, and a second end of the third pole matching circuit is connected with a third pole of the three-port transistor;

the third pole biasing circuit is connected with the third end of the third pole matching circuit;

2M first pole bias circuits, the first end of the 2i-1 st first pole bias circuit is connected with the 2i-1 st first pole bias power supply end,

the first end of the 2i first pole bias circuit is connected with the 2i first pole bias power supply end;

the first ends of the ith second pole bias circuits are connected with the fourth ends of the ith branches of the second pole matching circuits;

In an embodiment of the present application, the 2i-1 th branch of the first pole matching circuit includes:

a 2i-1 branch first inductive unit, a second end of the 2i-1 branch first inductive unit is connected with a first pole of the three-port transistor,

a 2i-1 th sub-circuit second inductive unit, a first end of the 2i-1 th sub-circuit second inductive unit being connected to a 2i-1 st pole bias power supply terminal, a second end of the 2i-1 th sub-circuit second inductive unit being connected to a first end of the 2i-1 th sub-circuit first inductive unit,

the first end of the third inductive unit of the 2i-1 branch is connected with the first end of the first inductive unit of the 2i-1 branch, and the second end of the third inductive unit of the 2i-1 branch is connected with the radio frequency signal output end of the 2i-1 branch;

the 2i branch of the first polar matching circuit includes:

a 2i branch eighth inductive unit, a first end of the 2i branch eighth inductive unit being connected to a first pole of the three-port transistor,

a ninth inductive unit of the 2i branch, a first end of the ninth inductive unit of the 2i branch being connected to a second end of the eighth inductive unit of the 2i branch, a second end of the ninth inductive unit of the 2i branch being connected to a first pole bias power supply terminal of the 2i branch,

a tenth inductive unit of the 2i branch, a first end of the tenth inductive unit of the 2i branch being connected to a second end of the eighth inductive unit of the 2i branch, and a second end of the tenth inductive unit of the 2i branch being connected to the 2i radio frequency signal output end;

In an embodiment of the present application, the ith branch of the second pole matching circuit includes:

the first end of the ith branch fourth inductive unit is connected with the second pole of the three-port transistor;

the first end of the fifth sensing unit of the ith branch is connected with the second end of the fourth sensing unit of the ith branch;

an ith branch first capacitor, wherein a first end of the ith branch first capacitor is connected with a second end of the ith branch fourth inductive unit, and a second end of the ith branch first capacitor is connected with a 2M +2i-1 radio frequency signal output end;

a fifth capacitor of the ith branch, wherein a first end of the fifth capacitor of the ith branch is connected with a second end of the fourth inductive unit of the ith branch, and a second end of the fifth capacitor of the ith branch is connected with the radio-frequency signal output end 2M +2i;

In an embodiment of the present application, the third pole matching circuit includes:

a sixth inductive unit, a first end of the sixth inductive unit being connected to a third pole of the three-port transistor;

a seventh inductive unit, a first end of the seventh inductive unit being connected to a second end of the sixth inductive unit, a second end of the seventh inductive unit being connected to the third pole bias circuit;

and a first end of the second capacitor is connected with the radio frequency signal input end, and a second end of the second capacitor is connected with a second end of the sixth inductive unit.

In this embodiment, the 2i-1 st branch first inductive unit and the 2i-1 st branch second inductive unit are inductive pairs with opposite inductive magnetic fields, and the 2i branch eighth inductive unit and the 2i branch ninth inductive unit are inductive pairs with opposite inductive magnetic fields; and/or the presence of a gas in the gas,

the sixth inductive unit and the seventh inductive unit are inductive pairs with opposite inductive magnetic fields.

In an embodiment of the present application, the third pole bias circuit includes:

and a first end of the third capacitor is grounded, a second end of the third capacitor is connected with a second end of the seventh inductive unit, and the second end of the third capacitor is further connected with a third pole bias power supply end.

In an embodiment of the present application, the ith second pole bias circuit includes:

an ith fourth capacitor, a first end of the ith fourth capacitor is connected to a second end of the fifth inductive unit of the ith branch of the second pole matching circuit, the first end of the ith fourth capacitor is further connected to an ith second pole bias power supply terminal, and the second end of the ith fourth capacitor is grounded;

In the embodiment of the application, the ith second pole bias circuit is a ground, wherein i =1 \ 8230, i \ 8230, M, i is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.

In the embodiment of the present application, the third pole bias circuit is a ground.

an ith sixth capacitor, a first end of the ith sixth capacitor is connected to the second end of the fifth sensing unit of the ith branch, and a second end of the ith sixth capacitor is grounded;

an ith first resistor, wherein a first end of the ith first resistor is connected with a second end of the fifth inductive unit of the ith branch, and a second end of the ith first resistor is grounded;

In an embodiment of the present application, the 2i-1 th first pole bias circuit includes:

a 2i-1 seventh capacitor, wherein a first end of the 2i-1 seventh capacitor is grounded, and a second end of the 2i-1 seventh capacitor is connected with a 2i-1 first electrode bias power supply end;

the 2 i-th first pole bias circuit includes:

a first end of the 2i eighth capacitor is grounded, and a second end of the 2i eighth capacitor is connected with a 2i first electrode bias power supply end;

In a second aspect, the present application provides a radio frequency chip including a substrate, and an amplifier as described above on the substrate.

In a third aspect, an electronic device is provided, which includes the rf chip as described above.

An embodiment of the present application provides an amplifier, including: a three-port transistor including a first pole, a second pole, and a third pole, the three-port transistor being configured to receive a radio frequency signal to be amplified from the third pole of the three-port transistor, amplify the radio frequency signal to be amplified, output an anti-phase amplified signal from the first pole of the three-port transistor, and output an in-phase amplified signal from the second pole of the three-port transistor; a first pole matching circuit, which includes 2M branches, a first end of a 2i-1 branch of the first pole matching circuit is connected with a first pole of the three-port transistor, a second end of a 2i-1 branch of the first pole matching circuit is connected with a 2i-1 radio frequency signal output end, the 2i-1 branch of the first pole matching circuit is used for matching an impedance of the first pole of the three-port transistor to a 2i-1 target impedance, the 2i-1 target impedance is an output impedance of the 2i-1 radio frequency signal output end, the 2i-1 branch of the first pole matching circuit is further used for transmitting the inverted amplified signal to the 2i-1 radio frequency signal output end to become a 2i-1 amplified signal, a first end of a 2i branch of the first pole matching circuit is connected with a first pole of the three-port transistor, a second end of the 2i branch of the first pole matching circuit is connected with a 2i radio frequency signal output end, the 2i branch of the first pole matching circuit is used for matching impedance of the first pole of the three-port transistor to a 2i target impedance, the 2i target impedance is output impedance of the 2i radio frequency signal output end, and the 2i branch of the first pole matching circuit is also used for transmitting the inverted amplified signal to the 2i radio frequency signal output end to become a 2i amplified signal; a second pole matching circuit, which includes M branches, a first end of an ith branch of the second pole matching circuit is connected to a second pole of the three-port crystal, a second end of the ith branch of the second pole matching circuit is connected to a 2m +2i-1 rf signal output end, a third end of the ith branch of the second pole matching circuit is connected to a 2m +2i rf signal output end, the ith branch of the second pole matching circuit is used for matching a second pole output impedance of the three-port transistor to a 2m +2i-1 target impedance and a 2m +2i target impedance respectively, the 2M +2i-1 target impedance is an output impedance of the 2M +2i-1 radio-frequency signal output end, the 2M +2i target impedance is an output impedance of the 2M +2i radio-frequency signal output end, the ith branch of the second pole matching circuit is further used for transmitting the in-phase amplification signal to the 2M +2i-1 radio-frequency signal output end to become a 2M +2i-1 amplification signal, and the ith branch of the second pole matching circuit is further used for transmitting the in-phase amplification signal to the 2M +2i radio-frequency signal output end to become a 2M +2i amplification signal; wherein i =1 \ 8230, wherein M is an integer greater than or equal to 1, and M is an integer greater than or equal to 1. The embodiment of the application can output 4M paths of amplified signals, synthesize the 4M paths of amplified signals according to a preset rule and output 2M paths of synthesized amplified signals, so that the function intensity of the amplifier can be improved; in addition, the gain of the amplifier can be superposed, so that the amplifier has higher gain; in the embodiment of the application, the amplifier only comprises one three-port transistor, and the power consumption of the three-port transistor determines the power consumption of the amplifier, so that the amplifier realizes the gain superposition of a plurality of paths of amplifiers without multiplying the power consumption, and the power-to-power consumption ratio of the amplifier is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.

Fig. 1 to 8, 11 to 15, and 17 to 25 are schematic structural diagrams of an amplifier in an embodiment of the present application;

FIGS. 9, 10 and 16 are signal diagrams of amplifiers in embodiments of the present application;

FIG. 26 is a schematic diagram of an RF chip in an embodiment of the present application;

fig. 27 is a schematic view of an electronic device in an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.

The amplifier provided by the embodiment of the application can be used as an independent component, or can be applied to radio frequency chip or system integration.

As shown in fig. 1, an embodiment of the present application provides an amplifier, including:

a three-port transistor 111 including a first pole, a second pole and a third pole, the three-port transistor 111 being configured to receive a radio-frequency signal SIN to be amplified from the third pole of the three-port transistor 111, and output an inverted amplified signal SO1 from the first pole of the three-port transistor 111 and an in-phase amplified signal SO2 from the second pole of the three-port transistor 111 after amplifying the radio-frequency signal SIN to be amplified;

a first pole matching circuit 112, the first pole matching circuit 112 comprising 2M branches,

a first end of the 2i-1 branch 112_2i-1 of the first pole matching circuit 112 is connected with a first pole of the three-port transistor 111, a second end of the 2i-1 branch 112_2i-1 is connected with a 2i-1 radio frequency signal output end RFOUT _2i-1,

the 2i-1 branch 112_2i-1 of the first pole matching circuit 112 is used for matching the impedance of the first pole of the three-port transistor 111 to a 2i-1 target impedance ZO _2i-1, the 2i-1 target impedance ZO _2i-1 being the output impedance of the 2i-1 radio frequency signal output terminal RFOUT _2i-1, the 2i-1 branch 112_2i-1 of the first pole matching circuit is further used for transmitting the inverted amplified signal SO1 to the 2i-1 radio frequency signal output terminal RFOUT _2i-1 as a 2i-1 amplified signal S _2i-1,

a first terminal of the 2 i-th branch 112\2i of the first pole matching circuit 112 is connected to a first pole of the three-port transistor 111, a second terminal of the 2 i-th branch 112 _2iof the first pole matching circuit 112 is connected to a2 i-th rf signal output terminal,

the 2i branch 112_2i of the first pole matching circuit 112 is configured to match the impedance of the first pole of the three-port transistor 111 to a 2i target impedance ZO _2i, where the 2i target impedance ZO _2i is an output impedance of the 2i rf signal output terminal RFOUT _2i, and the 2i branch 112 _2iof the first pole matching circuit is further configured to transmit the inverted amplified signal SO1 to the 2i rf signal output terminal RFOUT _2i as a 2i amplified signal S _2i;

a second pole matching circuit 113, wherein the second pole matching circuit 113 includes M branches, a first end of an ith branch 113 of the second pole matching circuit 113 is connected to a second pole of the three-port crystal 111, a second end of the ith branch 113 of the second pole matching circuit 113 is connected to a 2m +2i-1 radio frequency signal output end RFOUT _2m +2i-1, a third end of the ith branch 113 of the second pole matching circuit 113 is connected to a 2m +2i radio frequency signal output end RFOUT _2m +2i,

an i branch 113 u i of the diode th matching circuit 113 is used for matching a second pole output impedance of the three-port transistor 111 to a 2m +2i-1 target impedance ZO _2m +2i-1 and a 2m +2i target impedance ZO _2m +2i, the 2m +2i-1 target impedance ZO _2m +2i-1 is an output impedance of the 2m +2i-1 radio frequency signal output end RFOUT _2m +2i-1, the 2m +2i target impedance ZO _2m +2i is an output impedance of the 2m +2i-1 radio frequency signal output end RFOUT _2m +2i, the ith branch 113 u i of the second pole matching circuit 113 is further configured to transmit the in-phase amplified signal SO2 to the 2m +2i-1 radio frequency signal output end RFOUT _2m +2i-1 to become the 2m +2i-1 amplified signal S _2m +2i-1, and the ith branch of the second pole matching circuit is further configured to transmit the in-phase amplified signal SO2 to the 2m +2i radio frequency signal output end RFOUT _2m +2i to become the 2m +2i amplified signal S _2m +2i;

In the embodiment of the present application, the 2i-1 st amplified signal S _2i-1 is combined with the 2M +2i-1 nd amplified signal S _2M +2i-1, the 2i amplified signal S _2i is combined with the 2M +2i th amplified signal S _2M +2i,

In an embodiment of the present application, the 2i-1 st amplified signal S _2i-1 is combined with the 2m +2i-1 nd amplified signal S _2m +2i-1, and the 2i amplified signal S _2i is combined with the 2m +2i th amplified signal S _2m +2i, which includes:

the 2i-1 radio frequency signal output end RFOUT _2i-1 is connected with the 2M +2i-1 radio frequency signal output end RFOUT _2M + 2i-1;

the 2i RF signal output end RFOUT _2i is connected with the 2M +2i RF signal output end RFOUT _2M +2i;

As shown in fig. 2, the amplifier further comprises:

2M impedance transformation circuits are arranged in the circuit,

wherein, the first end of the 2i-1 impedance transformation circuit 150_2i-1 is connected with the 2i-1 radio frequency signal output end RFOUT _2i-1, and the second end of the 2i-1 impedance transformation circuit 150 _u2i-1 is connected with the 4M +2i-1 radio frequency signal output end RFOUT _4M + 2i-1;

a first end of a 2i impedance conversion circuit 150_2i is connected with the 2i radio-frequency signal output end RFOUT _2i, and a second end of the 2i impedance conversion circuit 150_2i is connected with a 4M +2i radio-frequency signal output end RFOUT _4M +2i;

The two amplified signals are synthesized, either directly connected as shown in fig. 2, or connected through a synthesis circuit 190 as shown in fig. 3.

In the embodiment of the present application, as shown in fig. 3, the amplifier further includes 2M synthesis circuits,

the 2i-1 th amplified signal S _2i-1 is synthesized with the 2M +2i-1 nd amplified signal S _2M +2i-1, and the 2i th amplified signal S _2i is synthesized with the 2M +2i th amplified signal S _2M +2i, including:

the 2i-1 radio frequency signal output end RFOUT _2i-1 is connected with the first end of the 2i-1 synthesis circuit 190_2i-1, and the 2M +2i-1 radio frequency signal output end RFOUT _2M +2i-1 is connected with the second end of the 2i-1 synthesis circuit 190_2i-1, so that the 2i-1 amplification signal S _2i-1 and the 2M +2i-1 amplification signal S _2M +2i-1 are synthesized;

the 2i radio frequency signal output end RFOUT _2i is connected with the first end of the 2i synthesis circuit 190 u 2i, and the 2M +2i radio frequency signal output end RFOUT _2M +2i is connected with the second end of the 2i synthesis circuit 190 u 2i, so that the 2i amplification signal S _2i and the 2M +2i amplification signal S _2M +2i are synthesized;

As shown in fig. 3, the amplifier further comprises:

2M impedance transformation circuits;

wherein, the first end of the 2i-1 th impedance conversion circuit 150_2i-1 is connected with the third end of the 2i-1 th synthesis circuit 190_2i-1, and the second end of the 2i-1 th impedance conversion circuit 150_2i-1 is connected with the output end RFOUT _4M +2i-1 of the radio frequency signal of the 2i-1 st impedance conversion circuit 150_2i-1;

a first end of a 2i impedance conversion circuit 150_2i is connected with a third end of a 2i synthesis circuit 190_2i, and a second end of the 2i impedance conversion circuit 150_2i is connected with an 4mj2i radio-frequency signal output end RFOUT _4M +2i;

As shown in fig. 1, in the embodiment of the present application, the amplifier further includes:

a third pole matching circuit 130, a first terminal of the third pole matching circuit 130 being connected to the radio frequency signal input terminal RFIN, a second terminal of the third pole matching circuit 130 being connected to a third pole of the three-port transistor 111;

a third pole bias circuit 160, wherein the third pole bias circuit 160 is connected to a third terminal of the third pole matching circuit 130;

2M first pole bias circuits 120, the first terminal of the 2i-1 st pole bias circuit 120 u 2i-1 is connected to the 2i-1 st pole bias power supply terminal V1_2i-1,

the first end of the 2 i-th first pole bias circuit 120 (u 2i) is connected with a2 i-th first pole bias power supply end V1_ 2i;

m second pole bias circuits 140, a first end of the ith second pole bias circuit 140_ibeing connected to a fourth end of the ith branch 113 \iof the second pole matching circuit 113;

In the embodiment of the present application, the plurality of first electrode bias power terminals may be physically independent, but electrically equivalent. Therefore, for convenience of description, the first bias power supply terminals V1_2i-1 and V1_2i can be directly referred to as the first bias power supply terminal V1 in the embodiments and the drawings of the present application.

In the embodiment of the present application, although there are a plurality of first-pole bias power supply terminals, it is only necessary that any one of the first-pole bias power supply terminals is connected to the first-pole bias power supply. Likewise, the second pole bias power supply V2 and/or the third pole bias unit V3 may be provided as described above.

In the embodiment of the present application, the 2M branches of the first pole matching circuit 112 may be the same or may be different; similarly, the M branches of the second pole matching circuit 113 may be the same or may be different; the M second pole bias circuits 140 may be the same or may be different; the M impedance matching circuits 150 may be identical or may be different; the M combining circuits 190 may be the same or different, and are not described herein.

In the above, i =1 \ 8230, M8230, i is an integer of 1 or more, and M is an integer of 1 or more.

The following describes a specific embodiment, an operation principle, advantageous effects, and the like of the present application with M = 1.

M =1, as in the embodiment shown in fig. 4, the first pole matching circuit 112 of the amplifier includes two branches, 112_1 and 112_2, respectively; the second pole matching circuit 113 comprises a branch, 113_1; 2 first

pole bias circuits

120, 120 _1and 120_2, respectively; 1 second pole bias circuit 140_1; 2

impedance transformation circuits

150, 150 _1and 150_2, respectively; and outputting the two paths of synthesized amplified radio-frequency signals through a 5 th radio-frequency signal output end RFOUT _5 and a 6 th radio-frequency signal output end RFOUT _6.

At this time, the first terminal of the 1 st branch 112_1 of the first pole matching 112 circuit is connected to the first pole of the transistor 111, the second terminal of 112_1 outputs the amplified signal S _1,

a first terminal of a2 nd branch 112_2 of the first pole matching 112 circuit is connected to a first pole of the transistor 111, and a second terminal of the 112_2 outputs an amplified signal S _2;

a first end of the 1 st branch 113_1 of the second diode matching circuit 113 is connected to a second pole of the three-port transistor, a second end of the 1 st branch 113_1 of the second diode matching circuit 113 outputs an amplified signal S _3, and a third end of the 1 st branch 113_1 of the second diode matching circuit 113 outputs an amplified signal S _4;

wherein, S _1 and S _3 are combined, and S _2 and S _4 are combined.

In the embodiment of the present application, the S _1 and S _3 phase combining and the S _2 and S _4 phase combining may be performed such that the second end of the 1 st branch 112 _1of the first pole matching circuit 112 is directly connected to the second end of the 1 st branch 113 _1of the second pole matching circuit 113, and the second end of the 2 nd branch 112 _2of the first pole matching circuit 112 is directly connected to the third end of the 1 st branch 113 _1of the second pole matching circuit 113, as shown in fig. 4; or may be connected through the 1 st synthesizing circuit 190 u 1 and the 2 nd synthesizing circuit 190 u 2, respectively, as shown in fig. 5.

The 1 st synthesizing circuit 190_1 and the 2 nd synthesizing circuit 190_2 may be couplers, or may be other circuits that can synthesize radio frequency signals.

The 1 st branch 112_1 of the first pole matching circuit 112 is used for matching the impedance of the first pole of the three-port transistor 111 to the 1 st target impedance ZO _1; the 2 nd branch 112 _2of the first pole matching circuit 112 is used to match the impedance of the first pole of the three-port transistor 111 to the 2 nd target impedance ZO _2.

The amplifier of the embodiment of the present application further includes a first pole bias circuit 120, a third pole matching circuit 130, a second pole bias circuit 140, an impedance transformation circuit 150, and a third pole bias circuit 160.

The 1 st first pole bias circuit 120_1 is used for providing a bias voltage V1_1 to the first pole of the transistor 111 and simultaneously providing a radio frequency signal ground to the third end of the 1 st branch 112_1 of the first pole matching circuit 112; the 2 nd first pole bias circuit 120_2 is used to provide a bias voltage V1_2 to the first pole of the transistor 111 while providing a radio frequency signal ground to the third terminal of the 2 nd branch 112 _2of the first pole matching circuit 112.

In the 1 st first pole bias circuit 120 _1and the 2 nd first pole bias circuit 120_2, since the first pole bias voltage terminals V1_1 and V1_2 are electrically equivalent, any first pole bias circuit can be connected to the first bias power supply V1, and the first bias power supply V1 provides a bias power supply signal for the first pole of the transistor.

The 1 st branch 113_1 of the second diode matching circuit 113 is used to match the second diode output impedance of the three-port transistor 111 to the 3 rd and 4 th target impedances ZO _3 and ZO _4.

The third pole matching circuit 130 is for matching the input impedance of the third pole of the transistor 111 to the 5 th target impedance.

The 1 st second pole bias circuit 140_1 is used to provide a bias voltage V2 (not shown) to the second pole of the transistor 111 while providing the rf signal ground to the fourth terminal of the 1 st branch 113_1 of the second stage matching circuit.

The 1 st impedance transformation circuit 150_1 is for transforming a combined impedance of the 1 st and 3 rd target impedances ZO _1 and ZO _3 to an output impedance ZO _5 of the amplifier, and the 2 nd impedance transformation circuit 150 _2is for transforming a combined impedance of the 2 nd and 4 th target impedances ZO _2 and ZO _4 to an output impedance ZO _6 of the amplifier.

The 1 st impedance conversion circuit 150_1 in the embodiment of the present application has a function of blocking the first end of the 1 st impedance conversion circuit 150 _1from ground, and also has a function of blocking the first end of the 1 st impedance conversion circuit 150 _1from the second end of the 1 st impedance conversion circuit 150_1. The function of the 2 nd impedance transformation circuit 150_2 is the same as that of the 1 st impedance transformation circuit 150_1, and will not be described again.

The 1 st impedance transformation circuit 150 _1and the 2 nd impedance transformation circuit 150 _2in the embodiments of the present application may each be a lambda/4 impedance transformation circuit of the prior art, or may be any impedance matching network of the prior art that can achieve the requirements of the amplifier of the embodiments of the present application.

In the embodiment of the present application, the transistor 111 and the 1 st branch 112 _1of the first polar matching circuit 112 form a first rf signal amplifying link, and the transistor 111 and the 2 nd branch 112 _2of the first polar matching circuit 112 form a second rf signal amplifying link, so that two rf signal amplifying links are shared in this embodiment, and two amplified signals S _1 and S _2 are output. The transistor 111 and the second stage matching circuit 113 form a second rf signal amplification chain, and output two amplified signals S _3 and S _4.

An amplified signal output by a first rf signal amplification chain and an amplified signal output by a second rf signal amplification chain may be combined, specifically, combined S _1 and S _3, and combined S _2 and S _4. The synthesized S _1 and S _3 are output through the 1 st impedance conversion circuit 150_1, and the synthesized S _2 and S _4 are output through the 2 nd impedance conversion circuit 150_2, so that two paths of synthesized amplified signals are output by the embodiment.

In the embodiment of the present application, the input signal, the output signal, and the amplified signal are all radio frequency signals.

In the embodiment of the present invention, when the three-port transistor 111 is a field effect transistor 1111, the first electrode is a Drain (Drain, D electrode), the second electrode is a Source (S electrode), and the third electrode is a Gate (Gate, G electrode). At this time, the first stage matching circuit 112 is a drain matching circuit 112, the second stage matching circuit 113 is a source matching circuit 113, the third stage matching circuit 130 is a gate matching circuit 130, the second stage biasing circuit 140 is a source biasing circuit 140, and the third stage biasing circuit 160 is a gate biasing circuit 160. The drain bias voltage of the corresponding field effect transistor 1111 is VD, the source bias voltage of the field effect transistor 1111 is VS, and the gate bias voltage of the field effect transistor 1111 is VG

In the prior art, according to the working principle of the fet 1111, the drain current of the fet 1111 and the source current of the fet 1111 are in opposite phases, and in an ideal state, the drain current and the source current are equal.

In the embodiment of the present application, the amplifier shown in fig. 4 and 5 can be decomposed into 2 rf signal amplifiers based on the operating principle of the three-port transistor 111 for amplifying the rf signal. When the three-port transistor 111 is a field effect transistor 1111, it is a common source amplifier shown in fig. 6 and a source follower amplifier shown in fig. 7, respectively. A radio frequency signal SIN to be amplified is input by a gate matching circuit 130, and outputs two amplified signals S _1 and S _2 through an equivalent common source amplifier, and a source follower amplifier outputs two amplified signals S _3 and S _4, wherein S _1 and S _3 are synthesized, S _2 and S _4 are synthesized, and finally two paths of synthesized radio frequency amplified signals are output in common, that is, each path of synthesized radio frequency amplified signal is a radio frequency signal obtained by amplifying two paths and synthesizing the two paths of amplified signals into one path, as shown in fig. 8, S _1 and S _3 are synthesized and then output through a 1 st impedance transformation circuit 150 xu 1, and S _2 and S _4 are synthesized and then output through a2 nd impedance transformation circuit 150 xu 2.

The working principle of the signal synthesis and amplification is described in detail below by taking one path of the synthesized and amplified signal as an example. As shown in fig. 6, the fet 1111, the gate matching circuit 130, the gate bias circuit 160, the 1 st branch 112 _1of the drain matching circuit 112, the 1 st drain bias circuit 120_1, the 2 nd branch 112 _2of the drain matching circuit 112, the 2 nd drain bias circuit 120_2, and the source equivalent impedance ZS form an equivalent common-source amplifier, and signals amplified by the equivalent common-source amplifier are respectively output from the 1 st branch 112 _1rf output port RFOUT _1 and the 1 st branch 112 _1rf output port RFOUT _2, wherein the source equivalent impedance ZS is an equivalent impedance at the first end of the source matching circuit 113. The rf signal SIN to be amplified is input from the gate matching circuit 130, drives the gate of the fet 1111, and outputs an inverted amplified signal SO1 after being inverted and amplified by the fet 1111, and the inverted amplified signal SO1 passes through the two branches 112_1 and 112_2 of the drain matching circuit 112 and then outputs the amplified signals S _1 and S _2, respectively.

As shown in fig. 7, the fet 1111, the gate matching circuit 130, the gate bias circuit 160, the 1 st source matching circuit 113_1, the 1 st source bias circuit 140_1, and the drain equivalent impedance ZD constitute an equivalent source follower amplifier, and the source matching circuit 113 _1of the source follower amplifier has two rf signal output ports, i.e., rf signal output ports RFOUT _3 and RFOUT _4, respectively, wherein the drain equivalent impedance ZD is the equivalent impedance at the first end of the drain matching circuit 112. The radio frequency signal SIN to be amplified is input from the gate matching circuit 130, drives the gate of the field effect transistor 1111, is followed and amplified by the field effect transistor 1111 to output a following amplification signal SO2, and the following amplification signal SO2 passes through the 1 st source matching circuit 113_1 to output amplification signals S _3 and S _4.

As shown in fig. 9 (a) and fig. 9 (b), if the SO1 and the SO2 are directly synthesized, amplitudes thereof cancel each other, ideally the SO1 and the SO2 are completely cancelled after being synthesized, and a synthesis state after being completely cancelled is shown in fig. 9 (c), at this time, the amplifier cannot effectively amplify the radio frequency signal.

In the embodiment of the present application, the amplifier of fig. 6 and the amplifier of fig. 7 adopt corresponding matching circuits, and ideally, the phase difference between the amplified signal S _1 and the amplified signal S _3 can be made to be 2n pi, where n is an integer, as shown in fig. 10 (a) and 10 (b).

The amplifiers of fig. 6 and 7 are connected and can be equivalent to two circuits as shown in fig. 8, where the amplified signals S _1 and S _3 are combined and, similarly, S _2 and S _4 are combined. After two continuous and periodic signals with the phase difference of 2n pi are superposed, corresponding wave crests and wave crests, wave troughs and wave troughs can be superposed, and the amplitude of the signals is enhanced. One possible case is that the phase difference between the peaks of the two signals is 0, and the two signals are superimposed as shown in fig. 10 (c).

As described above, the amplifier of the embodiment of the present application outputs two paths of synthesized and amplified radio frequency signals, and each path of synthesized and amplified radio frequency signal performs two paths of amplification on a radio frequency input signal, that is, each path of synthesized and amplified signal realizes two paths of amplification of a radio frequency signal through a common source amplifier and a source follower amplifier, and the two paths of amplified signals are synthesized, so that the amplitudes of the amplifier signals are superimposed, and the amplifier has higher gain. The method and the device output two paths of synthesized amplification signals, so that one path of input signals are converted into two paths of amplification signals with higher gains, and therefore the amplification signals have higher gain and power consumption ratios.

In the embodiment of the present application, the amplifier includes only one three-port transistor 111, for example, the field effect transistor 1111 of the above embodiment, and the power consumption of the three-port transistor 111 determines the power consumption of the amplifier, so that the amplifier of the embodiment of the present application realizes outputting two paths of synthesized and amplified radio frequency signals, each path of synthesized and amplified radio frequency signal realizes gain superposition, and the power consumption of the amplifier is not doubled, thereby improving the gain-to-power consumption ratio of the amplifier. That is, the power consumption of the amplifier of the embodiment of the present application is only equivalent to that of one common source amplifier or one source follower amplifier, but two paths of synthesized and amplified radio frequency signals can be simultaneously output, and the gain is larger, so that the amplifier has a larger gain-to-power consumption ratio.

In the prior art, if two amplifiers are simply combined, that is, the two amplifiers amplify and output the same input signal at the same time and then directly superpose, since the two amplifiers respectively include a three-port transistor 111, the power consumption of the combined circuit is also doubled. The amplifier of the embodiment of the application enables the gains of the multipath signals of the amplifier to be superposed, but because only one three-port transistor 111 is adopted, the power consumption is not multiplied, and the power-to-power ratio of the amplifier is improved. Meanwhile, the embodiment of the application also outputs two paths of synthesized amplified radio-frequency signals at the same time, and the gain is higher. In addition, the amplifier provided by the embodiment of the application has the functions of single-path input and multi-path output, can replace a circuit or a module or a system which is combined and applied by a power divider and a plurality of amplifiers, and obviously improves the function integration level and the function density; because the loss of the power divider and the power consumption of the amplifiers are avoided, the gain-to-power consumption ratio is effectively improved; meanwhile, the amplifier circuit is simple, occupies a small space, is easy to design and manufacture, and can obviously reduce the cost of an amplifier or a circuit module or a system.

In addition, the same transistor is adopted to output two amplified signals, so that the functions of the amplifier are more intensive. In the embodiment of the present application, optimization for gain, power, and noise can also be achieved by adjusting the drain matching circuit 112 and the source matching circuit 113.

In the embodiment of the present application, as shown in fig. 11, the drain matching circuit 112 of the amplifier includes two branches, and the 1 st branch 112_1 of the drain matching circuit 112 includes:

a first inductive unit L1_1 in branch 1, wherein a second end of the first inductive unit L1_1 in branch 1 is connected to a drain of the fet 1111;

a branch 1 second inductive unit L2_1, a first end of the branch 1 second inductive unit L2_1 being connected to the drain bias power source terminal VD, a second end of the branch 1 second inductive unit L2_1 being connected to a first end of the branch 1 first inductive unit L1_ 1;

a third inductive unit L3_1 in the 1 st branch, a first end of the third inductive unit L3_1 in the 1 st branch is connected to a first end of the first inductive unit L1_1 in the 1 st branch, and a second end of the third inductive unit L3_1 in the 1 st branch is connected to a radio frequency signal output terminal RFOUT _1 in the 1 st branch.

In the embodiment of the present application, any inductive unit may be any one of an inductor, a microstrip line, and a combination of an inductor and a microstrip line.

As shown in fig. 11, the 2 nd branch 112_2 of the drain matching circuit 112 includes:

a eighth inductive unit L8_2 in the branch 2, wherein a first end of the eighth inductive unit L8_2 in the branch 2 is connected to the drain of the three-port transistor 111,

a ninth inductive unit L9_2 of the 2 nd branch, a first end of the ninth inductive unit L9_2 of the 2 nd branch being connected to a second end of the eighth inductive unit L8_2 of the 2 nd branch, a second end of the ninth inductive unit L9_2 of the 2 nd branch being connected to a drain bias power source terminal VD,

a tenth inductive unit L10_2 in the 2 nd branch, wherein a first end of the tenth inductive unit L10_2 in the 2 nd branch is connected to a second end of the eighth inductive unit L8_2 in the 2 nd branch, and a second end of the tenth inductive unit L10_2 in the 2 nd branch is connected to a2 nd radio frequency signal output end RFOUT _2;

as shown in fig. 11, the 1 st branch 113_1 of the source matching circuit 113 includes:

a fourth inductive unit L4_1 of branch 1, wherein a first end of the fourth inductive unit L4_1 of branch 1 is connected to a source electrode of the field effect transistor 1111;

a fifth inductive unit L5_1 in branch 1, wherein a first end of the fifth inductive unit L5_1 in branch 1 is connected to a second end of the fourth inductive unit L4_1 in branch 1;

a first capacitor C1_1 of the 1 st branch, wherein a first end of the first capacitor C1_1 of the 1 st branch is connected to a second end of the fourth inductive unit L4_1 of the 1 st branch, and a second end of the first capacitor C1_1 of the 1 st branch is connected to a 3 rd radio frequency signal output end RFOUT _ 3;

a fifth capacitor C5_1 in the 1 st branch, a first end of the fifth capacitor C5_1 in the 1 st branch is connected to a second end of the fourth inductive unit L4_1 in the 1 st branch, and a second end of the fifth capacitor C5_1 in the 1 st branch is connected to the 4 th rf signal output end RFOUT _4.

In this embodiment, the first inductive unit L1_1 in the 1 st branch and the second inductive unit L2_1 in the 1 st branch are inductor pairs with opposite inductive magnetic fields.

In the embodiment of the application, the pair of inductors with opposite induction magnetic fields is formed by a pair of inductors with opposite induction magnetic fields. That is, the 1 st branch first inductive unit L1_1 and the 1 st branch second inductive unit L2_1 are inductive pairs with opposite inductive magnetic fields, and only the 1 st branch first inductance L1_1 and the 1 st branch second inductance L2_1 can be used. Other inductor pairs are the same as the inductor pairs described above and are not described in detail herein.

When the inductor is excited by a signal, an induction magnetic field can be generated, an induction electric field can be generated by the induction magnetic field, and radiation can be generated by the induction electric field, so that energy loss is generated; therefore, an induced magnetic field is also present in the first inductor L1_1 of the 1 st branch and the second inductor L2_1 of the 1 st branch, and an energy loss is generated by an induced electric field generated by the induced magnetic field.

In this embodiment of the application, the first inductance L1_1 of the 1 st branch and the second inductance L2_1 of the 1 st branch are low-coupling inductance pairs, the directions of the induced magnetic fields of the first inductance L1_1 of the 1 st branch and the second inductance L2_1 of the 1 st branch are opposite, so that the directions of the induced electric field generated by the induced magnetic field of the first inductance L1_1 of the 1 st branch and the induced electric field generated by the induced magnetic field of the second inductance L2_1 of the 1 st branch are also opposite, the two opposite induced electric fields can be partially offset, so that the radiation generated by the induced electric field is reduced, and thus the energy loss is reduced.

Because the induced electric field between the 1 st branch circuit first inductor L1_1 and the 1 st branch circuit second inductor L2_1 is partially offset, the physical distance between the 1 st branch circuit first inductor L1_1 and the 1 st branch circuit second inductor L2_1 can be closer, so that the size of the circuit can be reduced, and the cost can be reduced.

Similarly, the eighth inductive unit L8_2 in the 2 nd branch and the ninth inductive unit L9_2 in the 2 nd branch are an inductance pair with opposite inductive magnetic fields, so that energy loss can be reduced, the size of the circuit can be reduced, and the cost can be reduced.

In the embodiment of the present application, as shown in fig. 11, the amplifier further includes:

a gate matching circuit 130, a first terminal of the gate matching circuit 130 is connected to a radio frequency signal input terminal RFIN, and a second terminal of the gate matching circuit 130 is connected to the gate of the fet 1111;

the gate bias circuit 160, the gate bias circuit 160 is connected to the third terminal of the gate matching circuit 130;

two drain bias circuits 120, a first terminal of the 1 st drain bias circuit 120 _1is connected to a drain bias power supply terminal VD, a second terminal of the 1 st drain bias circuit 120 _1is connected to a third terminal of the 1 st branch 112 _1of the drain matching circuit,

a first end of the 2 nd drain bias circuit 120_2 is connected to a drain bias power supply terminal VD, and a second end of the 2 nd drain bias circuit 120_2 is connected to a third end of the 2 nd branch 112_2 of the drain matching circuit;

a first terminal of the 1 st source bias circuit 140 _1is connected to a fourth terminal of the 1 st branch 113 _1of the source matching circuit 113, and a first terminal of the 1 st source bias circuit 140 _1.

In this embodiment, the gate matching circuit 130, the drain bias circuit 120, and the source bias circuit 140 have various implementation forms, as shown in fig. 11, the gate matching circuit 130 includes:

a sixth inductive unit L6, a first end of the sixth inductive unit L6 is connected to the gate of the fet 1111;

a seventh inductive unit L7, wherein a first end of the seventh inductive unit L7 is connected to a second end of the sixth inductive unit L6, and a second end of the seventh inductive unit L7 is connected to the gate bias circuit 160;

a second capacitor C2, a first end of the second capacitor C2 being connected to the radio frequency signal input terminal RFIN, and a second end of the second capacitor C2 being connected to a second end of the sixth inductive unit L6.

As shown in fig. 11, the gate bias circuit 160 includes:

a first end of the third capacitor C3 is grounded, a second end of the third capacitor C3 is connected to a second end of the seventh inductive unit L7, and a second end of the third capacitor C3 is further connected to a gate bias power supply terminal VG.

In the embodiment of the present application, the resonant point frequency of the third capacitor C3 is close to or the same as the center frequency of the operating frequency band of the amplifier, and is used for realizing the isolation of the amplifier from the rf ac signal of the gate bias power supply terminal VG and providing the rf signal ground for the second terminal of the seventh inductive unit L7.

Similarly, the directions of the induced magnetic fields of the sixth inductor L6 and the seventh inductor L7 are opposite, so that the energy loss can be reduced, the size of the circuit can be reduced, and the cost can be reduced, which is not described herein again.

In this embodiment of the application, the 1 st branch first inductor L1_1 and the 1 st branch second inductor L2_1 with opposite directions of the induced magnetic field may be referred to as a low-coupling inductor pair, and similarly, the 2 nd branch eighth inductor L8_2 and the 2 nd branch ninth inductor L9_2 with opposite directions of the induced magnetic field may be referred to as a low-coupling inductor pair, and the sixth inductor L6 and the seventh inductor L7 with opposite directions of the induced magnetic field may also be referred to as a low-coupling inductor pair. The amplifier in the embodiment of the present application may not have any low coupling inductance pair, as shown in fig. 11 and 12; or may include a low-coupling inductor pair composed of a first inductor L1_1 of the 1 st branch and a second inductor L2_1 of the 1 st branch with opposite directions of the induced magnetic field, and a low-coupling inductor pair composed of an eighth inductor L8_2 of the 2 nd branch and a ninth inductor L9_2 of the 2 nd branch with opposite directions of the induced magnetic field, as shown in fig. 13; or may include only the low-coupling inductor pair composed of the sixth inductor L6 and the seventh inductor L7 with opposite induction magnetic field directions, as shown in fig. 14; or the inductor may include two pairs of low-coupling inductor pairs composed of a 1 st branch first inductor L1_1 and a 1 st branch second inductor L2_1 with opposite directions of the induced magnetic field, and also include a low-coupling inductor pair composed of a sixth inductor L6 and a seventh inductor L7 with opposite directions of the induced magnetic field, and a low-coupling inductor pair composed of a2 nd branch eighth inductor L8_2 and a2 nd branch ninth inductor L9_2 with opposite directions of the induced magnetic field, as shown in fig. 15.

In the embodiment shown in fig. 11, the 1 st source bias circuit 140\ u 1 includes:

a 1 st fourth capacitor C4_1, wherein a first end of the 1 st fourth capacitor C4_1 is connected to the second end of the 1 st branch fifth inductive unit L5_1, a first end of the 1 st fourth capacitor C4_1 is further connected to a source bias power source terminal VS, and a second end of the 1 st fourth capacitor C4_1 is grounded.

In this embodiment, the resonant frequency of the 1 st fourth capacitor C4_1 is close to or the same as the center frequency of the operating frequency band of the amplifier, so as to implement isolation of the amplifier from the radio frequency ac signal of the source bias power source terminal VS, and provide a radio frequency signal ground for the second end of the 1 st branch fifth inductive unit L5_ 1.

In the embodiment shown in fig. 11, the 1 st drain bias circuit 120\ u 1 includes:

a 1 st seventh capacitor C7_1, wherein a first end of the 1 st seventh capacitor C7_1 is grounded, and a second end of the 1 st seventh capacitor C7_1 is connected to a drain bias power supply terminal VD.

The 2 nd drain bias circuit 120 _2includes:

a2 nd eighth capacitor C8_2, wherein a first end of the 2 nd eighth capacitor C8_2 is grounded, and a second end of the 2 nd eighth capacitor C8_2 is connected to the drain bias power supply terminal VD.

In this embodiment, the resonant point frequencies of the 1 st seventh capacitor C7_1 and the 2 nd eighth capacitor C8_2 are close to or the same as the center frequency of the operating frequency band of the amplifier, so as to achieve the isolation of the amplifier from the rf ac signal of the drain bias power source VD, meanwhile, the 1 st seventh capacitor C7_1 provides the rf signal ground for the first end of the second inductive unit L2_1 of the 1 st branch 112 xu 1 of the drain matching circuit 112, and the 2 nd eighth capacitor C8_2 provides the rf signal ground for the second end of the ninth inductive unit L9_2 of the 2 nd branch 112 xu 2 of the drain matching circuit 112.

In the amplifier shown in fig. 11, when the amplified signals outputted from the amplifiers are combined, they can be directly combined, as shown in fig. 12, after the 1 st rf signal output terminal RFOUT _1 and the 3 rd rf signal output terminal RFOUT _3 are connected, they are connected to the first terminal of the 1 st impedance transformation circuit 150 \1; a second terminal of the 1 st impedance transformation circuit 150\ \ u 1 is connected to the 5 th rf signal output terminal RFOUT _ 5. After the 2 nd radiofrequency signal output end RFOUT _2 and the 4 th radiofrequency signal output end RFOUT _4 are connected, the 2 nd radiofrequency signal output end RFOUT _2 is connected with a first end of the 2 nd impedance transformation circuit 150_2; a second terminal of the 2 nd impedance transforming circuit 150 u 2 is connected to the 6 th rf signal output terminal RFOUT _6.

In the embodiment shown in fig. 11 to fig. 15, the gate bias voltage VG is provided to the field-effect transistor 1111 of the amplifier through the gate bias power supply terminal VG, the drain bias voltage VD is provided to the field-effect transistor 1111 of the amplifier through the drain bias power supply terminal VD, the source bias voltage VS is provided to the field-effect transistor 1111 of the amplifier through the source bias power supply terminal VS, the voltage difference between VG and VS is adjusted to be the gate-source bias voltage difference of the normal working state of the field-effect transistor 1111, and the voltage difference between VD and VS is adjusted to be the drain-source bias voltage difference of the normal working state of the field-effect transistor 1111, so that the field-effect transistor 1111 is in the normal working state. Radio frequency signals are input through a radio frequency signal input end RFIN, pass through a grid matching circuit 130, drive a grid of a field effect tube 1111 in the amplifier, are amplified through the field effect tube 1111, and then respectively output two amplification signals through two branches of a drain matching circuit 112, and further output two amplification signals through a source matching circuit 113, one amplification signal output by the drain matching circuit 112 is synthesized with one amplification signal output by the source matching circuit 113, and the two paths of synthesized amplification signals are respectively output through a 5 th radio frequency signal output end RFOUT _5 and a 6 th radio frequency signal output end RFOUT _6 after respectively passing through a 1 st impedance transformation circuit 150 xu 1 and a2 nd impedance transformation circuit 150 xu 2.

The phase shifting effect of the matching circuit on the radio frequency signal is explained below.

In the embodiment of the present application, each of the drain matching circuit 112 and the source matching circuit 113 includes an inductive unit and a capacitor, and taking a branch as an example, the phase of the rf signal SO1 output by the drain of the fet 1111 and the phase of the rf signal SO2 output by the source of the fet 1111 may shift accordingly, for example, the series connection of the inductive unit may cause a phase lag, and the series connection of the capacitor may cause a phase lead.

The link of the 1 st branch 112 _1of the drain matching circuit 112, etc. may shift the phase of the signal of S _1 with respect to the signal of SO1 by Δ Φ 1, and the link of the 1 st branch 113 _1of the source matching circuit 113, etc. may shift the phase of the signal of S _3 with respect to the signal of SO2 by Δ Φ 2, as shown in fig. 16. Wherein the absolute value of the difference between Δ φ 1 and Δ φ 2 is about (2 n-1) π, and n is an integer. Since SO1 and SO2 are in opposite phases and have a phase difference of pi, the phase difference between S _1 and S _3 is 2n pi, and n is an integer. Therefore, S _1 and S _3 are combined and superimposed at the first end of the 1 st impedance transformation circuit 150_1, and the signal amplitude is enhanced. In the schematic diagram shown in fig. 16, only one period of signals among SO1, S _1, SO2, and S _3 is shown, and in reality, SO1, S _1, SO2, and S _3 are all periodic continuous signals.

FIG. 16 only shows the case where the phase difference is a specific difference, and in practice, the phase difference of S _1 and S _3 can be designed to be 2n π + φ, n is an integer, φ is a designed target phase value. Adjusting phi can adjust the efficiency of gain synthesis of two paths of signals, so that the performance of the amplifier can tilt to some extent towards other performances, such as stability factor, noise coefficient, output power, linearity, power consumption efficiency and the like.

As shown in fig. 17, in the embodiment of the present application, the 1 st source bias circuit 140 _1is ground. I.e. the second terminal of the 1 st branch of the fifth inductive unit L5_1 is directly connected to ground.

In the embodiment shown in fig. 17, the amplifier does not include a low coupled inductor pair when the 1 st source bias circuit 140_1 is at ground. In other embodiments of the present application, a low-coupling inductor pair comprising a first inductor L1_1 in the 1 st branch and a second inductor L2_1 in the 1 st branch with opposite directions of the induced magnetic field, and a low-coupling inductor pair comprising an eighth inductor L8_2 in the 2 nd branch and a ninth inductor L9_2 in the 2 nd branch with opposite directions of the induced magnetic field may be included, as shown in fig. 18; or may include only the low-coupling inductor pair composed of the sixth inductor L6 and the seventh inductor L7 with opposite directions of the induced magnetic field, as shown in fig. 19; or the inductor pair may include two pairs of low-coupling inductor pairs including a first inductor L1_1 of the 1 st branch and a second inductor L2_1 of the 1 st branch, which have opposite directions of the induced magnetic field, a low-coupling inductor pair including an eighth inductor L8_2 of the 2 nd branch and a ninth inductor L9_2 of the 2 nd branch, which have opposite directions of the induced magnetic field, and a low-coupling inductor pair including a sixth inductor L6 and a seventh inductor L7, which have opposite directions of the induced magnetic field, as shown in fig. 20.

In the embodiment shown in fig. 17 to fig. 20, the gate bias voltage VG is provided to the field effect transistor 1111 of the amplifier through the gate bias power source terminal VG, and the drain bias voltage VD is provided to the field effect transistor 1111 of the amplifier through the drain bias power source terminal VD, so as to maintain the stable operation of the field effect transistor 1111. Radio frequency signals are input through a radio frequency signal input end RFIN, pass through a grid matching circuit 130, drive a grid of a field effect tube 1111 in the amplifier, are amplified through the field effect tube 1111, and respectively output two amplification signals through two branches of a drain matching circuit 112 and output two amplification signals through a source matching circuit 113; two amplified signals output by the amplifier drain matching circuit 112 and two amplified signals output by the source matching circuit 113 are respectively synthesized, and the two paths of synthesized amplified signals are respectively output by a 5 th radio frequency signal output end RFOUT _5 and a 6 th radio frequency signal output end RFOUT _6 after passing through a 1 st impedance transformation circuit 150 _1and a2 nd impedance transformation circuit 150 _2respectively.

In the embodiment of the present application, another implementation of the gate bias circuit 160 and the source bias circuit 140 is provided, as shown in fig. 21, the gate bias circuit 160 is ground, that is, the second terminal of the seventh inductor L7 is directly grounded.

As shown in fig. 21, the 1 st source bias circuit 140_1 includes:

a 1 st sixth capacitor C6_1, wherein a first end of the 1 st sixth capacitor C6_1 is connected to a second end of the 1 st branch of the fifth inductive unit L5_1, and a second end of the 1 st sixth capacitor C6_1 is grounded;

a 1 st first resistor R1_1, wherein a first end of the 1 st first resistor R1_1 is connected to a second end of the 1 st branch of the fifth inductive unit L5_1, and a second end of the 1 st first resistor R1_1 is grounded.

In the embodiment of the present application, the 1 st sixth capacitor C6_1 is used to couple the signal output by the source of the field effect transistor 1111 and passing through the inductor to ground, so as to ideally form a radio frequency signal and reduce the energy loss of the source circuit.

In this embodiment, the 1 st resistor R1_1 is used to raise the source voltage of the fet 1111, so that the gate-to-source voltage of the fet 1111 is negative, thereby maintaining the normal operation of the amplifier.

In the embodiment shown in fig. 21, the 1 st drain bias circuit 120\ u 1 includes:

The 2 nd drain bias circuit 120\ u 2 includes:

In the embodiment of fig. 21, when source bias circuit 140 u 1 of embodiment 1 is at ground, the amplifier does not include a low coupled inductor pair. In other embodiments of the present application, a low-coupling inductor pair may be included, which includes a first inductor L1_1 of the 1 st branch and a second inductor L2_1 of the 1 st branch with opposite directions of the induced magnetic field, and a low-coupling inductor pair including an eighth inductor L8_2 of the 2 nd branch and a ninth inductor L9_2 of the 2 nd branch with opposite directions of the induced magnetic field, as shown in fig. 22; or may include only the low-coupling inductor pair composed of the sixth inductor L6 and the seventh inductor L7 with opposite directions of the induced magnetic field, as shown in fig. 23; or the inductor pair may include two pairs of low-coupling inductor pairs including a first inductor L1_1 of the 1 st branch and a second inductor L2_1 of the 1 st branch, which have opposite directions of the induced magnetic field, a pair of low-coupling inductors including an eighth inductor L8_2 of the 2 nd branch and a ninth inductor L9_2 of the 2 nd branch, which have opposite directions of the induced magnetic field, and a pair of low-coupling inductors including a sixth inductor L6 and a seventh inductor L7, which have opposite directions of the induced magnetic field, as shown in fig. 24.

In the embodiment shown in fig. 21 to fig. 24, a drain bias voltage is provided to the fet 1111 through the drain bias power source terminal VD, and at this time, a drain-source current of the fet 1111 flows through the resistor R1_1 in the source bias circuit 140, so as to raise the source potential of the fet 1111, so that the gate-source voltage of the fet 1111 is negative, and the normal operation of the fet 1111 is maintained. Radio frequency signals are input through a radio frequency signal input end RFIN, pass through a grid matching circuit 130, drive a grid of a field effect tube 1111 in the amplifier, are amplified through the field effect tube 1111, and respectively output two amplification signals through two branches of a drain matching circuit 112 and output two amplification signals through a source matching circuit 113; two amplified signals output by the amplifier drain matching circuit 112 and two amplified signals output by the source matching circuit 113 are respectively synthesized, and the two paths of synthesized amplified signals are respectively output by a 5 th radio frequency signal output end RFOUT _5 and a 6 th radio frequency signal output end RFOUT _6 after passing through a 1 st impedance transformation circuit 150 _1and a2 nd impedance transformation circuit 150 _2respectively.

In the embodiment of M =1 shown in fig. 21 to 24, the 1 st source bias circuit 140 _1includes one resistor and one capacitor, and in other embodiments of the present application, M >1, includes a plurality of source bias circuits, each of which must include one capacitor, but at least one of the plurality of source bias circuits includes a resistor.

In the embodiment of the present application, any inductive unit is one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line. In the embodiment of the present application, any one of the plurality of inductive units may be one of an inductor, a microstrip line, or a combination of an inductor and a microstrip line, or a part of the inductive units are inductors, a part of the inductive units are microstrip lines, and a part of the inductive units are a combination of inductors and microstrip lines; or all of them are inductors, or all of them are microstrip lines, or all of them are a combination of inductors and microstrip lines, and are not described herein again.

In the embodiment of the present application, the inductive units forming the low-coupling inductor pair can only be two inductors, and are not described herein again.

In the embodiment of the application, the power supply bias modes of the amplifier comprise single power supply self-bias, double power supply bias and triple power supply bias. Single power self-bias means that only the drain bias voltage VD is supplied from the outside as shown in fig. 21 to 24; the dual power bias means that a drain bias voltage VD and a gate bias voltage VG are supplied from the outside, as shown in fig. 17 to 20; the three-power bias means that a gate bias voltage VD, a gate bias voltage VG, and a source bias voltage VS are supplied from the outside, as shown in fig. 11 to 15. The single power supply is simple in self-bias power supply, the double power supply can exert better power performance, the three power supply biases are beneficial to energy conservation, and a power supply bias mode can be configured according to practical application. The power supply bias mode of the embodiment of the present application may also be used in other circuits, and is not described herein again.

In other embodiments of the present application, as shown in fig. 25, the three-port transistor 111 may be a transistor 1112, and then the first electrode of the transistor 111 is a collector (C electrode), the second electrode is an emitter (E electrode), and the third electrode is a base (B electrode), in this case, the first electrode matching circuit 112 is a collector matching circuit 112, the second electrode matching circuit 113 is an emitter matching circuit 113, the third electrode matching circuit 130 is a base matching circuit 130, the first electrode biasing circuit 120 is a collector biasing circuit 120, the second electrode biasing circuit 140 is an emitter biasing circuit 140, the third electrode biasing circuit 160 is a base biasing circuit 160, and the amplifier further includes an impedance transformation circuit 150.

The circuit shown in fig. 25 is an application scenario when M =1, and in this case, based on the principle of amplification of radio frequency signals, the circuit can be decomposed into two amplifiers, namely a common emitter amplifier and an emitter follower amplifier. In this case, different power supply modes are possible according to different bias modes.

The single power supply can be that a collector bias power supply end VC provides voltage VC for a collector, the collector bias power supply end VC provides current mirror power supply voltage, a current mirror generates base bias current IB, an emitter bias power supply end VE is grounded, and the collector voltage VC and the base current IB jointly provide bias for the triode; or the emitter bias power supply end VE supplies power (negative voltage), the emitter bias power supply end VE supplies power to the current mirror, the current mirror generates base currents IB, and the base currents VE and IB jointly provide bias for the triode (PNP) (VE and IB are not shown in the figure).

The dual power supply may provide a collector with a voltage VC from a collector bias supply terminal VC and a base current IB from a base bias supply terminal IB (IB not shown in the figure).

The three-source power supply is provided with a collector bias supply terminal VC providing a collector voltage VC, an emitter bias supply terminal VE providing an emitter voltage VE, and a base bias supply terminal IB providing a base current IB (VE and IB are not shown in the figure).

When the amplifier uses the transistor 1112, the amplified signals may be directly synthesized, as shown in fig. 25; or may be combined by a combining circuit (not shown), which will not be described in detail herein.

When the amplifier uses the transistor 1112, the working principle, the circuit configuration, the beneficial effects, and the like of the amplifier are the same as or similar to those of the above embodiment using the field effect transistor 1111, but some circuits may be adjusted according to the actual application scenario, and are not described herein again.

In the embodiment of the present application, as shown in fig. 5, the combining circuit 190 may be a coupler, a combiner with a phase shifting function, or the like, or may be other circuits that can combine radio frequency signals.

The amplified signal S _1 and the amplified signal S _3 are combined by the 1 st combining circuit 190_1, and enter the 1 st impedance transformation circuit 150_1, and the combined amplified signal is output from the 5 th rf signal output terminal RFOUT _ 5.

The amplified signal S _2 and the amplified signal S _4 are combined by the 2 nd combining circuit 190_2, and enter the 2 nd impedance transformation circuit 150_2, and the combined amplified signal is output from the 6 th rf signal output terminal RFOUT _6.

The 1 st synthesizing circuit 190_1 may combine the amplified signal S _1 and the amplified signal S _3 after a certain phase shift, and make the output signal enter the 1 st impedance transformation circuit 150_1; the 1 st combining circuit 190_1 may be configured to phase-shift only one of the amplified signal S _1 and the amplified signal S _3 and then combine the signals, and to cause the output signal to enter the 1 st impedance transforming circuit 150_1.

As described in the above embodiments, the phase shift of the amplified signal S _1 and/or the amplified signal S _3 by the 1 st combining circuit 190_1 is to make the phase difference between the two signals approach to 2n pi, where n is an integer, so that the two amplified signals of the amplifier can be combined and then the amplitudes are superimposed, so that the amplifier has higher gain.

Similarly, the 2 nd synthesizing circuit 190\ 2 shifts the phase of one or both of the amplified signal S _2 and the amplified signal S _4, which is not described in detail herein.

In this embodiment, the combining circuit 190 may implement phase shifting of the radio frequency signal, the combining circuit 190 may be further divided into three sub-circuits, the three sub-circuits may be integrated with the 1 st branch 112 _1of the first pole matching circuit 112, the 2 nd branch 112 _2of the first pole matching circuit 112, and the 1 st branch 113 _1of the second pole matching circuit 113, respectively, implement phase shifting of any one or more amplified signals of the amplified signals S _1, S _2, S _3, and S _4, and then combine the amplified signal S _1 and the amplified signal S _3, and combine the amplified signal S _2 and the amplified signal S _4; alternatively, the 1 st synthesizing circuit 190 _1may be integrated with the 1 st impedance transforming circuit 150_1, the 2 nd synthesizing circuit 190 _2may be integrated with the 2 nd impedance transforming circuit 150_2, and any one or more of the amplified signals S _1, S _2, S _3, and S _4 are phase shifted and synthesized in the 1 st impedance transforming circuit 150 _1and the 2 nd impedance transforming circuit 150_2, and S _1 and S _3 are synthesized, and S _2 and S _4 are synthesized.

The embodiment of the application provides an amplifier and a radio frequency chip, wherein the amplifier comprises a substrate and the amplifier on the substrate.

Still take M =1 and field effect transistor as an example for explanation. In the amplifier as described above, or the amplifier may include a low-coupling inductor pair including a first inductor L1_1 of the 1 st branch and a second inductor L2_1 of the 1 st branch, which induce magnetic fields in opposite directions, and a low-coupling inductor pair including an eighth inductor L8_2 of the 2 nd branch and a ninth inductor L9_2 of the 2 nd branch, which induce magnetic fields in opposite directions; or only a low-coupling inductor pair consisting of a sixth inductor L6 and a seventh inductor L7 with opposite induction magnetic field directions can be included; or the inductor pair may include two pairs of low-coupling inductors formed by the first inductor L1_1 of the 1 st branch and the second inductor L2_1 of the 1 st branch, which have opposite directions of the induced magnetic field, a low-coupling inductor pair formed by the eighth inductor L8_2 of the 2 nd branch and the ninth inductor L9_2 of the 2 nd branch, which have opposite directions of the induced magnetic field, and a low-coupling inductor pair formed by the sixth inductor L6 and the seventh inductor L7, which have opposite directions of the induced magnetic field. The specific structure is described in the above embodiments, and is not described herein again.

In the embodiment of the present application, the inductor in the low-coupling inductor pair may be a single-layer wiring spiral inductor or a multi-layer wiring spiral inductor.

When the inductor is excited by a signal, an induction magnetic field is generated, the induction magnetic field generates an induction electric field, and the induction electric field generates induction eddy current in a substrate of the chip, so that energy loss is generated.

The chip of the embodiment of the present application includes the above amplifier, and the amplifier may include a low-coupling inductor pair, for example, the 1 st branch first inductor L1_1 and the 1 st branch second inductor L2_1. The first inductance L1_1 of the 1 st branch and the second inductance L2_1 of the 1 st branch are low-coupling inductance pairs, the directions of the induction magnetic fields of the first inductance L1_1 of the 1 st branch and the second inductance L2_1 of the 1 st branch are opposite, so that the directions of the induction electric field generated by the induction magnetic field of the first inductance L1_1 of the 1 st branch and the induction electric field generated by the induction magnetic field of the second inductance L2_1 of the 1 st branch are also opposite, the directions of the induction eddy currents generated by the two opposite induction electric fields are opposite, the induction eddy currents with opposite directions can be partially offset, so that the induction eddy currents are reduced, the generated energy loss is reduced, and the energy loss of the chip matching network is reduced.

In the embodiment of the present application, in the drain matching circuit 112 of the amplifying circuit in the chip, the directions of the induced magnetic fields of the first inductor L1_1 of the 1 st branch and the second inductor L2_1 of the 1 st branch are opposite, so that the induced eddy current in the substrate can be partially offset, and the energy loss can be reduced. In addition, the physical distance between the first inductor L1_1 of the 1 st branch and the second inductor L2_1 of the 1 st branch can be closer, so that the size of a chip can be reduced, and the cost can be reduced.

In the chip of the embodiment of the present application, the effect of the low-coupling inductor pair formed by other inductor pairs with opposite induction magnetic fields is as described above, and is not described herein again.

As shown in fig. 26, the radio frequency chip 2000 may include an amplifier 2001, where the amplifier 2001 may be any embodiment of the amplifier described above. One amplifier 2001 may be used alone, or a plurality of amplifiers 2001 may be used in combination. In one example, the radio frequency chip 2000 may include one or more amplifiers 2001.

The embodiment of the present application further provides an electronic device, where the electronic device includes the radio frequency chip, and the radio frequency chip including the amplifier embodiment of the present application can be used in an electronic device.

As shown in fig. 27, the electronic device 3000 includes the rf chip 2000 shown in fig. 26. The electronic device 3000 may be a wireless device or any other electronic device that may use an amplifier.

A wireless device may be a User Equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a base station, etc. The wireless device may also be a cellular phone, a smart phone, a tablet, a wireless modem, a Personal Digital Assistant (PDA), a handheld device, a laptop, a smartbook, a netbook, a cordless phone, a Wireless Local Loop (WLL) station, a bluetooth device, etc. The wireless device may be capable of communicating with a wireless communication system, may be capable of receiving signals from a broadcast station, signals from one or more satellites, and the like. The wireless device may support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter wave, etc.).

The embodiment of the application provides an amplifier, a radio frequency chip and an electronic device, which can output a plurality of paths of amplified signals, synthesize each two paths of amplified signals in the plurality of paths of amplified signals according to a preset rule, and output the synthesized amplified signals, so that the plurality of paths of synthesized amplified signals can be output, and the functional density of the amplifier is improved; in addition, the gain of the amplifier can be superposed, so that the amplifier has higher gain; in the embodiment of the application, the amplifier only comprises one three-port transistor, and the power consumption of the three-port transistor determines the power consumption of the amplifier, so that the amplifier realizes the gain superposition of a multi-path amplifier without the power consumption being multiplied, and the power-to-power consumption ratio of the amplifier is improved.

In the embodiments of the present application, functional units with the same reference numbers in the drawings have the same or similar functions, and are not described herein again.

The amplifiers in the embodiments of the present application may be used independently, or may be used in a cascade of multiple stages, or may be used in a cascade with other circuits with various functions; the radio frequency chip of the embodiment of the present application may also include an independently used amplifier, or may include a plurality of amplifiers used in combination, or may include a plurality of independently used amplifiers; the rf chip of the embodiment of the present application may be used independently, or may be used in combination with multiple stages, or may be used in combination with other chips/circuits with various functions.

In the embodiment of the present application, the bias circuits of the respective poles of the three-port transistor respectively include multiple implementation forms, and these implementation forms may also be applied to other circuits, or may be combined with other implementation forms, or combined with each other, and are not described herein again.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to requirements, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to corresponding processes in the context, which are not described herein again.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described or illustrated in detail in a certain embodiment, reference may be made to related descriptions in other embodiments.

The units or modules described as separate parts may or may not be physically separate, and parts displayed as units or modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of functional units. Some or all of the units or modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, each functional unit or module in each embodiment of the present application may be integrated into one chip unit, or each unit or module may exist alone physically, or two or more units or modules are integrated into one unit.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An amplifier, characterized in that the amplifier comprises:

a three-port transistor including a first pole, a second pole, and a third pole, the three-port transistor being configured to receive a radio frequency signal to be amplified from the third pole of the three-port transistor, amplify the radio frequency signal to be amplified, output an anti-phase amplified signal from the first pole of the three-port transistor, and output an in-phase amplified signal from the second pole of the three-port transistor;

a first pole matching circuit comprising 2M branches,

the first end of the 2i-1 th branch of the first pole matching circuit is connected with the first pole of the three-port transistor, the second end of the 2i-1 th branch of the first pole matching circuit is connected with the 2i-1 radio frequency signal output end,

the 2i-1 branch of the first pole matching circuit is used for matching the impedance of the first pole of the three-port transistor to a 2i-1 target impedance, the 2i-1 target impedance is the output impedance of a 2i-1 radio frequency signal output end, the 2i-1 branch of the first pole matching circuit is also used for transmitting the inverted amplified signal to the 2i-1 radio frequency signal output end to become a 2i-1 amplified signal,

a second pole matching circuit, wherein the second pole matching circuit comprises M branches, a first end of an ith branch of the second pole matching circuit is connected with a second pole of the three-port crystal, a second end of the ith branch of the second pole matching circuit is connected with a 2M +2i-1 radio frequency signal output end, a third end of the ith branch of the second pole matching circuit is connected with a 2M +2i radio frequency signal output end,

2. The amplifier of claim 1, wherein the 2i-1 amplified signal is combined with the 2M +2i-1 amplified signal, the 2i amplified signal is combined with the 2M +2i amplified signal,

3. The amplifier of claim 2, wherein the 2i-1 amplified signal is combined with the 2m +2i-1 amplified signal, and the 2i amplified signal is combined with the 2m +2i amplified signal, comprising:

4. The amplifier of claim 3, further comprising:

2M impedance transformation circuits are arranged in the circuit,

the first end of the 2i-1 impedance transformation circuit is connected with the 2i-1 radio frequency signal output end, and the second end of the 2i-1 impedance transformation circuit is connected with the 4M +2i-1 radio frequency signal output end;

the first end of the 2i impedance transformation circuit is connected with the 2i radio frequency signal output end, and the second end of the 2i impedance transformation circuit is connected with the 4M +2i radio frequency signal output end;

5. The amplifier of claim 2, wherein the amplifier further comprises 2M combining circuits,

the 2i-1 radio frequency signal output end is connected with the first end of the 2i-1 synthesis circuit, and the 2M +2i-1 radio frequency signal output end is connected with the second end of the 2i-1 synthesis circuit, so that the 2i-1 amplified signal and the 2M +2i-1 amplified signal are synthesized;

6. The amplifier of claim 5, further comprising:

2M impedance transformation circuits;

the first end of the 2i-1 impedance conversion circuit is connected with the third end of the 2i-1 synthesis circuit, and the second end of the 2i-1 impedance conversion circuit is connected with the radio-frequency signal output end of 4M + 2i-1;

7. The amplifier according to any one of claims 1 to 6, further comprising:

a third pole matching circuit, a first end of the third pole matching circuit being connected to the radio frequency signal input terminal, a second end of the third pole matching circuit being connected to a third pole of the three-port transistor;

2M first pole bias circuits, the first end of the 2i-1 st pole bias circuit is connected with the 2i-1 st pole bias power supply terminal,

the first end of the 2i first electrode bias circuit is connected with a 2i first electrode bias power supply end;

8. The amplifier of claim 7, wherein the 2i-1 branch of the first pole matching circuit comprises:

a 2i-1 branch third inductive unit, a first end of the 2i-1 branch third inductive unit being connected to a first end of the 2i-1 branch first inductive unit, a second end of the 2i-1 branch third inductive unit being connected to a 2i-1 radio frequency signal output end;

the 2i branch of the first polar matching circuit includes:

9. The amplifier of claim 8, wherein the ith branch of the second pole matching circuit comprises:

the first end of the fourth sensing unit of the ith branch is connected with the second pole of the three-port transistor;

a fifth capacitor of the ith branch, wherein a first end of the fifth capacitor of the ith branch is connected with a second end of the fourth inductive unit of the ith branch, and a second end of the fifth capacitor of the ith branch is connected with the 2M +2i radio frequency signal output end;

10. The amplifier of claim 9, wherein the third pole matching circuit comprises:

11. The amplifier of claim 10, wherein the 2i-1 st branch first inductive unit and the 2i-1 st branch second inductive unit are inductive pairs with opposite inductive magnetic fields, and the 2i branch eighth inductive unit and the 2i branch ninth inductive unit are inductive pairs with opposite inductive magnetic fields; and/or the presence of a gas in the atmosphere,

12. The amplifier of claim 10 or 11, wherein the third pole bias circuit comprises:

13. The amplifier of claim 12, wherein the ith second pole bias circuit comprises:

14. The amplifier of claim 12, wherein the ith second pole bias circuit is ground, wherein i =1 \ 8230 \8230:/\ 8230, M, i is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.

15. The amplifier of claim 10 or 11, wherein the third pole bias circuit is ground.

16. The amplifier of claim 15, wherein the ith second pole bias circuit comprises:

an ith sixth capacitor, a first end of the ith sixth capacitor is connected to the second end of the fifth inductive unit of the ith branch, and a second end of the ith sixth capacitor is grounded;

an ith first resistor, a first end of the ith first resistor being connected to the second end of the fifth inductive unit of the ith branch, and a second end of the ith first resistor being grounded;

17. The amplifier of claim 7, wherein the 2i-1 first pole bias circuit comprises:

the 2 i-th first pole bias circuit includes:

18. A radio frequency chip, characterized in that it comprises a substrate, and on said substrate an amplifier according to any of claims 1 to 17.

19. An electronic device comprising the radio frequency chip of claim 18.