CN217606027U

CN217606027U - Universal chip verification system

Info

Publication number: CN217606027U
Application number: CN202221065784.2U
Authority: CN
Inventors: 黄俊伟; 李晋; 王荣丰; 杜鹰; 霍旭东; 胡波
Original assignee: Chengdu Sunway Technology Co ltd
Current assignee: Chengdu Sunway Technology Co ltd
Priority date: 2022-05-06
Filing date: 2022-05-06
Publication date: 2022-10-18
Anticipated expiration: 2032-05-06

Abstract

The utility model relates to a general chip verification system, including host computer, test mother board, measured chip daughter board and communication module, the test mother board passes through communication module and is connected with the host computer, and the test mother board is connected with measured chip daughter board, and measured chip daughter board is connected with the chip that awaits measuring; the testing mother board comprises a first connecting circuit board, a DSP module and an FPGA module, the first connecting circuit board is respectively connected with the DSP module and the tested chip daughter board, the first connecting circuit board is connected with an upper computer through a communication module, and the DSP module is connected with the FPGA module. The problem that the same type of verification system cannot be used for verification testing when the chips come from different manufacturers is solved.

Description

Universal chip verification system

Technical Field

The utility model relates to a chip test technical field especially relates to a general chip verification system.

Background

In the aspect of chip verification, each chip development unit designs a verification system for each chip, and the verification system is used for performing functional test on the chip, although the conventional verification system can test the general function of the chip, the types of the chips are various, and the functions of the chips have difference, for example, some chips need to test the implementation, integrity, electrical property and the like of input and output data, but the functions are not all required to be tested, so that the universality of chip verification cannot be achieved, and when the chips come from different manufacturers, the verification test cannot be performed by using the same verification system.

SUMMERY OF THE UTILITY MODEL

In order to overcome the problem that can't use same money verification system to verify the test when the chip comes from different producers, the utility model provides a general chip verification system.

In order to solve the technical problem, the utility model provides a general chip verification system, which comprises an upper computer, a testing mother board, a tested chip daughter board and a communication module, wherein the testing mother board is connected with the upper computer through the communication module, the testing mother board is connected with the tested chip daughter board, and the tested chip daughter board is connected with a chip to be tested;

the test motherboard comprises a first connecting circuit board, a DSP module and an FPGA module, the first connecting circuit board is respectively connected with the DSP module and the tested chip daughter board, the first connecting circuit board is connected with an upper computer through a communication module, the DSP module is connected with the FPGA module, and the FPGA module is an editing device for running an FPGA firmware program.

The utility model provides a pair of general chip verification system's beneficial effect is: when the FPGA firmware program is used, the FPGA module loaded with the FPGA firmware program can carry out differential test on the chips to be tested, and the problem that the same type of verification system cannot be used for verification test when the chips come from different manufacturers is solved.

On the basis of the technical scheme, the utility model discloses a general chip verification system can also do following improvement.

Further, the DSP module adopts a microprocessor with the model number of xilinx ZC 702.

The beneficial effect of adopting the above further scheme is: the microprocessor with the model number of xilinx ZC702 is directly used for executing the test instruction sent by the upper computer, the structure is simple, and the execution capacity of the test instruction is strong.

Further, the FPGA module adopts an editing device with the model number of xilinxXC7K 325T.

The beneficial effect of adopting the above further scheme is: by adopting the editing device with the model number of xilinxXC7K325T, a user can load a needed FPGA firmware program according to actual requirements so as to carry out diversified difference tests.

Furthermore, the chip daughter board to be tested comprises a chip placing board and a second connecting circuit board, and the second connecting circuit board is connected with the test mother board.

The beneficial effect of adopting the further scheme is that: during the use, the chip that awaits measuring directly places on the chip places the board, and the chip that awaits measuring just can be connected with second connecting circuit board, and the chip that awaits measuring can be connected with the DSP module through second connecting circuit board, realizes the test of the chip that awaits measuring.

Furthermore, the system also comprises a power supply instrument, and the test motherboard is connected with the power supply instrument.

The beneficial effect of adopting the further scheme is that: the power supply instrument supplies power to the system and the chip to be tested.

Further, the upper computer is at least one of a computer and a mobile phone.

The beneficial effect of adopting the further scheme is that: the user can select a computer or a mobile phone as the upper computer according to actual requirements.

Further, the communication module is at least one of ethernet, 4G, 5G or WIFI.

The beneficial effect of adopting the above further scheme is: the user can select the communication mode according to actual requirements.

Furthermore, the system also comprises a measuring instrument module, and the measuring instrument module is connected with the test motherboard.

The beneficial effect of adopting the further scheme is that: signals output by the chip to be tested during verification testing are drawn into a oscillogram through the measuring instrument module, so that a user can observe the verification test result of the chip to be tested conveniently.

Drawings

To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be further described with reference to the accompanying drawings and embodiments.

Fig. 1 is a schematic structural diagram of a universal chip verification system according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a general chip verification system according to an embodiment of the present invention in another operating state.

Reference numerals are as follows: the device comprises an upper computer 1, a communication module 2, a first connecting circuit board 3, a DSP module 4, a tested chip daughter board 5, an FPGA module 6, a chip placing board 7, a second connecting circuit board 8 and a chip to be tested 9.

Detailed Description

The following examples are further illustrative and supplementary to the present invention and do not constitute any limitation to the present invention.

The following describes a general chip verification system according to an embodiment of the present invention with reference to the drawings.

As shown in fig. 1, the utility model provides a general chip verification system, including host computer 1, test mother board, chip daughter board 5 and communication module 2 under test, the test mother board passes through communication module 2 and is connected with host computer 1, and the test mother board is connected with chip daughter board 5 under test, and chip daughter board 5 under test is connected with chip 9 under test;

the testing motherboard comprises a first connecting circuit board 3, a DSP module 4 and an FPGA module 6, the first connecting circuit board 3 is respectively connected with the DSP module 4 and a tested chip daughter board 5, the first connecting circuit board 3 is connected with the upper computer 1 through a communication module 2, the DSP module 4 is connected with the FPGA module 6, and the FPGA module 6 is an editing device for running an FPGA firmware program.

When the test platform is used, a chip 9 to be tested is connected to a chip daughter board 5 to be tested, a host computer 1 sends a test instruction to a DSP module 4 on a test mother board through a communication module 2, a DSP template is connected with the chip daughter board 5 to be tested through a first connecting circuit board 3 so as to be connected with the chip 9 to be tested, the DSP module 4 carries out universality test on the chip 9 to be tested according to the test instruction, when the chip needs difference test, a user can download an FPGA firmware program from a test sequence file of a chip 9 company to be tested according to the type of the chip 9 to be tested, the FPGA firmware program contains the test instruction of the company for the difference test of the chip to be tested, the user sends the FPGA firmware program to the DSP module 4 on the test mother board through the host computer, the DSP module 4 calls an FPGA module 6 to load the FPGA firmware program, the FPGA module 6 loaded with the FPGA firmware program can carry out the difference test on the chip 9 to be tested, and the problem that the test system cannot be used for test verification when the chip comes from different manufacturers is solved.

The processing processes of the upper computer 1, the test mother board, the chip daughter board 5 to be tested and the communication module 2 are all the prior art, and refer to the following specifically.

The difference test means that functions of different chips have differences, for example, some chips need to test the feasibility, integrity, electrical property and the like of input and output data, and not all the chips need to be tested, so that the FPGA module 6 needs to be used for the difference test of the chips.

Optionally, the upper computer 1 is at least one of a computer and a mobile phone, in this embodiment, the upper computer 1 is preset with chip verification software, the chip verification software may adopt chip verification software commonly used in the market, for example, apps such as eidolon test, after the chip verification software is run in the upper computer 1, a "control identifier" may be displayed on a display interface of the upper computer 1, a user triggers the control identifier to generate a test instruction, the control identifier may be a plug-in, and may be displayed in a form of characters or shapes, after the user triggers the control identifier, the generated test instruction is sent to a test motherboard, and the DSP module 4 executes a verification test function of the chip to be tested 9 according to the test instruction.

Optionally, the DSP module 4 employs a microprocessor of a model xilinx ZC702, which has conventional functions of sending related instructions and invoking related modules.

Optionally, the FPGA module 6 is an editing device with a model number of xilinx XC7K325T, in this embodiment, an FPGA firmware program needs to be prestored in the upper computer 1, the prestored FPGA firmware program is directly downloaded from a test sequence file of a corresponding company, when a difference test needs to be performed on the chip 9 to be tested, the upper computer 1 sends the FPGA firmware program to the DSP module 4, the DSP module 4 sends the FPGA firmware program to the FPGA module 6, the FPGA module 6 completes the loading of the FPGA firmware program, and the FPGA module 6 performs the difference test on the chip 9 to be tested after the FPGA firmware program is loaded.

Optionally, as shown in fig. 2, the chip daughter board 5 to be tested includes a chip placing board 7 and a second connection circuit board 8, and the second connection circuit board 8 is connected to the test motherboard.

The shape and size of the chip placement board 7 can be customized according to actual needs.

Optionally, the system further includes a power supply instrument, and the test motherboard is connected to the power supply instrument.

Optionally, the communication module 2 is at least one of ethernet, 4G, 5G, or WIFI.

Optionally, the system further includes a measurement instrument module, the measurement instrument module is connected to the test motherboard, and the measurement instrument module is configured to draw a waveform according to a signal output by the chip 9 to be tested during the verification test, for example, an intelligent oscilloscope or the like.

Optionally, the connection mode among the test motherboard, the power supply instrument, and the chip daughter board 5 to be tested may be as follows:

the communication pin, the power pin, the first test pin, the processor pin and the level conversion pin are preset on the first connecting circuit board 3, the first test pin is preset on the second circuit board, the communication module 2 is connected with the first connecting circuit board 3 through the communication pin, the power instrument is connected with the first connecting circuit board 3 through the power pin, the DSP module 4 is connected with the first connecting circuit board 3 through the processor pin, and the first test pin is connected with the second test pin to realize the connection of the first connecting circuit board 3 and the second connecting circuit board 8.

In addition, a selectmap interface and a Bram interface are preset in the DSP module 4, and the DSP module 4 is connected with the FPGA module 6 through the selectmap interface, so that the FPGA firmware program is transmitted to the FPGA module 6; the DSP module 4 is connected with the FPGA module 6 through a Bram interface, so that data interaction between the DSP module 4 and the FPGA module 6 is realized.

The working principle is as follows: when the device is used, a chip 9 to be tested is placed on the chip placing board 7, the upper computer 1 generates a test instruction according to a test sequence file of the chip 9 to be tested, the test instruction is sent to the DSP module 4 through the communication module 2, the DSP module 4 carries out universal functional test on the chip 9 to be tested, the DSP returns a test result to the upper computer 1 or draws a waveform diagram through the measuring instrument module, when difference test is needed, the upper computer 1 sends a preset corresponding FPGA firmware program to the DSP module 4 through the communication module 2, the DSP module 4 sends the FPGA firmware program to the FPGA module 6, the FPGA module 6 carries out difference test on the chip 9 to be tested after the FPGA firmware program is loaded and completed, the FPGA module 6 returns the test result to the DSP module 4, and the DSP module 4 returns the test result to the upper computer 1 through the communication module 2 or draws the waveform diagram through the measuring instrument module.

In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.

Although embodiments of the present invention have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art without departing from the scope of the present invention.

Claims

1. A universal chip verification system, comprising: the device comprises an upper computer (1), a testing mother board, a tested chip daughter board (5) and a communication module (2), wherein the testing mother board is connected with the upper computer (1) through the communication module (2), the testing mother board is connected with the tested chip daughter board (5), and the tested chip daughter board (5) is connected with a chip (9) to be tested;

the test motherboard comprises a first connecting circuit board (3), a DSP module (4) and an FPGA module (6), wherein the first connecting circuit board (3) is respectively connected with the DSP module (4) and the tested chip daughter board (5), the first connecting circuit board (3) is connected with the upper computer (1) through the communication module (2), the DSP module (4) is connected with the FPGA module (6), and the FPGA module (6) is an editing device for running an FPGA firmware program.

2. The universal chip verification system according to claim 1, wherein: the DSP module (4) adopts a microprocessor with the model number of xilinx ZC 702.

3. The universal chip verification system according to claim 1, wherein: the FPGA module (6) adopts an editing device with the model number of xilinxXC7K 325T.

4. The universal chip verification system according to claim 1, wherein: the tested chip daughter board (5) comprises a chip placing board (7) and a second connecting circuit board (8), and the second connecting circuit board (8) is connected with the testing mother board.

5. The universal chip verification system according to claim 1, wherein: the system also comprises a power supply instrument, and the test motherboard is connected with the power supply instrument.

6. The universal chip verification system according to claim 1, wherein: the upper computer (1) is at least one of a computer and a mobile phone.

7. The universal chip verification system according to claim 1, wherein: the communication module (2) is at least one of Ethernet, 4G, 5G or WIFI.

8. The universal chip verification system according to claim 1, wherein: the system also comprises a measuring instrument module, and the measuring instrument module is connected with the test motherboard.