CN217404857U - Watchdog circuit and electronic equipment - Google Patents

Abstract

The utility model belongs to the field of watchdog circuits, a watchdog circuit and electronic equipment are provided, the watchdog circuit includes a timing circuit, level switching circuit and level holding circuit, timing circuit is connected with master control circuit, a reset signal is generated when the reset signal that master control circuit provided is not received to be used for in the power input end of timing circuit does not receive first voltage signal or in the time interval of predetermineeing, level switching circuit connects timing circuit, a second switch control signal is exported to be used for only receiving the reset signal of timing circuit output, level holding circuit is connected with level switching circuit, a third voltage signal and second switch control signal when the power input end of level holding circuit input are received, export the hold control signal and give master control circuit, so that master control circuit normally works, the watchdog circuit that this application provided has solved master control circuit and has still sent reset signal to master control circuit when burning record and make MCU unable normal work to master control circuit watchdog circuit The problem of burning.

Description

Watchdog circuit and electronic equipment

Technical Field

The application belongs to the field of watchdog circuits, and particularly relates to a watchdog circuit and electronic equipment.

Background

The watchdog circuit is a timer circuit and functions to prevent a program in a Micro Controller Unit (MCU) from dead-cycling or running out. The watchdog circuit generally has an input terminal, and the input terminal of the watchdog circuit is connected to the MCU. When the MCU normally works, a clear signal can be output to the input end of the watchdog circuit at intervals, and when the MCU exceeds the specified time and does not output the clear signal to the watchdog circuit (generally when a program runs away), the watchdog circuit can output a reset signal to the MCU, so that the MCU is reset, and the MCU is prevented from being halted.

However, when the MCU is programming, the watchdog circuit sends a reset signal to the MCU due to the inability to send a clear signal to the watchdog circuit, so that the MCU cannot continue programming. Therefore, the watchdog circuit has the problem that when the MCU is burned, the watchdog circuit still sends a reset signal to the MCU so that the MCU cannot be burned normally.

SUMMERY OF THE UTILITY MODEL

An object of the application is to provide a watchdog circuit and electronic equipment, aim at solving master control circuit when burning, watchdog circuit still sends reset signal to master control circuit and makes the unable problem of normally burning of master control circuit.

The watchdog circuit is connected with a main control circuit, comprises a timing circuit, is connected with the main control circuit, and is used for generating a reset signal when a power supply input end of the timing circuit does not receive a first voltage signal or a reset signal provided by the main control circuit is not received within a preset time interval;

the level switching circuit is connected with the timing circuit and used for outputting a first switch control signal when receiving the reset signal and a first voltage signal input by a power supply input end of the level switching circuit, and outputting a second switch control signal when only receiving the reset signal output by the timing circuit;

and the level holding circuit is connected with the level conversion circuit, and is used for outputting a reset control signal to the main control circuit to stop the main control circuit when receiving a second voltage signal and the first switch control signal which are input by a power supply input end of the level holding circuit, and is also used for outputting a holding control signal to the main control circuit to enable the main control circuit to normally work when receiving a third voltage signal and the second switch control signal which are input by the power supply input end of the level holding circuit.

In one embodiment, the watchdog circuit further comprises:

the isolating circuit is arranged between the timing circuit and the main control circuit, is used for transmitting the zero clearing signal to the timing circuit when receiving the zero clearing signal output by the main control circuit, and is also used for isolating the non-zero clearing signal sent by the main control circuit.

In one embodiment, the timing circuit includes: the watchdog circuit comprises a watchdog chip, a first resistor, a second resistor and a first capacitor; wherein the content of the first and second substances,

a first end of the first resistor receives the first voltage signal, and a second end of the first resistor is connected with a power supply input end of the watchdog chip; the first end of the first capacitor is grounded, and the second end of the first capacitor is connected with the power supply input end of the watchdog chip; the zero clearing signal input end of the watchdog chip is connected with the main control circuit; the second resistor is connected between the power supply input end of the watchdog chip and the zero clearing input end of the watchdog chip.

In one embodiment, the level shift circuit comprises a third resistor, a fourth resistor, a fifth resistor, a second capacitor and a first switch tube; wherein the content of the first and second substances,

the first end of the third resistor is connected with the output end of the timing circuit, and the second end of the third resistor is connected with the control end of the first switching tube; the first end of the first switch tube is connected with the level holding circuit, and the second end of the first switch tube is grounded; the fourth resistor and the second capacitor are respectively connected between the control end of the first switch tube and the second end of the first switch tube; the first end of the fifth resistor is connected with the first end of the first switch tube, and the second end of the fifth resistor is connected with the power supply input end of the level conversion circuit.

In one embodiment, the level holding circuit includes:

a receiving unit, configured to receive the second voltage signal or the third voltage signal;

the switch unit is connected with the level conversion circuit and used for outputting a first control signal when receiving a first switch control signal of the level conversion circuit; the first switch is used for switching the level conversion circuit to a first switch control signal;

and the level holding unit is respectively connected with the receiving unit and the switching unit, and is used for outputting the reset control signal when receiving the second voltage signal and the first control signal and outputting the holding control signal when receiving the third voltage signal and the second control signal.

In one embodiment, the switch unit comprises a sixth resistor, a seventh resistor, a third capacitor and a second switch tube; wherein the content of the first and second substances,

the sixth resistor and the third capacitor are respectively connected between the control end and the second end of the second switching tube; the first end of the seventh resistor is connected with the control end of the second switching tube, and the second end of the seventh resistor is connected with the output end of the level conversion circuit; the first end of the second switch tube is connected with the level holding unit, and the second end of the second switch tube is grounded.

In one embodiment, the level holding unit includes an eighth resistor and a fourth capacitor; the first end of the eighth resistor is connected to the receiving unit, the second end of the eighth resistor and the first end of the fourth capacitor are connected to the main control circuit, and the second end of the fourth capacitor is grounded.

In one embodiment, the watchdog circuit further comprises:

the first power supply circuit is connected with the level conversion circuit, the timing circuit and the power supply and is used for converting the power supply voltage of the power supply into a first voltage signal and then outputting the first voltage signal to the timing circuit and the level conversion circuit;

the second power supply circuit is connected with the level holding circuit and the power supply, converts the power supply voltage of the power supply into a second voltage signal and outputs the second voltage signal to the level holding circuit;

and the third power supply circuit is connected with the level conversion circuit and used for receiving a third voltage signal and outputting the third voltage signal to the level holding circuit.

In one embodiment, the second power supply circuit comprises a first diode, a fifth capacitor, a sixth capacitor, a seventh capacitor and a first power management chip; wherein the content of the first and second substances,

the anode of the first diode is connected with the power supply, and the cathode of the first diode is connected with the voltage input end of the first power management chip; the first end of the fifth capacitor is connected with the voltage input end of the first power management chip, and the second end of the fifth capacitor is grounded; a first end of the sixth capacitor is connected with the noise bypass end of the first power management chip, and a second end of the sixth capacitor is grounded;

the voltage output end of the first power supply management chip is connected with the receiving unit;

and the first end of the seventh capacitor is connected with the voltage output end of the first power management chip, and the second end of the seventh capacitor is grounded.

The present application provides, in another aspect, an electronic device including the watchdog circuit described in any one of the above embodiments.

The embodiment of the application has the beneficial effects that: the watchdog circuit provided by the embodiment of the application comprises a timing circuit, a level conversion circuit and a level holding circuit, wherein the timing circuit is connected with a main control circuit and used for generating a reset signal when a power input end of the timing circuit does not receive a first voltage signal or a zero clearing signal provided by the main control circuit is not received within a preset time interval, the level conversion circuit is connected with the timing circuit and used for outputting a first switch control signal when receiving the reset signal and the first voltage signal input by the power input end of the level conversion circuit, outputting a second switch control signal when only receiving the reset signal output by the timing circuit, the level holding circuit is connected with the level conversion circuit and used for outputting the reset control signal to the main control circuit when receiving the second voltage signal and the first switch control signal input by the power input end of the level holding circuit so as to stop the main control circuit, and the output circuit is also used for outputting a holding control signal to the main control circuit when receiving a third voltage signal and a second switch control signal which are input by the power supply input end of the level holding circuit so as to ensure that the main control circuit works normally. The watchdog circuit provided by the embodiment of the application can enable the master control circuit to receive the holding control signal output by the watchdog circuit in the burning process, and the problem that the MCU in the master control circuit cannot be burned normally because the watchdog circuit still sends the reset signal to the master control circuit when the master control circuit burns is solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a functional block diagram of a watchdog circuit provided in an embodiment of the present application;

FIG. 2 is a schematic circuit diagram of a timing circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic circuit diagram of a level shift circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic circuit diagram of a level holding circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic circuit diagram of a watchdog circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic circuit diagram of a second power supply circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic circuit diagram of a first power supply circuit according to an embodiment of the present disclosure.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

The watchdog circuit sets a preset time interval, which is the timing time of a timer inside the watchdog circuit. When the MCU works normally, the MCU outputs a zero clearing signal to the watchdog circuit within a preset time interval. And when the watchdog circuit receives the zero clearing signal in a preset time interval, clearing the timing time of the timer, timing again and outputting a keeping control signal to the MCU so as to ensure that the MCU keeps normal work. When the MCU is damaged or the program flies disorderly, a zero clearing signal cannot be sent to the watchdog circuit within a preset time interval, and at the moment, a timer in the watchdog circuit reaches the preset time and still does not receive the zero clearing signal sent by the MCU, so that the watchdog circuit outputs a reset signal to the MCU to reset the MCU.

However, in the process of burning the MCU, the MCU generally cannot send a clear signal to the watchdog circuit, so the watchdog circuit will continue to output a reset signal to the MCU to stop the MCU, and the MCU cannot burn after receiving the reset signal.

In order to solve the above problem, the present application provides, in one aspect, a watchdog circuit, which is shown in fig. 1 and includes a timing circuit 10, a level shift circuit 20, and a level holding circuit 30. The timing circuit 10 is connected to the main control circuit, and is configured to generate a reset signal Vr when the power input terminal of the timing circuit 10 does not receive the first voltage signal VDD1, or when the power input terminal does not receive the clear signal Ve provided by the main control circuit within a preset time interval. The level shift circuit 20 is connected to the timing circuit 10, and outputs a first switching control signal Vc1 when receiving the reset signal Vr and the first voltage signal VDD1 input to the power input terminal of the level shift circuit, and outputs a second switching control signal Vc2 when receiving only the reset signal Vr output from the timing circuit. The level holding circuit 30 is connected to the level converting circuit 20, and is configured to output a reset control signal Vrc to the main control circuit to stop the operation of the main control circuit when receiving the second voltage signal VDD2 and the first switch control signal Vc1 inputted from the power input terminal of the level holding circuit 30, and further to output a hold control signal Vhc to the main control circuit to enable the normal operation of the main control circuit when receiving the third voltage signal VDD3 and the second switch control signal Vc2 inputted from the power input terminal of the level holding circuit 30. It is understood that the first voltage signal VDD1 may be generated by an internal power source of the main control circuit, the second voltage signal VDD2 may be generated by an internal power source of the main control circuit, and the third voltage signal VDD3 is provided by a burning device when the main control circuit burns, where the main control circuit is usually built based on an MCU. In other embodiments, the first voltage signal VDD1 and the second voltage signal VDD2 may be provided by other power supplies.

Specifically, when the main control circuit is in a normal working state, the watchdog circuit normally receives the first voltage signal VDD1 and the second voltage signal VDD2, and when the MCU in the main control circuit fails (e.g., a program flies), the timing circuit 10 in the watchdog circuit does not receive the clear signal Ve output by the main control circuit within a preset time interval, at this time, the timing circuit 10 outputs the reset signal Vr to the level conversion circuit 20, and the level conversion circuit 20 generates the first switch control signal Vc1 when receiving the reset signal Vr and the first voltage signal VDD 1. When receiving the first switch control signal Vc1 and the second voltage signal VDD2, the level hold circuit 30 outputs a reset control signal Vrc to the main control circuit, so that the MCU in the main control circuit performs a reset operation.

The MCU of the main control circuit cannot output the clear signal Ve to the timing circuit 10 in the recording state, and the watchdog circuit only receives the third voltage signal VDD3 provided by the recording device. When the timing circuit 10 in the watchdog circuit does not receive the clear signal Ve output by the main control circuit and also does not receive the first voltage signal VDD1, the timing circuit 10 outputs the reset signal Vr to the level conversion circuit 20. When the level shift circuit 20 receives only the reset signal Vr without receiving the first voltage signal VDD1, the level shift circuit 10 outputs the second switch control signal Vc2 to the level hold circuit 30. When the level holding circuit 30 receives the third voltage signal VDD3 and the second switch control signal Vc2, the level holding circuit 30 outputs a holding control signal Vhc to the main control circuit, so that the MCU in the main control circuit performs burning normally.

Therefore, in the embodiment, the MCU in the main control circuit can only receive the hold control signal Vhc output from the watchdog circuit in the burning process, so that the problem that the watchdog circuit of the main control circuit still sends the reset signal Vrc to the main control circuit during burning, so that the MCU cannot burn normally is solved.

In an embodiment, as shown in fig. 2, the watchdog circuit further includes an isolation circuit 40, where the isolation circuit 40 is disposed between the timing circuit 10 and the main control circuit, and is configured to transmit the clear signal Ve to the timing circuit 10 when receiving the clear signal Ve output by the main control circuit, and is further configured to isolate other non-clear signals sent by the main control circuit.

Specifically, the isolation circuit 40 includes an anti-reverse diode Da, an anode of the anti-reverse diode Da is connected to the timing circuit 10, and a cathode of the anti-reverse diode Da is connected to the main control circuit and receives the clear signal Ve output by the main control circuit.

In one embodiment, referring to fig. 2, the timing circuit 10 includes a watchdog chip U1, a first resistor R1, a second resistor R2, and a first capacitor C1. A first end of the first resistor R1 is used as a power input end of the timing circuit 10 for receiving a first voltage signal VDD1, and a second end of the first resistor R1 is connected to a power input VCC of the watchdog chip U1. The first end of the first capacitor C1 is grounded GND, and the second end of the first capacitor C1 is connected to the power input VCC of the watchdog chip U1. A zero clearing signal input end WDI of the watchdog chip U1 is connected with the main control circuit; the second resistor R2 is connected between the power supply input VCC of the watchdog chip U1 and the zero clearing input WDI of the watchdog chip. The manual RESET terminal nMR of the watchdog chip U1 is connected to the second terminal of the first resistor R1, the ground terminal GND of the watchdog chip U1 is grounded, and the RESET output terminal RESET of the watchdog chip U1 is connected to the level shifter circuit 20. Specifically, a zero clearing signal input end WDI of the watchdog chip U1 is connected with the main control circuit through an anti-reverse diode Da.

Specifically, the watchdog chip U1 receives a first voltage signal VDD1 through a first resistor R1, the clear signal input terminal WDI receives the clear signal Ve, when the main control circuit normally operates, the main control circuit sends the clear signal Ve to the clear signal input terminal WDI of the watchdog chip U1 within a preset time interval, at this time, the watchdog chip U1 clears the timing time of the internal timer after receiving the clear signal Ve, restarts timing, and outputs a hold signal to enable the main control circuit to continue to normally operate. When the MCU in the main control circuit fails, it is impossible to send a clear signal Ve to the clear signal input terminal WDI of the watchdog chip U1 within a preset time interval, and after the timing time of the internal timer is reached, the watchdog chip U1 outputs a RESET signal Vr to the level shift circuit 20 through the RESET output terminal RESET. The first capacitor C1 is used to prevent external static electricity from damaging circuit components in the watchdog circuit.

In one embodiment, referring to fig. 3, the level shifter circuit includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a second capacitor C2, and a first switch transistor Q1. A first end of the third resistor R3 is connected to the output end of the timing circuit 10, and a second end of the third resistor R3 is connected to the control end of the first switch transistor Q1; a first end of the first switch tube Q1 is connected to the level holding circuit 30, and a second end of the first switch tube Q1 is grounded GND; the fourth capacitor R4 and the second capacitor C2 are respectively connected between the control terminal of the first switch transistor Q1 and the second terminal of the first switch transistor Q1. A first end of the fifth resistor R5 is connected to the first end of the first switch Q1, a second end of the fifth resistor R5 is connected to a power input terminal of the level shifter circuit 20, and the power input terminal of the level shifter circuit 20 is configured to receive the first voltage signal VDD 1.

Specifically, the first switch Q1 is connected to the output terminal of the timing circuit 10 through the third resistor R3, and receives the reset signal Vr sent by the timing circuit 10. As can be appreciated, the valid reset signal Vr is a low level signal, and the third resistor R3 is used for limiting the current of the reset signal Vr. The first switch tube Q1 is turned off when the received reset signal Vr is a low level signal, at this time, if the level shift circuit 20 receives the first voltage signal VDD1, that is, when the main control circuit is in a normal working state, the first voltage signal VDD1 generates the first switch control signal Vc1 after passing through the fifth resistor R5, and the effective first switch control signal Vc1 is a high level signal; if the level shift circuit 20 does not receive the first voltage signal VDD1, that is, when the MCU in the main control circuit performs the burning operation, the level shift circuit 20 outputs the second switch control signal Vc2, and the valid second switch control signal Vc2 is a low level signal.

In one embodiment, as shown in fig. 4, the level holding circuit includes a receiving unit 31, a switching unit 32, and a level holding unit 33, wherein the receiving unit 31 is configured to receive the second voltage signal VDD2 or the third voltage signal VDD 3. The switch unit 32 is connected to the level shifter circuit 20, and is configured to output a first control signal when receiving a first switch control signal Vc1 from the level shifter circuit 20, and further configured to output a second control signal when receiving a second switch control signal Vc2 from the level shifter circuit 20. The level holding unit 33 is connected to the receiving unit 31 and the switching unit 32, respectively, and is configured to output a reset control signal Vrc when receiving the second voltage signal VDD2 and the first control signal, and further configured to output a hold control signal Vhc when receiving the third voltage signal VDD3 and the second control signal.

Specifically, as shown in fig. 4, the receiving unit 31 receives the second voltage signal VDD2 and outputs the second voltage signal VDD2 to the level-keeping unit 33 when the main control circuit is in the normal operating state, and receives the third voltage signal VDD3 and outputs the third voltage signal VDD3 to the level-keeping unit 33 when the main control circuit is in the burn operating state. The switch unit 32 receives the first switch control signal Vc1 or the second switch control signal Vc2 output by the level shift circuit 20, and enables the level holding unit 33 to output the reset control signal Vrc according to the first switch control signal Vc1, so as to enable the MCU in the main control circuit to perform a reset operation, or enables the level holding unit 32 to output the hold control signal Vhc according to the second switch control signal Vc2, so as to enable the MCU in the main control circuit to continue to maintain a normal burning operation.

In one embodiment, referring to fig. 4, the switch unit 32 includes a sixth resistor R6, a seventh resistor R7, a third capacitor C3, and a second switch tube Q2. The sixth resistor R6 and the third capacitor C3 are respectively connected between the control end and the second end of the second switch transistor Q2; a first end of the seventh resistor R7 is connected to the control end of the second switch Q2, and a second end of the seventh resistor R7 is connected to the output end of the level shifter 20; a first terminal of the second switching tube Q2 is connected to the level holding unit 33, and a second terminal of the second switching tube Q2 is grounded to GND.

Specifically, the second switch Q2 receives the first switch control signal Vc1 or the second switch control signal Vc2 output by the level shift circuit 20 through the seventh resistor R7, and the second switch Q2 is turned on when receiving the first switch control signal Vc1, so that the output port of the level holding unit 33 outputs an effective reset control signal Vrc (set at a low level), so that the MCU in the main control circuit performs a reset operation. The second switch tube Q2 is turned off when receiving the second switch control signal Vc2, so that the output port of the level holding unit 33 outputs a holding control signal Vhc (set at a high level) to the main control circuit, so that the MCU in the main control circuit performs burning normally. Therefore, even if the MCU of the main control circuit is in a burning state and cannot send the zero clearing signal Ve to the watchdog circuit, the watchdog circuit still sends the holding control signal Vhc to the main control circuit, so that the MCU can carry out normal burning.

In one embodiment, referring to fig. 4, the level holding unit 33 includes an eighth resistor R8 and a fourth capacitor C4. A first end of the eighth resistor R8 is connected to the receiving unit 31, a second end of the eighth resistor R8 and a first end of the fourth capacitor C4 are connected to the main control circuit, and a second end of the fourth capacitor C4 is grounded GND.

Referring to fig. 5, in a normal operating state of the MCU, the first voltage signal VDD1 and the second voltage signal VDD2 are normally input, and the third voltage signal VDD3 from the recorder has no input. When the program of the MCU flies, the watchdog chip U1 outputs a low-level reset signal Vr to the first switch tube Q1 through the resistor R3, the base of the first switch tube Q1 is at a low level, the first switch tube Q1 is turned off, at this time, the first voltage signal VDD1 is output to the base of the second switch tube Q2 through the fifth resistor R5, the base voltage of the second switch tube Q2 is pulled high, the second switch tube Q2 is turned on, the second voltage signal VDD2 is grounded through the eighth resistor R8 and the second switch tube Q2, that is, the voltage of the second end of the eighth resistor R8 is pulled low to ground, and the level holding circuit 30 outputs a low-level reset control signal Vrc to the MCU, so that the MCU performs a reset operation.

When the MCU is in a recording state, the watchdog circuit does not receive the first voltage signal VDD1 and the second voltage signal VDD2, only receives the third voltage signal VDD3 from the recorder, and the watchdog chip does not receive the clear signal Ve, the watchdog chip outputs the low-level reset signal Vr to the level shifter circuit 20, the first switch tube Q1 in the level shifter circuit 20 is turned off, and the fifth resistor R5 does not receive the first voltage signal VDD1, so that the second end of the fifth resistor R5 outputs the low-level second switch control signal Vc2, so that the second switch tube Q2 in the level keeper circuit 30 is turned off, and therefore the eighth resistor R8 divides the accessed third voltage signal VDD3 to form a level keeping signal Vc, which is output to the MCU, so that the MCU performs a recording operation.

In one embodiment, in conjunction with fig. 1, 6, and 7, the watchdog circuit further comprises a first power supply circuit, a second power supply circuit, and a third power supply circuit. The first power supply circuit and the second power supply circuit perform voltage stabilization/voltage conversion based on the same working power supply Vd to respectively provide a first voltage signal VDD1 and a second voltage signal VDD 2; meanwhile, the working power supply Vd is used for supplying power to the MCU, and the third power supply circuit is a burning device such as a burner. When the MCU is in a normal working state, the first power supply circuit provides a first voltage signal VDD1, the second power supply circuit provides a second voltage signal VDD2, and the third power supply circuit is not connected and does not provide a third voltage signal VDD 3; when the MCU is in a burning state, the first power supply circuit does not provide the first voltage signal VDD1, the second power supply circuit does not provide the second voltage signal VDD2, and the third power supply circuit provides the third voltage signal VDD 3. In this embodiment, when the MCU is in the burning state, the level holding circuit 30 outputs the holding control signal Vhc according to the third voltage signal VDD3 to make the MCU continue to work normally without affecting the MCU to perform the burning operation.

In one embodiment, referring to fig. 5 and 6, the second power supply circuit includes a first diode D1, a fifth capacitor C5, a sixth capacitor R6, a seventh capacitor C7, and a first power management chip U2. Wherein, the anode of the first diode D1 is connected with the working power Vd, and the cathode of the first diode D1 is connected with the voltage input end VIN of the first power management chip U2; a first end of the fifth capacitor C5 is connected to the voltage input terminal VIN of the first power management chip U2, and a second end of the fifth capacitor C5 is grounded to GND; a first end of the sixth capacitor C6 is connected to the noise bypass end BP of the first power management chip U2, and a second end of the sixth capacitor C6 is grounded to GND; the enable pin EN of the first power management chip U2 is connected to the cathode of the first diode D1. The voltage output terminal VOUT of the first power management chip U2 is connected to the receiving unit 31 and outputs a second voltage signal VDD 2. The first end of the seventh capacitor R7 is connected to the voltage output terminal VOUT of the first power management chip U2, and the second end of the seventh capacitor C7 is connected to the ground GND. In this embodiment, the enable pin EN of the first power management chip U2 activates the first power management chip U2 after detecting the operating voltage inputted by the operating power Vd, and the first power management chip U2 starts to operate. The first power management chip U2 converts the operating voltage input by the operating power Vd into a second voltage signal VDD2 and outputs the second voltage signal VDD 2.

In this embodiment, the second power supply circuit and the first power supply circuit are the same power supply, and the first diode D1 is connected between the working power Vd and the first power management chip U2, and is used for preventing interference of the working power Vd or the MCU.

In one embodiment, referring to fig. 5 and 7, the first power supply circuit includes an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, and a second power management chip U3. A first end of the eighth capacitor C8 is connected to the voltage input terminal VIN of the second power management chip U3, and a second end of the eighth capacitor C8 is grounded to GND; a first end of the ninth capacitor C9 is connected to the noise bypass terminal BP of the second power management chip U3, and a second end of the ninth capacitor C9 is grounded GND; the enable pin EN of the second power management chip U3 is connected to the operating power Vd, the voltage input terminal VIN of the second power management chip U3 is connected to the operating power Vd, and the voltage output terminal VOUT of the second power management chip U3 is connected to the timing circuit 10 and the level shift circuit 20 and outputs the first voltage signal VDD 1. The first end of the tenth capacitor R10 is connected to the voltage output terminal VOUT of the second power management chip U3, and the second end of the tenth capacitor C10 is connected to the ground GND. In this embodiment, the enable pin EN of the second power management chip U3 activates the second power management chip U3 after detecting the operating voltage input by the operating power Vd, and the second power management chip U3 starts to operate. The second power management chip U3 converts the operating voltage input by the operating power Vd into the first voltage signal VDD1 and outputs the first voltage signal VDD 1.

The present application provides, in another aspect, an electronic device including the watchdog circuit described in any one of the above embodiments.

The electronic equipment can detect whether the MCU is in a normal state or not through the set watchdog circuit, when the MCU is in the normal state or in a burning state, the electronic equipment outputs a holding control signal to enable the MCU to continue to normally work, and when the MCU breaks down, the electronic equipment outputs a reset control signal to control the MCU to stop working. The electronic equipment enables the MCU to carry out normal burning work when the MCU is in a burning state, and the problem that the MCU cannot be burned normally when the MCU carries out burning and the watchdog circuit sends a reset signal to the MCU is solved.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A watchdog circuit connected to a master control circuit, the watchdog circuit comprising:

the timing circuit is connected with the main control circuit and used for generating a reset signal when the power supply input end of the timing circuit does not receive a first voltage signal or a reset signal provided by the main control circuit is not received within a preset time interval;

the level switching circuit is connected with the timing circuit and used for outputting a first switch control signal when receiving the reset signal and a first voltage signal input by a power supply input end of the level switching circuit, and outputting a second switch control signal when only receiving the reset signal output by the timing circuit;

and the level holding circuit is connected with the level conversion circuit, and is used for outputting a reset control signal to the main control circuit to stop the main control circuit when receiving a second voltage signal and the first switch control signal which are input by a power supply input end of the level holding circuit, and is also used for outputting a holding control signal to the main control circuit to enable the main control circuit to normally work when receiving a third voltage signal and the second switch control signal which are input by the power supply input end of the level holding circuit.

2. The watchdog circuit of claim 1, wherein the watchdog circuit further comprises:

the isolation circuit is arranged between the timing circuit and the main control circuit, is used for transmitting the zero clearing signal to the timing circuit when receiving the zero clearing signal output by the main control circuit, and is also used for isolating the non-zero clearing signal sent by the main control circuit.

3. The watchdog circuit of claim 1, wherein the timing circuit comprises: the watchdog circuit comprises a watchdog chip, a first resistor, a second resistor and a first capacitor; wherein the content of the first and second substances,

a first end of the first resistor receives the first voltage signal, and a second end of the first resistor is connected with a power supply input end of the watchdog chip; the first end of the first capacitor is grounded, and the second end of the first capacitor is connected with the power supply input end of the watchdog chip; the zero clearing signal input end of the watchdog chip is connected with the main control circuit; the second resistor is connected between the power supply input end of the watchdog chip and the zero clearing input end of the watchdog chip.

4. The watchdog circuit of claim 1, wherein the level shift circuit comprises a third resistor, a fourth resistor, a fifth resistor, a second capacitor, and a first switch transistor; wherein, the first and the second end of the pipe are connected with each other,

the first end of the third resistor is connected with the output end of the timing circuit, and the second end of the third resistor is connected with the control end of the first switch tube; the first end of the first switch tube is connected with the level holding circuit, and the second end of the first switch tube is grounded; the fourth resistor and the second capacitor are respectively connected between the control end of the first switch tube and the second end of the first switch tube; the first end of the fifth resistor is connected with the first end of the first switching tube, and the second end of the fifth resistor is connected with the power supply input end of the level conversion circuit.

5. The watchdog circuit of claim 1, wherein the level hold circuit comprises:

a receiving unit, configured to receive the second voltage signal or the third voltage signal;

the switch unit is connected with the level conversion circuit and used for outputting a first control signal when receiving a first switch control signal of the level conversion circuit; the first switch is used for switching the level conversion circuit to a first switch control signal;

and the level holding unit is respectively connected with the receiving unit and the switching unit, and is used for outputting the reset control signal when receiving the second voltage signal and the first control signal and outputting the holding control signal when receiving the third voltage signal and the second control signal.

6. The watchdog circuit of claim 5, wherein the switch unit includes a sixth resistor, a seventh resistor, a third capacitor, and a second switch tube; wherein the content of the first and second substances,

the sixth resistor and the third capacitor are respectively connected between the control end and the second end of the second switching tube; a first end of the seventh resistor is connected with the control end of the second switch tube, and a second end of the seventh resistor is connected with the output end of the level conversion circuit; the first end of the second switch tube is connected with the level holding unit, and the second end of the second switch tube is grounded.

7. The watchdog circuit of claim 5, wherein the level holding unit includes an eighth resistor and a fourth capacitor; the first end of the eighth resistor is connected to the receiving unit, the second end of the eighth resistor and the first end of the fourth capacitor are connected to the main control circuit, and the second end of the fourth capacitor is grounded.

8. The watchdog circuit of claim 5, wherein the watchdog circuit further comprises:

the first power supply circuit is connected with the level conversion circuit, the timing circuit and the power supply and is used for converting the power supply voltage of the power supply into a first voltage signal and then outputting the first voltage signal to the timing circuit and the level conversion circuit;

the second power supply circuit is connected with the level holding circuit and the power supply, converts the power supply voltage of the power supply into a second voltage signal, and then outputs the second voltage signal to the level holding circuit;

and the third power supply circuit is connected with the level conversion circuit and used for receiving a third voltage signal and outputting the third voltage signal to the level holding circuit.

9. The watchdog circuit of claim 8, wherein the second power supply circuit comprises a first diode, a fifth capacitor, a sixth capacitor, a seventh capacitor, and a first power management chip; wherein, the first and the second end of the pipe are connected with each other,

the anode of the first diode is connected with the power supply, and the cathode of the first diode is connected with the voltage input end of the first power management chip; the first end of the fifth capacitor is connected with the voltage input end of the first power management chip, and the second end of the fifth capacitor is grounded; the first end of the sixth capacitor is connected with the noise bypass end of the first power management chip, and the second end of the sixth capacitor is grounded;

the voltage output end of the first power supply management chip is connected with the receiving unit;

and the first end of the seventh capacitor is connected with the voltage output end of the first power management chip, and the second end of the seventh capacitor is grounded.

10. An electronic device, characterized in that the electronic device comprises a watchdog circuit according to any one of claims 1-9.

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