CN109116179B - Handle function test circuit and handle function test device - Google Patents
Handle function test circuit and handle function test device Download PDFInfo
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- CN109116179B CN109116179B CN201811084987.4A CN201811084987A CN109116179B CN 109116179 B CN109116179 B CN 109116179B CN 201811084987 A CN201811084987 A CN 201811084987A CN 109116179 B CN109116179 B CN 109116179B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
- G01R31/68—Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
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Abstract
The invention discloses a handle function test circuit and a handle function test device, wherein the handle function test circuit comprises: the electric connector is used for being inserted with the expansion interface of the handle and is provided with a power supply end and a trigger signal output end; the device access trigger circuit is electrically connected with the trigger signal output end of the electric connector so as to trigger the handle to act when the electric connector is accessed to the extension interface of the handle, so that the handle outputs a first direct current power supply to the power end of the electric connector through the handle extension interface; and the detection end of the power supply detection circuit is connected with the power end of the electric connector and is used for detecting the voltage of the first direct current power supply and outputting a corresponding voltage detection signal. The invention realizes the hardware test of the expansion interface of the handle.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a handle function testing circuit and a handle function testing device.
Background
The handle, for example the game paddle in the process of producing line assembly, may cause the expansion interface of handle to appear the phenomenon of buckling easily because of touching such as falling and colliding, and when leading to the handle and the connecting terminal of external equipment to be connected, the problem that contact failure appears, and the expansion interface that does not handle is less, is difficult to discover under the ordinary condition through artifical naked eye, and is easily neglected.
Disclosure of Invention
The invention mainly aims to provide a handle function test circuit and a handle function test device, and aims to realize hardware test of an expansion interface of a handle.
In order to achieve the above object, the present invention provides a handle function test circuit, including:
the electric connector is used for being inserted into the extension interface of the handle and is provided with a power supply end and a trigger signal output end;
the device access trigger circuit is electrically connected with a trigger signal output end of the electric connector so as to trigger the handle to act when the electric connector is accessed to the extension interface of the handle, so that the handle outputs a first direct current power supply to a power end of the electric connector through the handle extension interface;
and the detection end of the power supply detection circuit is connected with the power end of the electric connector and is used for detecting the voltage of the first direct current power supply and outputting a corresponding voltage detection signal.
Optionally, the handle function test circuit further includes a memory, a clock pin and a data pin of the memory are connected to the handle through the electrical connector, and the memory stores handle communication state test data.
Optionally, the handle function test circuit further includes an I2C bus I/O expansion chip, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first capacitor, where clock pins and data pins of the I2C bus I/O expansion chip are connected to clock pins and data pins of the memory in a one-to-one correspondence, and a quasi-bidirectional input pin of the I2C bus I/O expansion chip is connected to a write protection pin of the memory; the first resistor is arranged between the output end of the power supply detection circuit and a clock pin of the I2C bus I/O expansion chip in series; the second resistor is arranged between the output end of the power supply detection circuit and the data pin of the I2C bus I/O expansion chip in series; the third resistor is arranged between the output end of the power supply detection circuit and a quasi-bidirectional input pin of the I2C bus I/O expansion chip in series; the first end of the fourth resistor is interconnected with the power pin of the I2C bus I/O expansion chip and the output end of the power supply detection circuit, and the second end of the fourth resistor is connected with the reset pin of the I2C bus I/O expansion chip.
Optionally, the handle function test circuit further includes a fifth resistor and a sixth resistor, the electrical connector further includes a clock signal terminal and a data signal terminal, the fifth resistor is connected to the clock signal terminal, and the sixth resistor is connected to the data signal terminal.
Optionally, the handle function test circuit further includes a first transient suppression diode and a second transient suppression diode, the first transient suppression diode is serially connected between the clock signal terminal and the ground, and the second transient suppression diode is serially connected between the data signal terminal and the ground.
Optionally, the device access trigger circuit includes a seventh resistor, a first end of the seventh resistor is connected to the trigger signal output terminal, and a second end of the seventh resistor is grounded.
Optionally, the power supply detection circuit includes a detection trigger unit and a first electronic switch, an input end of the detection trigger unit is a detection end of the power supply detection circuit and is connected to an input end of the first electronic switch, and an output end of the detection trigger unit is connected to a controlled end of the first electronic switch; the output end of the first electronic switch is the output end of the power supply detection circuit.
Optionally, the detection trigger unit includes an eighth resistor, a ninth resistor, a zener diode, and a second electronic switch, where a first end of the eighth resistor is a detection end of the detection trigger unit, and a second end of the eighth resistor is interconnected with a cathode of the zener diode and a first end of the ninth resistor; the anode of the voltage stabilizing diode is grounded; and the second end of the ninth resistor is the output end of the detection trigger unit.
Optionally, the power supply detection circuit further includes a tenth resistor and a second capacitor, the first electronic switch is a P-MOS transistor, a gate of the P-MOS transistor is a controlled terminal of the first electronic switch and is connected to a first terminal of the tenth resistor, a drain of the P-MOS transistor is an input terminal of the first electronic switch, a source of the P-MOS transistor is an output terminal of the first electronic switch and is connected to a first terminal of the second capacitor, and a second terminal of the second capacitor and a second terminal of the tenth resistor are grounded.
The invention also provides a handle function testing device which comprises the handle function testing circuit.
The handle function test circuit is provided with an electric connector, a device access trigger circuit and a power supply detection circuit, wherein the electric connector is inserted with an extension interface of a handle, the device access trigger circuit is electrically connected with a trigger signal output end of the electric connector, so that when the electric connector is connected to the extension interface of the handle, the handle is triggered to act to complete interface access state test, and meanwhile, the trigger handle outputs a first direct current power supply to a power supply end of the electric connector through the handle extension interface. The detection pin of the power supply detection circuit is connected with the power supply end of the electric connector, whether the extension interface pin of the handle is normal is tested by detecting the voltage of the power supply end, and when the extension interface pin is normal, a corresponding voltage detection signal, namely a first direct current power supply, is output to supply power for other circuit modules in the handle function test circuit. The invention realizes the hardware test of the expansion interface of the handle.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a functional block diagram of a handle function test circuit according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a handle function test circuit according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of an embodiment of the power supply detection circuit shown in FIG. 1;
FIG. 4 is a schematic circuit diagram of an embodiment of a memory in the handle function test circuit according to the present invention;
fig. 5 is a schematic circuit structure diagram of another embodiment of the handle function test circuit of the present invention.
The reference numbers illustrate:
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a handle function test circuit.
Referring to fig. 1 to 5, in an embodiment of the present invention, the handle function test circuit includes:
the electric connector 10 is used for being plugged with an expansion interface of the handle, and the electric connector 10 is provided with a power supply end VDD and a trigger signal output end STA;
the device access trigger circuit 20 is electrically connected with the trigger signal output terminal STA of the electrical connector 10, so as to trigger the handle to act when the electrical connector 10 is connected to the handle extension interface, so that the handle outputs a first direct current power source to the power supply terminal VDD of the electrical connector 10 through the handle extension interface;
and a power supply detection circuit 30, a detection end of which is connected to the power supply end VDD of the electrical connector 10, and configured to detect a voltage of the first direct current power supply and output a corresponding voltage detection signal.
In this embodiment, the electrical connector 10 may be a plug adapted to be plugged into an expansion interface of the handle, and the electrical connector 10 may also be a connection terminal strip formed by a plurality of connection terminals, where the connection terminal strip has a plug interface for inserting a contact pin in the expansion interface of the handle. When the handle needs to be tested, the electric connector 10 is plugged with the expansion interface of the handle, so that the functional tests of the handle, such as the communication test of the handle, the interface test of the handle and the like, are completed.
The handle is provided with an interface detection circuit and a power supply, wherein the interface detection circuit is used for detecting whether an external device is connected, for example, a game device, and controlling the power supply to supply power to the external device when the external device is connected.
The device access trigger circuit 20 of this embodiment may simulate a trigger circuit of a game device, and when the electrical connector 10 is plugged into the extended interface of the handle, the device access trigger circuit is connected to the interface detection circuit of the handle through the electrical connector 10 to trigger the interface detection circuit of the handle to operate, so that the power supply in the handle outputs the power supply to the power supply terminal VDD of the electrical connector 10 through the extended interface of the handle. The power supply end VDD of the electrical connector 10 is used for connecting a first direct current power supply output by the handle to supply power to the circuit module in the handle function test circuit.
It should also be noted that the expansion interface of the handle is generally provided with a power input pin (VAC) for accessing an external power supply, and a power output pin (VDD) for supplying power to an external device such as a game machine, and the power input pin and the power output pin are disposed adjacent to each other. The terminal of the electrical connector 10 connected to the power input pin is left vacant, i.e. not connected to the handle function test circuit through the pin; the power supply output pin is connected to the power supply terminal VDD of the electrical connector 10. When external equipment is inserted into the two pins, the two pins are easy to bend, and even the two pins are short-circuited. The power voltage input by the power input pin is different from the power voltage output by the power output pin in size, generally, the power voltage input by the power input pin is 5V, the power voltage output by the power output pin is 3.2V, if the two pins are in short circuit, the output voltage of the power output pin is larger than the preset voltage, the voltage output to the handle test circuit is too large, and the rear-stage circuit is damaged.
In order to avoid the above problem, in this embodiment, the power supply detection circuit 30 is configured to detect the power supply end VDD voltage of the electrical connector 10, and determine, through the detected power supply voltage, whether the handle supplies power to the handle function test circuit after the electrical connector 10 is plugged into the expansion interface of the handle, and detect the power supply end VDD voltage through the power supply detection circuit 30, and also test whether the pin of the expansion interface of the handle is normal.
Specifically, when detecting that the voltage value of the power supply terminal VDD of the electrical connector 10 is the first dc power supply voltage value, that is, 3.2V, the power supply detection circuit 30 outputs the first dc power supply to other circuit modules of the handle function test circuit to supply power to the handle function test circuit. When it is detected that the voltage value of the power supply terminal VDD of the electrical connector 10 is greater than 3.2V, for example, 5V, it may be determined that the power input pin and the power output pin of the expansion interface of the handle are short-circuited at this time, and the power supply detection circuit 30 does not operate at this time, that is, the voltage of the power supply terminal VDD cannot be output to other circuit modules of the handle function test circuit, so that other function tests of the handle cannot be performed. Or when detecting that the voltage value of the power supply terminal VDD of the electrical connector 10 is smaller than the voltage value of the first direct current power supply, that is, smaller than 3.2V, it may be determined that the power output pin is bent and is not electrically connected to the power supply terminal VDD of the electrical connector 10, and at this time, the power supply detection circuit 30 does not act, that is, the voltage of the power supply terminal VDD cannot be output to other circuit modules of the handle function test circuit, so that other function tests of the handle cannot be performed.
The handle function test circuit is provided with an electric connector 10, a device access trigger circuit 20 and a power supply detection circuit 30, wherein the electric connector 10 is inserted with an extended interface of a handle, the device access trigger circuit 20 is electrically connected with a trigger signal output end STA of the electric connector 10, so that when the electric connector 10 is connected with the extended interface of the handle, the handle is triggered to act to complete interface access state test, and meanwhile, the handle is triggered to output a first direct current power supply to a power supply end VDD of the electric connector 10 through the handle extended interface. The detection pin of the power supply detection circuit 30 is connected to the power supply terminal VDD of the electrical connector 10, and detects the voltage of the power supply terminal VDD to test whether the pin of the expansion interface of the handle is normal, and when the pin of the expansion interface is normal, outputs a corresponding voltage detection signal, i.e., a first dc power supply, to supply power to other circuit modules in the handle function test circuit. The invention realizes the hardware test of the expansion interface of the handle. The invention simulates external equipment to connect the electric connector 10 to the handle, thus automatically realizing the hardware test of the expansion interface of the handle, reducing the workload of manual detection and being beneficial to improving the test efficiency of the handle. In addition, the circuit of the invention has simple structure and easy realization, can be widely applied to the test of the expansion interface of other electronic equipment, and takes the handle as an example for explanation, but is not limited to the handle.
Referring to fig. 1 to 5, in an alternative embodiment, the handle function test circuit further includes a memory 40, the clock pin and the data pin of the memory 40 are connected to the handle through the electrical connector 10, and the memory 40 stores handle communication status test data.
In this embodiment, a memory 40 is further provided for simulating a storage medium of an external device, and test data for testing the communication state of the handle is stored in the memory 40, so that when the electrical connector 10 is connected to the handle, an external communication device is simulated and the handle is communicated, so that the handle reads the data stored in the memory 40. It can be understood that the memory 40 stores communication state test data for testing the communication state of the handle, the test data may be a string of characters, and when the handle is in communication connection with the memory 40, it is possible to determine whether the communication function of the handle is normal by detecting whether the handle reads the string of characters. The invention can also realize the I2C communication function test of the handle.
In this embodiment, the handle function test circuit is further provided with a capacitor C3, and the capacitor C3 is provided in series between the power source terminal of the power source terminal memory 40 and ground.
Referring to fig. 1 to 5, in an optional embodiment, the handle function test circuit further includes an I2C bus I/O expansion chip IC1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first capacitor C1, a clock pin and a data pin of the I2C bus I/O expansion chip IC1 are connected to a clock pin and a data pin of the memory 40 in a one-to-one correspondence, and a quasi-bidirectional input pin of the I2C bus I/O expansion chip IC1 is connected to a write protection pin of the memory 40; the first resistor R1 is serially connected between the output end of the power supply detection circuit 30 and the clock pin of the I2C bus I/O expansion chip IC 1; the second resistor R2 is serially connected between the output terminal of the power supply detection circuit 30 and the data pin of the I2C bus I/O expansion chip IC 1; the third resistor R3 is serially connected between the output terminal of the power detection circuit 30 and the quasi-bidirectional input pin of the I2C bus I/O expansion chip IC 1; a first end of the fourth resistor R4 is interconnected with the power pin of the I2C bus I/O expansion chip IC1 and the output end of the power detection circuit 30, and a second end of the fourth resistor R4 is connected with the reset pin of the I2C bus I/O expansion chip IC 1.
In this embodiment, the I2C bus I/O expansion chip IC1 is used to implement write protection of the memory 40, so as to prevent the data stored in the memory 40 from being rewritten during the operation of the memory 40, that is, when the data is not updated, specifically, when the memory 40 communicates with the handle, that is, when the handle reads the data of the memory 40, the quasi-bidirectional input pin of the I2C bus I/O expansion chip IC1 and the write protection pin of the memory 40 are pulled up by the third resistor R3, and a high level is output. When the memory 40 needs to update data, the I2C bus I/O expansion chip IC1 outputs a low-level write protection signal to be in communication connection with the upper computer through the I2C bus I/O expansion chip IC1 and the electrical connector 10, and the upper computer records program data into the memory 40 to complete data updating. The first resistor R1, the second resistor R2 and the third resistor R3 are pull-up resistors, which are used for pulling up the pins of the I/O expansion chip when the I/O expansion chip does not perform data transmission, thereby providing a high-level signal. The fourth resistor R4 is a reset resistor, and forms a reset circuit with the first capacitor C1 to reset the I2C bus I/O expansion chip IC1 when the handle function test circuit is powered on.
Referring to fig. 1 to 5, in an alternative embodiment, the handle function test circuit further includes a fifth resistor R5 and a sixth resistor R6, the electrical connector 10 further includes a clock signal terminal SCL and a data signal terminal SDA, the fifth resistor R5 is connected to the clock signal terminal SCL, and the sixth resistor R6 is connected to the data signal terminal SDA.
In this embodiment, the clock signal terminal SCL and the data terminal are used to implement the communication connection between the memory 40 and the handle, and perform data transmission. The fifth resistor R5 and the sixth resistor R6 are impedance matching resistors for impedance matching with the handle when the electrical connector 10 is connected to the handle.
Referring to fig. 1 to 5, in an alternative embodiment, the handle function test circuit further includes a first transient suppression diode TVS1 and a second transient suppression diode TVS2, the first transient suppression diode TVS1 is serially disposed between the clock signal terminal SCL and ground, and the second transient suppression diode TVS2 is serially disposed between the data signal terminal SDA and ground.
In this embodiment, the first transient suppression diode TVS1 and the second transient suppression diode TVS2 are used to prevent the I2C bus I/O expansion chip IC1 from being damaged by transient spike, such as electrostatic discharge effect or noise signal, and also to prevent the spike generated by the handle test circuit from being injected into the handle and the electronic components inside the handle.
Referring to fig. 1 to 5, in an alternative embodiment, the device access trigger circuit 20 includes a seventh resistor R7, a first end of the seventh resistor R7 is connected to the trigger signal output terminal STA, and a second end of the seventh resistor R7 is connected to ground.
In this embodiment, the seventh resistor R7 is serially connected between the trigger signal output terminal STA of the electrical connector 10 and ground, so that when the electrical connector 10 is connected to the expansion interface of the handle, the low-level trigger signal is output to the trigger signal output terminal STA, thereby triggering the handle to operate and outputting the first dc power to the power supply terminal VDD.
Referring to fig. 1 to 5, in an alternative embodiment, the power supply detection circuit 30 includes a detection trigger unit 31 and a first electronic switch Q1, an input terminal of the detection trigger unit 31 is a detection terminal of the power supply detection circuit 30 and is connected to an input terminal of the first electronic switch Q1, and an output terminal of the detection trigger unit 31 is connected to a controlled terminal of the first electronic switch Q1; the output terminal of the first electronic switch Q1 is the output terminal of the power supply detection circuit 30.
In this embodiment, the detection trigger unit 31 is used for detecting the power supply voltage of the power supply terminal VDD, and triggering the first electronic switch Q1 to turn on/off according to the detected power supply voltage.
Specifically, when detecting that the voltage value of the power supply terminal VDD of the electrical connector 10 is the first dc power supply voltage value, that is, 3.2V, the detection trigger unit 31 triggers the first electronic switch Q1 to be turned on, so as to output the first dc power supply to other circuit modules of the handle function test circuit to supply power to the handle function test circuit. When detecting that the voltage value of the power supply terminal VDD of the electrical connector 10 is greater than 3.2V, for example, 5V, the detection trigger unit 31 does not act, so as to trigger the first electronic switch Q1 to maintain the off state, and the power supply terminal VDD does not connect the voltage to other circuit modules of the handle function test circuit. When detecting that the voltage value of the power supply terminal VDD of the electrical connector 10 is smaller than the first dc power supply voltage value, that is, smaller than 3.2V, the detection trigger unit 31 does not act, so as to trigger the first electronic switch Q1 to keep an off state, and the power supply terminal VDD does not access the voltage to other circuit modules of the handle function test circuit.
Referring to fig. 1 to 5, in an alternative embodiment, the detection trigger unit 31 includes an eighth resistor R8, a ninth resistor R9, a zener diode ZD1 and a second electronic switch Q2, a first terminal of the eighth resistor R8 is a detection terminal of the detection trigger unit 31, and a second terminal of the eighth resistor R8 is interconnected with a cathode of the zener diode ZD1 and a first terminal of the ninth resistor R9; the anode of the zener diode ZD1 is grounded; a second end of the ninth resistor R9 is an output end of the detection trigger unit 31.
Further, the power supply detection circuit 30 further includes a tenth resistor R10 and a second capacitor C2, the first electronic switch Q1 is a P-MOS transistor, a gate of the P-MOS transistor is a controlled terminal of the first electronic switch Q1 and is connected to the first terminal of the tenth resistor R10, a drain of the P-MOS transistor is an input terminal of the first electronic switch Q1, a source of the P-MOS transistor is an output terminal of the first electronic switch Q1 and is connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 and the second terminal of the tenth resistor R10 are grounded.
In this embodiment, the first electronic switch Q1 and the second electronic switch Q2 may be implemented by transistors, MOS transistors, IGBTs, and other switching transistors, in which the first electronic switch Q1 may be a P-MOS transistor, and the second electronic switch Q2 may be a PNP-type transistor.
The specific working process of each element of the trigger detection circuit and the first electronic switch Q1 is as follows:
when the power supply voltage accessed by the power supply terminal VDD is a first direct-current power supply, that is, 3.2V, the zener diode ZD1 is reversely cut off, the voltage at the two ends of the eighth resistor R8 and the ninth resistor R9 is a high level of 3.2V, and the PNP type triode is kept cut off; the gate voltage of the P-MOS transistor is pulled low by the tenth resistor R10 to ground and turned on, and at this time, the P-MOS transistor outputs a first dc power voltage, i.e. 3.2V.
When the input of the power supply end VDD is abnormal, for example, a power supply input pin connected with the power supply end VDD is in short circuit with a power supply output pin, so that the input of the power supply end VDD is 5V, at the moment, the voltages of the eighth resistor R8 and the ninth resistor R9 are clamped at high level, for example, 3.9V, the PNP type triode is conducted, at the moment, the grid of the PMOS tube is at 5V high level and is cut off, at the moment, the P-MOS tube does not output the first direct current power supply, and the handle function test circuit does not work. The second capacitor C2 is a filter capacitor for filtering out noise components in the first dc power supply.
The invention also provides a handle function testing device which comprises the handle function testing circuit. The detailed structure of the handle function test circuit can refer to the above embodiments, and is not described herein; it can be understood that, because the handle function testing circuit is used in the handle function testing device of the present invention, the embodiment of the handle function testing device of the present invention includes all technical solutions of all embodiments of the handle function testing circuit, and the achieved technical effects are also completely the same, and are not described herein again.
In this embodiment, handle function test device still includes the host computer, and the host computer is connected with the handle communication to the test software of operation handle, and save the test log. For example, the handle reads the handle function test circuit, the handle communication state test data stored in the memory is read by the handle, and when the data is read by the handle, the data can be output to the upper computer when communicating with the upper computer so as to display that the handle and the memory are successfully communicated.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A handle function test circuit, the handle function test circuit comprising:
the electric connector is used for being inserted into the extension interface of the handle and is provided with a power supply end and a trigger signal output end;
the device access trigger circuit is electrically connected with the trigger signal output end of the electric connector so as to be used for simulating the trigger circuit of the game equipment to trigger the handle to act when the electric connector is connected to the extension interface of the handle, so that the handle outputs a first direct current power supply to the power end of the electric connector through the handle extension interface;
and the detection end of the power supply detection circuit is connected with the power end of the electric connector and is used for detecting the voltage of the first direct current power supply and outputting a corresponding voltage detection signal.
2. The handle functionality test circuit of claim 1, further comprising a memory, wherein a clock pin and a data pin of the memory are connected to the handle via the electrical connector, and wherein the memory stores handle communication status test data.
3. The functional test circuit of claim 2, further comprising an I2C bus I/O expansion chip, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first capacitor, wherein the clock pin and the data pin of the I2C bus I/O expansion chip are connected to the clock pin and the data pin of the memory in a one-to-one correspondence, and the quasi-bidirectional input pin of the I2C bus I/O expansion chip is connected to the write protection pin of the memory; the first resistor is arranged between the output end of the power supply detection circuit and a clock pin of the I2C bus I/O expansion chip in series; the second resistor is arranged between the output end of the power supply detection circuit and the data pin of the I2C bus I/O expansion chip in series; the third resistor is arranged between the output end of the power supply detection circuit and a quasi-bidirectional input pin of the I2C bus I/O expansion chip in series; the first end of the fourth resistor is interconnected with the power pin of the I2C bus I/O expansion chip and the output end of the power supply detection circuit, and the second end of the fourth resistor is connected with the reset pin of the I2C bus I/O expansion chip.
4. The functional test circuit of claim 1, further comprising a fifth resistor and a sixth resistor, wherein the electrical connector further comprises a clock signal terminal and a data signal terminal, the fifth resistor being connected to the clock signal terminal, and the sixth resistor being connected to the data signal terminal.
5. The handgrip function test circuit of claim 4, further comprising a first transient suppression diode and a second transient suppression diode, the first transient suppression diode being disposed in series between the clock signal terminal and ground, the second transient suppression diode being disposed in series between the data signal terminal and ground.
6. The handle function test circuit of claim 1, wherein the device access trigger circuit comprises a seventh resistor, a first end of the seventh resistor being connected to the trigger signal output terminal, a second end of the seventh resistor being connected to ground.
7. The handle function test circuit according to any one of claims 1 to 6, wherein the power supply detection circuit comprises a detection trigger unit and a first electronic switch, an input end of the detection trigger unit is a detection end of the power supply detection circuit and is connected with an input end of the first electronic switch, and an output end of the detection trigger unit is connected with a controlled end of the first electronic switch; the output end of the first electronic switch is the output end of the power supply detection circuit.
8. The handle function test circuit of claim 7, wherein the detection trigger unit comprises an eighth resistor, a ninth resistor, a zener diode and a second electronic switch, wherein a first terminal of the eighth resistor is a detection terminal of the detection trigger unit, and a second terminal of the eighth resistor is interconnected with a cathode of the zener diode and a first terminal of the ninth resistor; the anode of the voltage stabilizing diode is grounded; and the second end of the ninth resistor is the output end of the detection trigger unit.
9. The handle function test circuit of claim 7, wherein the power supply detection circuit further comprises a tenth resistor and a second capacitor, the first electronic switch is a P-MOS transistor, a gate of the P-MOS transistor is a controlled terminal of the first electronic switch and is connected to a first terminal of the tenth resistor, a drain of the P-MOS transistor is an input terminal of the first electronic switch, a source of the P-MOS transistor is an output terminal of the first electronic switch and is connected to a first terminal of the second capacitor, and a second terminal of the second capacitor and a second terminal of the tenth resistor are grounded.
10. A handle function testing device comprising a handle function testing circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811084987.4A CN109116179B (en) | 2018-09-17 | 2018-09-17 | Handle function test circuit and handle function test device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811084987.4A CN109116179B (en) | 2018-09-17 | 2018-09-17 | Handle function test circuit and handle function test device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109116179A CN109116179A (en) | 2019-01-01 |
| CN109116179B true CN109116179B (en) | 2021-08-20 |
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Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2418519Y (en) * | 2000-03-13 | 2001-02-07 | 神基科技股份有限公司 | Detection device for automatically detecting input and output interface |
| CN102269788B (en) * | 2010-06-03 | 2014-02-19 | 英业达股份有限公司 | Host device and plugging state detection method thereof |
| CN102692579A (en) * | 2011-03-25 | 2012-09-26 | 鸿富锦精密工业（深圳）有限公司 | Serial port detection circuit |
| CN102752623A (en) * | 2011-04-19 | 2012-10-24 | 鸿富锦精密工业（深圳）有限公司 | Signal testing device |
| CN102760089A (en) * | 2011-04-28 | 2012-10-31 | 鸿富锦精密工业（深圳）有限公司 | Motherboard diagnostic card |
| CN103871340B (en) * | 2014-03-06 | 2016-06-29 | 京东方科技集团股份有限公司 | Signaling interface detecting device |
| CN104732947B (en) * | 2015-04-16 | 2017-02-22 | 京东方科技集团股份有限公司 | Driving chip, driving board and method for testing same, and display device |
| CN105826894B (en) * | 2015-06-25 | 2018-06-26 | 维沃移动通信有限公司 | The charging short-circuit protection and power-supply device of power-supply device |
| TW201822068A (en) * | 2016-12-13 | 2018-06-16 | 英業達股份有限公司 | Automatic detection device, system and method thereof |
| CN206697953U (en) * | 2017-03-01 | 2017-12-01 | 顺丰科技有限公司 | Charging inlet short-circuit detecting device and mobile terminal |
| CN206820461U (en) * | 2017-03-30 | 2017-12-29 | 广州视源电子科技股份有限公司 | Power supply protection circuit |
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