CN117595928B

CN117595928B - Annotate wrong test fixture

Info

Publication number: CN117595928B
Application number: CN202410066347.XA
Authority: CN
Inventors: 张广乐; 薛广营; 郭月俊; 季冬冬
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2024-01-17
Filing date: 2024-01-17
Publication date: 2024-04-05
Anticipated expiration: 2044-01-17
Also published as: CN117595928A

Abstract

The invention discloses a fault injection test fixture, which relates to the technical field of testing and comprises the following components: the device comprises a main control unit, an isolation unit, an interface unit, a USB port test unit, an optical fiber port test unit and a power supply unit; the main control unit is used for issuing a fault injection instruction; the isolation unit is used for cutting off a connecting channel between a bus signal interface of the main control unit and the interface unit when the optical fiber port test unit simulates a bus short circuit according to the error injection instruction; the USB port test unit is used for connecting a USB port of the switch and simulating the power supply overcurrent of the USB port according to the fault injection instruction; the optical fiber port test unit is used for connecting an optical fiber port of the switch and simulating the over-current of an optical fiber port power supply and the short circuit of a bus according to the fault injection instruction. The fault injection test fixture can automatically complete the power supply overcurrent test and the bus signal short circuit test of the optical fiber port of the switch, and the power supply overcurrent test of the USB port of the switch, so that the test efficiency is improved, and the labor is saved.

Description

Annotate wrong test fixture

Technical Field

The invention relates to the technical field of testing, in particular to a fault injection testing jig.

Background

To ensure high reliability and high availability of the fibre switch, a large number of tests are required for the fibre switch. The fault injection test is one of the important tests. The fault injection test verifies whether the response of the optical fiber switch in the fault scene meets the expectations by injecting abnormal disturbance in the starting and running processes of the optical fiber switch. If the USB (Universal Serial Bus ) port and the optical fiber port of the optical fiber switch fail, the network system will be greatly affected, so that the error injection test needs to be performed on the USB port and the optical fiber port of the optical fiber switch. However, the current way to perform fault injection test on the USB port and the optical fiber port of the optical fiber switch is to manually construct a fault scenario, and then check whether the response of the optical fiber switch in the fault scenario meets the expectations. Such a fault injection test mode is inefficient and requires a lot of manpower. Therefore, providing a fault injection test scheme for ports of an optical fiber switch with high efficiency has become a technical problem to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide an error injection test fixture which can automatically complete power supply overcurrent test and bus signal short circuit test of an optical fiber port of a switch, complete power supply overcurrent test of a USB port of the switch, improve test efficiency and save manpower.

In order to solve the above technical problems, the present invention provides an error injection test fixture, comprising:

the device comprises a main control unit, an isolation unit, an interface unit, a USB port test unit, an optical fiber port test unit and a power supply unit; the main control unit is respectively connected with the isolation unit, the interface unit, the USB port test unit and the power supply unit; the isolation unit is also connected with the interface unit; the interface unit is also connected with the optical fiber port testing unit;

the main control unit is used for issuing error injection instructions to the isolation unit, the optical fiber port test unit and the USB port test unit;

the isolation unit is used for cutting off a connection channel between a bus signal interface of the main control unit and the interface unit when the optical fiber port test unit simulates a bus short circuit according to an error injection instruction issued by the main control unit;

The USB port test unit is used for connecting a USB port of the switch and simulating the power supply overcurrent of the USB port according to the fault injection instruction issued by the main control unit;

the optical fiber port test unit is used for connecting the optical fiber port of the switch and simulating the overcurrent of the optical fiber port power supply and the short circuit of the bus according to the fault injection instruction issued by the main control unit.

Optionally, the isolation unit includes:

the first isolation unit is used for cutting off a connection channel between a data signal interface of the main control unit and the interface unit when the optical fiber port test unit simulates a data signal short circuit according to an error injection instruction issued by the main control unit;

and the second isolation unit is used for cutting off a connection channel between a clock signal interface of the main control unit and the interface unit when the optical fiber port test unit simulates a clock signal short circuit according to the error injection instruction issued by the main control unit.

Optionally, the first isolation unit includes:

a first switch; the first switch is respectively connected with a data signal interface of the main control unit and the interface unit; when the main control unit enables the first switch, a data signal interface of the main control unit is disconnected from a connection channel of the interface unit.

Optionally, the second isolation unit includes:

a second switch; the second switch is respectively connected with the clock signal interface of the main control unit and the interface unit; when the main control unit enables the second switch, the clock signal interface of the main control unit is disconnected from the connection channel of the interface unit.

Optionally, the USB port test unit includes:

the first error injection unit is used for simulating the power supply overcurrent of the USB port;

and the USB interface unit is used for connecting with a USB port of the switch.

Optionally, the first error injection unit includes:

a plurality of first load circuits and a first voltage and current detection circuit; the first load circuit is respectively connected with the main control unit and the power interface of the USB interface unit;

the first load circuit is used for providing load current;

the first voltage and current detection circuit is used for detecting the current and the voltage of the power interface of the USB interface unit and feeding the current and the voltage back to the main control unit.

Optionally, the optical fiber port test unit includes:

the optical fiber interface unit is used for connecting an optical fiber port of the switch;

the second error injection unit is used for shorting the data signal interface of the optical fiber interface unit to a power supply or ground;

The third error injection unit is used for shorting the clock signal interface of the optical fiber interface unit to a power supply or ground;

the fourth error injection unit is used for shorting the data signal interface of the optical fiber interface unit and the clock signal interface of the optical fiber interface unit;

the fifth error injection unit is used for simulating the first power supply overcurrent of the optical fiber port;

and the sixth error injection unit is used for simulating the second power supply overcurrent of the optical fiber port.

Optionally, the second error injection unit includes:

a first transistor, a second transistor, a third transistor, and a first resistor; the first end of the first transistor is connected with the main control unit, the second end of the first transistor is grounded, the third end of the first transistor is connected with one end of the first resistor and the first end of the second transistor, the other end of the first resistor is connected with a power supply, the second end of the second transistor is connected with a data signal interface of the optical fiber interface unit, the third end of the second transistor is connected with the power supply, the first end of the third transistor is connected with the main control unit, the second end of the third transistor is grounded, and the third end of the third transistor is connected with a data signal interface of the optical fiber interface unit.

Optionally, the third error injection unit includes:

a fourth transistor, a fifth transistor, a sixth transistor, and a second resistor; the first end of the fourth transistor is connected with the main control unit, the second end of the fourth transistor is grounded, the third end of the fourth transistor is connected with one end of the second resistor and the first end of the fifth transistor, the other end of the second resistor is connected with a power supply, the second end of the fifth transistor is connected with the clock signal interface of the optical fiber interface unit, the third end of the fifth transistor is connected with the power supply, the first end of the sixth transistor is connected with the main control unit, the second end of the sixth transistor is grounded, and the third end of the sixth transistor is connected with the clock signal interface of the optical fiber interface unit.

Optionally, the fourth error injection unit includes:

a third switch; the third switch is connected with the interface unit, a data signal interface of the optical fiber interface unit and a clock signal interface of the optical fiber interface unit; and when the main control unit enables the third switch, the third switch shorts the data signal interface of the optical fiber interface unit and the clock signal interface of the optical fiber interface unit.

Optionally, the fifth error injection unit includes:

a plurality of second load circuits and a second voltage and current detection circuit; the second load circuit is connected with the interface unit and the first power interface of the optical fiber interface unit;

the second load circuit is used for providing load current;

the second voltage and current detection circuit is used for detecting the current and the voltage of the first power interface of the optical fiber interface unit and feeding back the current and the voltage to the main control unit.

Optionally, the sixth error injection unit includes:

a plurality of third load circuits and a third voltage and current detection circuit; the third load circuit is connected with the interface unit and a second power interface of the optical fiber interface unit;

the third load circuit is used for providing load current;

the third voltage and current detection circuit is used for detecting the current and the voltage of the second power interface of the optical fiber interface unit and feeding back the current and the voltage to the main control unit.

Optionally, the method further comprises:

and the display unit is used for displaying the data detected in the fault injection test process.

Optionally, the display unit is further configured to: and sending an operation instruction input by a user for controlling the display unit to the main control unit so that the main control unit issues a wrong injection instruction according to the operation instruction.

Optionally, the power supply unit includes:

the input power supply switching unit is used for switching the external direct-current voltage and the internal battery voltage;

and the voltage conversion unit is used for performing voltage conversion.

Optionally, the input power switching unit includes:

a first diode and a second diode; the first diode and the second diode share a cathode, an anode of the first diode is used for inputting external direct current voltage, and a cathode of the second diode is used for inputting internal battery voltage.

Optionally, the method further comprises:

and the storage unit is used for storing configuration information of the fault injection test jig.

Optionally, the main control unit is specifically configured to: when the error injection test is carried out on the USB port of the switch, if the test mode is a forced overcurrent test, selecting a target number of first load circuits to provide load current according to the configured overcurrent; if the test mode is the post-working overcurrent test, when the voltage of the power interface of the USB interface unit is higher than a first threshold value, starting delay timing, and when the delay timing reaches the first delay time, selecting a target number of first load circuits to provide load current according to the configured overcurrent.

Optionally, the main control unit is specifically configured to: when the optical fiber port of the switch is subjected to fault injection test, if the test item is a power supply test and the test mode is a forced overcurrent mode, selecting a target number of corresponding load circuits to provide load current according to the configured overcurrent; if the test item is a power supply test and the test mode is a post-operation overcurrent test, when the voltage of the power supply interface of the optical fiber interface unit is higher than a second threshold value, starting delay timing, and when the delay timing reaches the second delay time, selecting a target number of corresponding load circuits to provide load current according to the configured overcurrent.

Optionally, the main control unit is specifically configured to: when the optical fiber port of the switch is subjected to fault injection test, if the test item is that a bus signal is short-circuited to a short-circuit point and the test mode is a forced short-circuit mode, the corresponding switch is controlled to be disconnected, and the corresponding fault injection unit is controlled to enable the bus signal interface of the optical fiber interface unit to be short-circuited to the short-circuit point; if the test item is that the bus signal is short-circuited to a short-circuit point and the test mode is a working short-circuit mode, starting delay timing when the voltage of a target power interface on the optical fiber interface unit is higher than a third threshold value, controlling a corresponding switch to be disconnected when the delay timing reaches the third delay time, and controlling a corresponding error injection unit to enable the bus signal interface of the optical fiber interface unit to be short-circuited to the short-circuit point; the shorting point includes a power supply and ground.

Optionally, the main control unit is specifically configured to: when the optical fiber port of the switch is subjected to fault injection test, if the test item is short circuit among bus signals and the test mode is forced short circuit mode, controlling a fourth fault injection unit to short circuit a data signal interface of the optical fiber interface unit and a clock signal interface of the optical fiber interface unit; if the test item is short circuit between bus signals and the test mode is a post-operation short circuit mode, when the voltage of a target power interface on the optical fiber interface unit is higher than a fourth threshold value, starting delay timing, and when the delay timing reaches the fourth delay time, controlling a fourth error injection unit to short circuit a data signal interface of the optical fiber interface unit and a clock signal interface of the optical fiber interface unit.

The invention provides a fault injection test fixture, which comprises: the device comprises a main control unit, an isolation unit, an interface unit, a USB port test unit, an optical fiber port test unit and a power supply unit; the main control unit is respectively connected with the isolation unit, the interface unit, the USB port test unit and the power supply unit; the isolation unit is also connected with the interface unit; the interface unit is also connected with the optical fiber port testing unit; the main control unit is used for issuing error injection instructions to the isolation unit, the optical fiber port test unit and the USB port test unit; the isolation unit is used for cutting off a connection channel between a bus signal interface of the main control unit and the interface unit when the optical fiber port test unit simulates a bus short circuit according to an error injection instruction issued by the main control unit; the USB port test unit is used for connecting a USB port of the switch and simulating the power supply overcurrent of the USB port according to the fault injection instruction issued by the main control unit; the optical fiber port test unit is used for connecting the optical fiber port of the switch and simulating the overcurrent of the optical fiber port power supply and the short circuit of the bus according to the fault injection instruction issued by the main control unit.

Therefore, the fault injection test fixture provided by the invention can simulate the power supply overcurrent of the USB port through the USB port test unit and simulate the power supply overcurrent of the optical fiber port and the bus short circuit through the optical fiber port test unit on the basis of power supply of the power supply unit, so that the power supply overcurrent test and the bus signal short circuit test of the optical fiber port of the switch can be automatically completed, the power supply overcurrent test of the USB port of the switch is improved, the test efficiency is improved, and the labor is saved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a test fixture according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another test fixture according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a first isolation unit and a second error injection unit according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a second isolation unit and a third error injection unit according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a first error injection unit according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a fourth error injection unit according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a fifth error injection unit according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a sixth error injection unit according to an embodiment of the present application.

Detailed Description

The invention provides an error injection test fixture which can automatically complete power supply overcurrent test and bus signal short circuit test of an optical fiber port of a switch, and power supply overcurrent test of a USB port of the switch, so that the test efficiency is improved, and the labor is saved.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, fig. 1 is a schematic diagram of an error injection test fixture according to an embodiment of the invention, and referring to fig. 1, the error injection test fixture includes:

the device comprises a main control unit 10, an isolation unit 20, an interface unit 30, a USB port test unit 40, an optical fiber port test unit 50 and a power supply unit 60; the main control unit 10 is respectively connected with the isolation unit 20, the interface unit 30, the USB port test unit 40 and the power supply unit 60; the isolation unit 20 is also connected to the interface unit 30; the interface unit 30 is further connected to the optical fiber port test unit 50;

the main control unit 10 is configured to issue a fault injection instruction to the isolation unit 20, the optical fiber port test unit 50, and the USB port test unit 40;

the isolation unit 20 is configured to cut off a connection channel between a bus signal interface of the main control unit 10 and the interface unit 30 when the optical fiber port test unit 50 simulates a bus short circuit according to an error injection instruction issued by the main control unit 10;

the USB port test unit 40 is configured to connect to a USB port of the switch, and simulate a USB port power supply overcurrent according to an error injection instruction issued by the main control unit 10;

The optical fiber port test unit 50 is configured to connect to an optical fiber port of the switch, and simulate an over-current of an optical fiber port power supply and a short circuit of a bus according to an error injection command issued by the main control unit 10.

In some embodiments, further comprising:

and the display unit is used for displaying the data detected in the fault injection test process. It is to be understood that, in addition to the manner of setting the display unit by using the fault injection test fixture and displaying the data (current data, voltage data, etc.) detected during the fault injection test by the display unit, other manners may be used to display the data detected during the fault injection test. For example, data detected during the fault injection test may be sent to other devices for display. The data detected in the error injection test process can be stored, and the data can be read from the error injection test jig and displayed on other devices.

The main control unit 10 can be any embedded control chip. For example, the main control unit 10 is an STM32F103RBT6 chip. The code inside the main control unit 10 includes a display control module and a logic control module. The display control module is used for carrying out data interaction with the display unit. The logic control module is used for issuing error injection instructions to realize error injection tests of the switch optical fiber port power supply signals, bus signals and USB port power supply signals.

The isolation unit 20 is responsible for cutting off the connection channel between the bus signal interface of the main control unit 10 and the interface unit 30 when the optical fiber port test unit 50 simulates a bus short circuit according to the error injection instruction issued by the main control unit 10.

Referring to fig. 2, in some embodiments, the isolation unit 20 includes:

the first isolation unit is used for cutting off a connection channel between a data signal interface of the main control unit 10 and the interface unit 30 when the optical fiber port test unit simulates a data signal short circuit according to an error injection instruction issued by the main control unit 10;

and the second isolation unit is used for cutting off a connection channel between a clock signal interface of the main control unit 10 and the interface unit 30 when the analog clock signal of the optical fiber port test unit is short-circuited according to the error injection instruction issued by the main control unit 10.

The first isolation units are respectively connected with the data signal interface of the main control unit 10 and the interface unit 30. In addition, the first isolation unit is connected with one path of GPIO interface of the main control unit 10. Illustratively, the first isolation unit is connected to gpio_0 of the master unit 10. The main control unit 10 controls the first isolation unit through the gpio_0, so that the first isolation unit switches on or off a connection channel between a data signal interface of the main control unit 10 and the interface unit 30.

The second isolation units are respectively connected with the clock signal interface of the main control unit 10 and the interface unit 30. In addition, the second isolation unit is connected with one path of GPIO interface of the main control unit 10. Illustratively, the second isolation unit is connected to gpio_6 of the master unit 10. The main control unit 10 controls the second isolation unit through the gpio_6, so that the second isolation unit switches on or switches off a connection channel between the clock signal interface of the main control unit 10 and the interface unit 30.

The first isolation unit and the second isolation unit are used for isolating the bus data signal and the bus clock signal, and can be any chip with an isolation function. For example, the first isolation unit and the second isolation unit are PCA9511 chips, which can disconnect the signal connection between the main control unit 10 and the optical fiber port of the switch during the bus signal short circuit test, so as to avoid the damage to the main control unit 10 in the fault scenario of the bus signal short circuit to the power source or the ground.

Referring to fig. 3, in some embodiments, the first isolation unit includes:

a first switch; the first switch is respectively connected with a data signal interface of the main control unit 10 and the interface unit 30; when the main control unit 10 enables the first switch, the data signal interface of the main control unit 10 is disconnected from the connection channel of the interface unit 30.

The first switches are respectively connected with the data signal interface of the main control unit 10 and the interface unit 30. In addition, the enabling end of the first switch is connected with one path of GPIO interface of the main control unit 10. Illustratively, the enable terminal of the first switch is connected to gpio_0 of the master control unit 10. The main control unit 10 controls the first switch through the gpio_0 to enable the first switch to switch on or off a connection channel between the data signal interface of the main control unit 10 and the interface unit 30.

Referring to fig. 4, in some embodiments, the second isolation unit includes:

a second switch; the second switch is respectively connected with the clock signal interface of the main control unit 10 and the interface unit 30; when the master control unit 10 enables the second switch, the clock signal interface of the master control unit 10 is disconnected from the connection channel of the interface unit 30.

The second switches are respectively connected with the clock signal interface of the main control unit 10 and the interface unit 30. In addition, the enabling end of the second switch is connected with one path of GPIO interface of the main control unit 10. Illustratively, the enable terminal of the second switch is connected to gpio_6 of the master control unit 10. The main control unit 10 controls the second switch through the gpio_6, so that the second switch switches on or off a connection channel between the clock signal interface of the main control unit 10 and the interface unit 30.

The interface unit 30 is an arbitrary connector. In order to ensure reliable connection with the optical fiber port testing unit 50, the interface unit 30 may be a connector with Latch locking function.

Referring to FIG. 2, in some embodiments, the USB port test unit 40 includes:

the first error injection unit is used for simulating the power supply overcurrent of the USB port.

Wherein, referring to fig. 5, in some embodiments, the first error injection unit includes:

a plurality of first load circuits and a first voltage and current detection circuit; the first load circuit is respectively connected with the main control unit 10 and the power interface of the USB interface unit;

the first load circuit is used for providing load current;

the first voltage and current detection circuit is configured to detect a current and a voltage of a power interface of the USB interface unit and feed back the detected current and voltage to the main control unit 10.

Each first load circuit can provide a load current with a preset magnitude. Illustratively, each first load circuit provides a load current of 0.25A. The main control unit 10 selects a certain number of first load circuits to provide load current according to the configured overcurrent level. The first voltage and current detection circuit detects the load current and voltage value of the 5V-USB interface of the USB interface unit in real time, and feeds the load current and voltage value back to the main control unit 10, and can be displayed on the display unit.

The first load circuit may include a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide semiconductor field effect transistor) transistor and a resistor. According to the configured overcurrent, the main control unit 10 selectively conducts a certain number of MOS tubes, and then the first load circuit conducted by the MOS tubes provides load current.

Referring to fig. 2, in some embodiments, the fiber port test unit 50 includes:

The optical fiber interface unit is connected with an optical fiber port of the switch. The optical fiber interface unit is matched with an optical fiber port of the switch. The optical fiber interface unit may be an SFP (SMALL FORM FACTOR PLUGGABLE, small Form-factor Pluggable) optical fiber interface, a QSFP (Quad Small Form-factor Pluggable) optical fiber interface, a QSFP-DD (Quad Small Form-factor Pluggable Double Density, dual-density four-channel Small Form-Pluggable) optical fiber interface, or the like, to adapt to the testing of different types of optical fiber ports.

The second error injection unit is respectively connected with the interface unit 30 and the optical fiber interface unit, and the first error injection unit is connected with the first isolation unit and the main control unit 10 through the interface unit 30. The second error injection unit is used for shorting the data signal interface of the optical fiber interface unit, so that the data signal interface of the optical fiber interface unit can be shorted to a power supply, and the data signal interface of the optical fiber interface unit can be shorted to the ground.

The third error injection unit is respectively connected with the interface unit 30 and the optical fiber interface unit, and is connected with the second isolation unit and the main control unit 10 through the interface unit 30. The second error injection unit is used for shorting the clock signal interface of the optical fiber interface unit, so that the clock signal interface of the optical fiber interface unit can be shorted to a power supply, and the clock signal interface of the optical fiber interface unit can be shorted to the ground.

The fourth error injection unit is connected with the interface unit 30 and the optical fiber interface unit, and is connected with the main control unit 10 through the interface unit 30. And the fourth error injection unit is used for shorting the data signal interface of the optical fiber interface unit and the clock signal interface of the optical fiber interface unit.

The fifth error injection unit is connected with the interface unit 30 and the first power interface of the optical fiber interface unit, and is connected with the main control unit 10 through the interface unit 30. The fifth error injection unit is used for simulating the first power supply overcurrent of the optical fiber port.

The sixth error injection unit is connected to the interface unit 30 and the second power interface of the optical fiber interface unit, and is connected to the main control unit 10 via the interface unit 30. The sixth error injection unit is used for simulating the second power supply overcurrent of the optical fiber port.

Illustratively, the first power interface is a VCCR (receive part power) power interface of the SFP fiber optic interface and the second power interface is a VCCT (transmit part power) power interface of the SFP fiber optic interface.

Referring to fig. 3, in some embodiments, the second error injection unit includes:

a first transistor Q1, a second transistor Q2, a third transistor Q3, and a first resistor R1; the first end of the first transistor Q1 is connected to the master control unit 10, the second end of the first transistor Q1 is grounded, the third end of the first transistor Q1 is connected to one end of the first resistor R1 and the first end of the second transistor Q2, the other end of the first resistor R1 is connected to a power supply, the second end of the second transistor Q2 is connected to a data signal interface of the optical fiber interface unit, the third end of the second transistor Q2 is connected to a power supply, the first end of the third transistor Q3 is connected to the master control unit 10, the second end of the third transistor Q3 is grounded, and the third end of the third transistor Q3 is connected to a data signal interface of the optical fiber interface unit.

The first transistor Q1, the second transistor Q2, and the third transistor Q3 may be NMOS transistors. The first end of the transistor is the grid electrode of the NMOS tube, the second end of the transistor is the source electrode of the NMOS tube, and the third end of the transistor is the drain electrode of the NMOS tube.

Illustratively, the first terminal of the first transistor Q1 is connected to the gpio_2 of the master unit 10, and the first terminal of the third transistor Q3 is connected to the gpio_1 of the master unit 10. GPIO_2 defaults to high and GPIO_1 defaults to low, thereby disconnecting the data signal interface of the fiber interface unit from the VCCR power supply and ground. When the GPIO_2 outputs a low level, the data signal interface of the optical fiber interface unit is short-circuited to the VCCR power supply. When the GPIO_1 outputs high level, the data signal interface of the optical fiber interface unit is short-circuited to the ground.

Referring to fig. 4, in some embodiments, the third error injection unit includes:

a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, and a second resistor R2; the first end of the fourth transistor Q4 is connected to the master control unit 10, the second end of the fourth transistor Q4 is grounded, the third end of the fourth transistor Q4 is connected to one end of the second resistor R2 and the first end of the fifth transistor Q5, the other end of the second resistor R2 is connected to a power supply, the second end of the fifth transistor Q5 is connected to a clock signal interface of the optical fiber interface unit, the third end of the fifth transistor Q5 is connected to a power supply, the first end of the sixth transistor Q6 is connected to the master control unit 10, the second end of the sixth transistor Q6 is grounded, and the third end of the sixth transistor Q6 is connected to a clock signal interface of the optical fiber interface unit.

The fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 may be NMOS transistors. The first end of the transistor is the grid electrode of the NMOS tube, the second end of the transistor is the source electrode of the NMOS tube, and the third end of the transistor is the drain electrode of the NMOS tube.

Illustratively, the first terminal of the fourth transistor Q4 is connected to the gpio_5 of the master unit 10, and the first terminal of the sixth transistor Q6 is connected to the gpio_4 of the master unit 10. Gpio_5 defaults to high and gpio_4 defaults to low, thereby disconnecting the clock signal interface of the fiber interface unit from the VCCR power supply and ground. When the GPIO_5 outputs a low level, the clock signal interface of the optical fiber interface unit is short-circuited to the VCCR power supply. When the GPIO_4 outputs high level, the clock signal interface of the optical fiber interface unit is short-circuited to the ground.

The fourth error injection unit can be any chip with a switching function.

Referring to fig. 6, in some embodiments, the fourth error injection unit includes:

a third switch; the third switch connects the interface unit 30, the data signal interface of the optical fiber interface unit and the clock signal interface of the optical fiber interface unit; when the master control unit 10 enables the third switch, the third switch shorts the data signal interface of the optical fiber interface unit with the clock signal interface of the optical fiber interface unit.

The third switch is connected to the interface unit 30, and is connected to the main control unit 10 via the interface unit 30. The third switching unit is illustratively connected to gpio_3 of the master unit 10 via the interface unit 30. The GPIO_3 outputs a low level by default, at the moment, the third switch is not closed, and the data signal interface of the optical fiber interface unit is disconnected with the clock signal interface of the optical fiber interface unit. When the GPIO_3 outputs high level, enabling the third switch, closing the third switch, and shorting the data signal interface of the optical fiber interface unit with the clock signal interface of the optical fiber interface unit.

Referring to fig. 7, in some embodiments, the fifth error injection unit includes:

a plurality of second load circuits and a second voltage and current detection circuit; the second load circuit connects the interface unit 30 with the first power interface of the optical fiber interface unit;

the second load circuit is used for providing load current;

the second voltage and current detection circuit is configured to detect a current and a voltage of the first power interface of the optical fiber interface unit, and feed back the detected current and voltage to the main control unit 10.

Each path of second load circuit can provide load current with preset magnitude. Illustratively, each second load circuit provides a load current of 0.33A. The main control unit 10 selectively conducts a certain number of second load circuits to provide load current according to the configured overcurrent level. The second voltage and current detection circuit detects the current and voltage of the first power interface of the optical fiber interface unit in real time, and feeds back the current and voltage to the main control unit 10, and can display the current and voltage on the display unit.

The second load circuit may include a MOS transistor and a resistor. According to the configured overcurrent, the main control unit 10 selects and conducts a certain number of MOS tubes. The first power interface is a VCCR power interface, vccr=3.3v, and the resistance value of the resistor is 10Ω. The second load circuit may provide a load current of 0.33A.

Referring to fig. 8, in some embodiments, the sixth error injection unit includes:

a plurality of third load circuits and a third voltage and current detection circuit; the third load circuit connects the interface unit 30 with a second power interface of the optical fiber interface unit;

the third load circuit is used for providing load current;

the third voltage and current detection circuit is configured to detect a current and a voltage of the second power interface of the optical fiber interface unit, and feed back the detected current and voltage to the main control unit 10.

Each third load circuit can provide a load current with a preset magnitude. Illustratively, each third load circuit provides a load current of 0.33A. The main control unit 10 selectively conducts a certain number of third load circuits to provide load current according to the configured overcurrent level. The third voltage and current detection circuit detects the current and voltage of the second power interface of the optical fiber interface unit in real time, and feeds the current and voltage back to the main control unit 10, and can display the current and voltage on the display unit.

The third load circuit may include a MOS transistor and a resistor. According to the configured overcurrent, the main control unit 10 selects and conducts a certain number of MOS tubes. The second power interface is an VCCT power interface, vcct=3.3v, and the resistance value of the resistor is 10Ω. The third load circuit may provide a load current of 0.33A.

In some embodiments, the display unit is further configured to: and sending an operation instruction input by a user for controlling the display unit to the main control unit 10, so that the main control unit 10 issues a misinjection instruction according to the operation instruction.

The display unit can be an LCD touch screen of the UART interface, and a user can input operation instructions through the LCD touch screen, and the LCD touch screen transmits the operation instructions to the main control equipment.

The power supply unit 60 is responsible for supplying power. In some embodiments, the power supply unit 60 includes:

and the voltage conversion unit is used for performing voltage conversion.

Wherein, in some embodiments, the input power switching unit comprises:

In this embodiment, the input power switching unit includes a diode connected to a common cathode, and utilizes the reverse non-conductive characteristic of the diode to automatically input the voltage at the higher end of the voltage as the cathode output, so as to realize automatic switching between the external dc voltage and the internal battery voltage. The voltage conversion unit performs voltage conversion to obtain 9V voltage, 5V voltage and 3.3V voltage, and supplies power to the display unit, the main control unit 10 and the like.

In some embodiments, further comprising:

The storage unit can be a Flash storage chip of any signal. The memory unit is an exemplary GD25B512MEFFRR Flash memory chip.

In some embodiments, the master control unit 10 is specifically configured to: when the error injection test is carried out on the USB port of the switch, if the test mode is a forced overcurrent test, selecting a target number of first load circuits to provide load current according to the configured overcurrent; if the test mode is the post-working overcurrent test, when the voltage of the power interface of the USB interface unit is higher than a first threshold value, starting delay timing, and when the delay timing reaches the first delay time, selecting a target number of first load circuits to provide load current according to the configured overcurrent.

The magnitude of the overcurrent may be configured by the display unit. For example, as shown in fig. 5, after each GPIO in gpio_e to gpio_e+y is pulled high, the corresponding MOS transistor is turned on to provide a load current of 0.25A. If the test mode is the forced overcurrent test, the main control unit 10 selects and conducts the MOS tubes with corresponding quantity according to the configured overcurrent. If the test mode is the post-operation overcurrent test, the main control unit 10 reads the voltage value of the 5V-USB interface detected by the first voltage and current detection circuit in real time through an I2C (Inter-Integrated Circuit, integrated circuit bus) interface, and starts delay timing when the voltage of the 5V-USB interface is higher than a first threshold value. When the delay time reaches the first delay time, the main control unit 10 selects and conducts the MOS tubes with corresponding quantity according to the configured overcurrent.

In some embodiments, the master control unit 10 is specifically configured to: when the optical fiber port of the switch is subjected to fault injection test, if the test item is a power supply test and the test mode is a forced overcurrent mode, selecting a target number of corresponding load circuits to provide load current according to the configured overcurrent; if the test item is a power supply test and the test mode is a post-operation overcurrent test, when the voltage of the power supply interface of the optical fiber interface unit is higher than a second threshold value, starting delay timing, and when the delay timing reaches the second delay time, selecting a target number of corresponding load circuits to provide load current according to the configured overcurrent.

For example, the fiber optic interface unit is an SFP fiber optic interface unit. The power interface includes a VCCR power interface and a VCCT power interface. When the test item is VCCR power supply test and the test mode is forced overcurrent mode, selecting a corresponding number of second load circuits to provide load current according to the configured overcurrent. When the test item is the VCCR power supply test and the test mode is the post-operation overcurrent test, the main control unit 10 reads the voltage value of the VCCR power supply interface detected by the second voltage and current detection circuit in real time through the I2C interface. When the voltage of the VCCR power interface is higher than a second threshold value, starting delay timing, and when the delay timing reaches the second delay time, selecting a corresponding number of second load circuits to provide load current according to the configured overcurrent. When the test item is VCCT power supply test and the test mode is forced overcurrent mode, selecting a corresponding number of third load circuits to provide load current according to the configured overcurrent magnitude. When the test item is the VCCT power supply test and the test mode is the post-operation overcurrent test, the main control unit 10 reads the voltage value of the VCCT power supply interface detected by the third voltage and current detection circuit in real time through the I2C interface. When the voltage of the VCCT power supply interface is higher than a second threshold value, starting delay timing, and when the delay timing reaches the second delay time, selecting a corresponding number of third load circuits to provide load current according to the configured overcurrent magnitude.

The second threshold value during VCCR power supply test may be equal to or different from the second threshold value during VCCT power supply test. The second delay time during VCCR power test may be equal to or different from the second delay time during VCCT power test.

In some embodiments, the master control unit 10 is specifically configured to: when the optical fiber port of the switch is subjected to fault injection test, if the test item is that a bus signal is short-circuited to a short-circuit point and the test mode is a forced short-circuit mode, the corresponding switch is controlled to be disconnected, and the corresponding fault injection unit is controlled to enable the bus signal interface of the optical fiber interface unit to be short-circuited to the short-circuit point; if the test item is that the bus signal is short-circuited to a short-circuit point and the test mode is a working short-circuit mode, starting delay timing when the voltage of a target power interface on the optical fiber interface unit is higher than a third threshold value, controlling a corresponding switch to be disconnected when the delay timing reaches the third delay time, and controlling a corresponding error injection unit to enable the bus signal interface of the optical fiber interface unit to be short-circuited to the short-circuit point; the shorting point includes a power supply and ground.

Taking the short-circuit point as the VCCR power supply as an example, if the data signal is shorted to the VCCR power supply and the test mode is the forced short-circuit mode, the main control unit 10 controls the first switch to be turned off and controls the second error injection unit to short-circuit the data signal interface of the optical fiber interface unit to the VCCR power supply. If the test item is that the data signal is short-circuited to the VCCR power supply and the test mode is short-circuited after operation, when the voltage of the VCCR power supply interface on the optical fiber interface unit is higher than a third threshold value, starting delay timing, and when the delay timing reaches the third delay time, controlling the first switch to be disconnected, and controlling the second error injection unit to short-circuit the data signal interface to the VCCR power supply.

If the clock signal is shorted to the VCCR power source and the test mode is the forced short circuit mode, the main control unit 10 controls the second switch to be turned off and controls the third error injection unit to short-circuit the data signal interface of the optical fiber interface unit to the VCCR power source. If the test item is that the clock signal is short-circuited to the VCCR power supply and the test mode is short-circuited after operation, when the voltage of the VCCR power supply interface on the optical fiber interface unit is higher than a third threshold value, starting delay timing, and when the delay timing reaches the third delay time, controlling the second switch to be disconnected, and controlling the third error injection unit to short-circuit the clock signal interface to the VCCR power supply.

In some embodiments, the master control unit 10 is specifically configured to: when the optical fiber port of the switch is subjected to fault injection test, if the test item is short circuit among bus signals and the test mode is forced short circuit mode, controlling a fourth fault injection unit to short circuit a data signal interface of the optical fiber interface unit and a clock signal interface of the optical fiber interface unit; if the test item is short circuit between bus signals and the test mode is a post-operation short circuit mode, when the voltage of a target power interface on the optical fiber interface unit is higher than a fourth threshold value, starting delay timing, and when the delay timing reaches the fourth delay time, controlling a fourth error injection unit to short circuit a data signal interface of the optical fiber interface unit and a clock signal interface of the optical fiber interface unit.

If the data signal and the clock signal are short-circuited and the test mode is the forced short-circuit mode, the master control unit 10 controls the fourth error injection unit to short-circuit the data signal interface of the optical fiber interface unit and the clock signal interface of the optical fiber interface unit. Taking a target power interface as a VCCR power interface as an example, if a data signal and a clock signal are short-circuited and a test mode is a working short-circuited mode, when the voltage of the VCCR power interface on the optical fiber interface unit is higher than a fourth threshold value, starting delay timing, and when the delay timing reaches the fourth delay time, controlling a fourth error injection unit to short-circuit the data signal interface of the optical fiber interface unit and the clock signal interface of the optical fiber interface unit.

Taking the optical fiber interface unit as an SFP interface as an example, the process of performing the fault injection test by using the fault injection test fixture may include:

(1) Starting the test fixture, and entering the step (2).

(2) A test port is selected. If the test USB port is selected, go to step (3). If the test SFP port is selected, step (9) is entered.

(3) A test mode is selected. If the forced overcurrent mode is selected, i.e. the forced overcurrent test is performed on the USB port, step (4) is entered. If the post-operation overcurrent mode is selected, namely, the overcurrent test is carried out on the USB port in the working state, the step (6) is carried out.

(4) Depending on the USB port type (USB 2.0 or USB3.0, etc.), the user may configure the magnitude of the over-current through the interface of the display unit and then proceed to step (5).

(5) MOS tube conduction in the error injection unit can provide 0.25A load current. And (3) automatically switching on corresponding quantity of MOS (metal oxide semiconductor) tubes by the fault injection test jig according to the magnitude of the overcurrent configured in the step (4), thereby providing the overcurrent with the required magnitude. Meanwhile, the first voltage and current detection circuit detects the load current of the 5V-USB interface of the USB interface unit in real time, displays the load current through the display unit and enters the step (35).

(6) According to the type of the USB port (USB 2.0 or USB3.0, etc.), configuring the size of the overcurrent through a display interface, configuring a delay time T0, namely configuring how long the 5V-USB interface is powered on, starting the overcurrent, and then entering the step (7).

(7) The main control unit reads the voltage value of the 5V-USB interface through the I2C interface (I2C 2) in real time, starts to start delay time counting after the voltage of the 5V-USB interface is higher than a threshold (the threshold is configurable, for example, the threshold is 4.7V), and enters the step (8).

(8) When the delay time is equal to T0, the fault injection test fixture automatically selects and conducts MOS tubes with corresponding numbers according to the magnitude of the overcurrent configured in the step (6), and meanwhile, the first voltage and current detection circuit detects the load current of the 5V-USB interface in real time, displays the load current through the display unit, and enters the step (35).

(9) Test items are selected. If VCCR power supply test is selected, step (10) is entered, and if I2C signal test is selected, step (16) is entered.

(10) A test mode is selected. If the VCCR power supply is subjected to the forced overcurrent mode test, step (11) is entered. If the VCCR power supply is tested for overcurrent in the working state, the step (13) is entered.

(11) And (3) according to the actual working current of the VCCR power supply, configuring the overcurrent level through the interface of the display unit, and entering the step (12).

(12) After each of the gpios_a to gpios_a+x is pulled high, the corresponding MOS transistor is turned on to provide a load current of 0.33A (vccr=3.3v). And (3) automatically selecting and conducting the corresponding number of MOS tubes by the fault injection test jig according to the magnitude of the overcurrent configured in the step (11). Meanwhile, the second voltage and current detection circuit detects the load current of the VCCR power supply interface in real time, and displays the load current through the display unit, and the step (35) is entered.

(13) And (4) according to the actual working current of the VCCR power supply, configuring the overcurrent through an interface of the display unit, and configuring the delay time T1, namely configuring how long the VCCR power supply interface is powered on, starting overcurrent, and entering the step (14).

(14) The main control unit reads the voltage value of the VCCR power supply interface detected by the second voltage and current detection circuit in real time through the I2C interface (I2C 0), and starts to start delay time counting after the voltage value of the VCCR power supply interface is higher than a threshold value (the threshold value is configurable, for example, the threshold value is 3V), and then the step (15) is started.

(15) When the delay time is equal to T1, the fault injection test fixture automatically selects and conducts MOS tubes with corresponding numbers according to the magnitude of the overcurrent configured in the step (13), and meanwhile, the second voltage current detection circuit detects the load current of the VCCR power supply interface in real time, displays the load current through the unit, and enters the step (35).

(16) An I2C signal test sub-item is selected. If the I2C signal is shorted to power test, step (17) is entered. If an inter-I2C signal short circuit test is performed, step (29) is entered.

(17) Taking the data signal as an example, the gpio_2 outputs a high level by default, the gpio_1 outputs a low level by default, the SDA signal is disconnected from the VCCR power supply and GND, and the process proceeds to step (18).

(18) A short circuit point is selected. If a short to VCCR power supply is selected, step (19) is entered. If a short to Ground (GND) is selected, step (24) is entered.

(19) A test mode is selected. If a forced short test is selected, step (20) is entered. If the post-operation short circuit test is selected, step (21) is entered.

(20) The first switch is turned off, the GPIO_2 output is low, the SDA signal is shorted to the VCCR power supply, and step (35) is entered.

(21) The delay time T2 is configured and the process proceeds to step (22).

(22) The main control unit reads the voltage value of the VCCR power supply interface detected by the second voltage and current detection circuit through the I2C interface (I2C 0) in real time, and starts to start delay time counting after the voltage of the VCCR power supply interface is higher than a threshold value (the threshold value is configurable, for example, the threshold value is 3V), and then the step (23) is started.

(23) When the delay time is equal to T2, the first switch is turned off, and at the same time, gpio_2 outputs a low level, and the SDA signal is shorted to the VCCR power supply (in the delay time, the switch can normally access the interface of the main control unit I2C to simulate the abnormal short circuit of the switch I2C signal in the normal working state), and step (35) is entered.

(24) A test mode is selected. If the forced short test is selected, step (25) is entered. If the post-operation short circuit test is selected, step (26) is entered.

(25) The first switch is turned off, the GPIO_1 outputs a high level, the SDA signal is shorted to GND, and the process proceeds to step (35).

(26) A delay time T3 is configured and step (27) is entered.

(27) The main control unit starts to start delay time counting after the voltage of the VCCR power supply interface is higher than a threshold (the threshold is configurable, for example, the threshold is 3V) through the voltage value of the VCCR power supply interface detected by the I2C interface (I2C 0) real-time second reading voltage and current detection unit, and then the step (28) is started.

(28) When the delay time is equal to T3, the first switch is turned off, and at the same time, gpio_1 outputs a high level, and the SDA signal is shorted to GND (in the delay time, the switch can normally access the interface of the main control unit I2C to simulate the abnormal short circuit of the switch I2C signal in the normal working state), and step (35) is entered.

(29) GPIO_3 outputs a low level by default, SDA is disconnected from SCL, and step (30) is entered.

(30) A test mode is selected. If the forced short test is selected, step (31) is entered. If the post-operation short circuit test is selected, step (32) is entered.

(31) GPIO_3 outputs a high level, SDA and SCL are shorted, and step (35) is entered.

(32) The delay time T4 is set and the process proceeds to step (33).

(33) The main control unit reads the voltage value of the VCCR power interface detected by the second voltage-current detection circuit in real time through the I2C interface (I2C 0), and starts to start delay time counting after the voltage of the VCCR power interface is higher than a threshold (the threshold is configurable, for example, the threshold is 3V), and then step (34) is entered.

(34) When the delay time is equal to T4, gpio_3 outputs a high level, and SDA and SCL are shorted (during the delay time, the switch can normally access the interface of the master control unit I2C to simulate the short circuit abnormality of the switch I2C signal in the normal working state), and step (35) is entered.

(35) If the test is to be ended, the process proceeds to step (36). Otherwise, returning to the step (2).

(36) And (5) ending the test.

In summary, according to the fault injection test fixture provided by the invention, on the basis of power supply of the power supply unit, the USB port power supply overcurrent can be simulated through the USB port test unit, and the optical fiber port power supply overcurrent and bus short circuit can be simulated through the optical fiber port test unit, so that the power supply overcurrent test and the bus signal short circuit test of the optical fiber port of the switch can be automatically completed, the power supply overcurrent test of the USB port of the switch can be promoted, the test efficiency can be improved, and the labor can be saved. Meanwhile, the fault injection test fixture can also detect the power supply current of the optical fiber port, so that a designer can more accurately check when the port protection function is effective.

Because of the complexity and cannot be illustrated by a list, those skilled in the art will recognize that many examples are possible in combination with the practical situation under the basic principles of the embodiments provided by the present invention, and should be within the scope of the present invention without performing a sufficient amount of inventive effort.

In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred.

The error injection test fixture provided by the invention is described in detail above. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that the present invention may be modified and practiced without departing from the spirit of the invention.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

Claims

1. Annotate wrong test fixture, its characterized in that includes:

the optical fiber port test unit is used for connecting the optical fiber port of the switch and simulating the overcurrent of the optical fiber port power supply and the short circuit of the bus according to the fault injection instruction issued by the main control unit;

The USB port test unit includes:

the USB interface unit is used for connecting with a USB port of the switch;

the first error injection unit includes:

the first load circuit is used for providing load current;

the first voltage and current detection circuit is used for detecting the current and the voltage of the power interface of the USB interface unit and feeding the current and the voltage back to the main control unit;

the optical fiber port test unit includes:

2. The fault injection test fixture of claim 1, wherein the isolation unit comprises:

3. The fault injection test fixture of claim 2, wherein the first isolation unit comprises:

4. The fault injection test fixture of claim 2, wherein the second isolation unit comprises:

5. The fault injection test fixture of claim 1, wherein the second fault injection unit comprises:

6. The fault injection test fixture of claim 1, wherein the third fault injection unit comprises:

7. The fault injection test fixture of claim 1, wherein the fourth fault injection unit comprises:

8. The fault injection test fixture of claim 1, wherein the fifth fault injection unit comprises:

the second load circuit is used for providing load current;

9. The fault injection test fixture of claim 1, wherein the sixth fault injection unit comprises:

the third load circuit is used for providing load current;

10. The fault injection test fixture of claim 1, further comprising:

11. The fault injection test fixture of claim 10, wherein the display unit is further configured to: and sending an operation instruction input by a user for controlling the display unit to the main control unit so that the main control unit issues a wrong injection instruction according to the operation instruction.

12. The fault injection test fixture of claim 1, wherein the power supply unit comprises:

and the voltage conversion unit is used for performing voltage conversion.

13. The fault injection test fixture of claim 12, wherein the input power switching unit comprises:

14. The fault injection test fixture of claim 1, further comprising:

15. The fault injection test fixture of claim 1, wherein the main control unit is specifically configured to: when the error injection test is carried out on the USB port of the switch, if the test mode is a forced overcurrent test, selecting a target number of first load circuits to provide load current according to the configured overcurrent; if the test mode is the post-working overcurrent test, when the voltage of the power interface of the USB interface unit is higher than a first threshold value, starting delay timing, and when the delay timing reaches the first delay time, selecting a target number of first load circuits to provide load current according to the configured overcurrent.

16. The fault injection test fixture of claim 8, wherein the master control unit is specifically configured to: when the optical fiber port of the switch is subjected to fault injection test, if the test item is a power supply test and the test mode is a forced overcurrent mode, selecting a target number of corresponding load circuits to provide load current according to the configured overcurrent; if the test item is a power supply test and the test mode is a post-operation overcurrent test, when the voltage of the power supply interface of the optical fiber interface unit is higher than a second threshold value, starting delay timing, and when the delay timing reaches the second delay time, selecting a target number of corresponding load circuits to provide load current according to the configured overcurrent.

17. The fault injection test fixture of claim 1, wherein the main control unit is specifically configured to: when the optical fiber port of the switch is subjected to fault injection test, if the test item is that a bus signal is short-circuited to a short-circuit point and the test mode is a forced short-circuit mode, the corresponding switch is controlled to be disconnected, and the corresponding fault injection unit is controlled to enable the bus signal interface of the optical fiber interface unit to be short-circuited to the short-circuit point; if the test item is that the bus signal is short-circuited to a short-circuit point and the test mode is a working short-circuit mode, starting delay timing when the voltage of a target power interface on the optical fiber interface unit is higher than a third threshold value, controlling a corresponding switch to be disconnected when the delay timing reaches the third delay time, and controlling a corresponding error injection unit to enable the bus signal interface of the optical fiber interface unit to be short-circuited to the short-circuit point; the shorting point includes a power supply and ground.

18. The fault injection test fixture of claim 1, wherein the main control unit is specifically configured to: when the optical fiber port of the switch is subjected to fault injection test, if the test item is short circuit among bus signals and the test mode is forced short circuit mode, controlling a fourth fault injection unit to short circuit a data signal interface of the optical fiber interface unit and a clock signal interface of the optical fiber interface unit; if the test item is short circuit between bus signals and the test mode is a post-operation short circuit mode, when the voltage of a target power interface on the optical fiber interface unit is higher than a fourth threshold value, starting delay timing, and when the delay timing reaches the fourth delay time, controlling a fourth error injection unit to short circuit a data signal interface of the optical fiber interface unit and a clock signal interface of the optical fiber interface unit.