CN107666307B - USB inserts detection circuitry and USB inserts check out test set - Google Patents
USB inserts detection circuitry and USB inserts check out test set Download PDFInfo
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- CN107666307B CN107666307B CN201710770370.7A CN201710770370A CN107666307B CN 107666307 B CN107666307 B CN 107666307B CN 201710770370 A CN201710770370 A CN 201710770370A CN 107666307 B CN107666307 B CN 107666307B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a USB insertion detection circuit and a USB insertion detection device, comprising: a pulse interrupt unit for generating a pulse interrupt signal when the USB is inserted; a pulse repetition unit for controlling repeated generation of the pulse interrupt signal; an insertion detection unit for detecting an insertion state of the USB; and the Boost activation unit controls the start of a Boost mode according to the pulse interrupt signal generated by the pulse interrupt unit, and simultaneously outputs a voltage signal, wherein the voltage signal is used for controlling the working state of the pulse repetition unit, and the Boost activation unit controls the close of the Boost mode after the Boost mode is started for a preset time. By adopting the embodiment of the invention, a singlechip circuit is not needed for detection, the cost is saved, the phenomenon that a USB line is plugged firstly and a load cannot be detected after a period of time is inserted is avoided, the power chip can be deeply dormant when the Boost mode is turned off at regular time, and the power consumption is very low.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a USB (universal serial bus) insertion detection circuit and USB insertion detection equipment.
Background
The USB insertion detection mechanism is used for inserting the USB device after the test device enters deep sleep with the lowest power consumption, and the test device can recognize insertion through the insertion detection mechanism and successfully wake up. Products with batteries (PowerBank or MIFI) are sensitive to power consumption, and a reliable and easy-to-use plug-in detection circuit is important.
There are two types of USB insertion detection circuits in the prior art:
1. referring to fig. 1, fig. 1 is a circuit structure diagram of a USB detection circuit in the prior art, a single chip microcomputer detects voltages at two ends of a dummy load to determine whether a load is inserted, in the whole process, a USB port periodically outputs 5V, and an ADC of the single chip microcomputer detects voltages at two sides of the dummy load to detect whether a device is inserted into the USB port. The method is simple to implement, but because the singlechip and the Boost circuit are periodically turned on, the static power consumption cannot be the lowest, and the actually measured static power consumption can reach 1-5 mA.
2. Referring to fig. 2, fig. 2 is a circuit structure diagram of another USB detection circuit in the prior art, a USB socket with a load detection pin is adopted, the detection pin is connected to a GPIO port of a single chip, and when a load is inserted, the load detection pin is pulled down to the ground to perform a load detection function. If the USB line is plugged in firstly and then the mobile phone is plugged in after a while, the load insertion cannot be detected, the user experience is not good, the load detection is completed by the single chip microcomputer in the prior art, and the cost is high.
Therefore, a USB insertion detection circuit that can save cost, reduce power consumption, and repeat detection is desired to overcome the above-mentioned drawbacks.
Disclosure of Invention
The embodiment of the invention aims to provide a USB plug-in detection circuit and a USB plug-in detection device, which can effectively save cost and reduce power consumption, and meanwhile, the phenomenon that a USB line is plugged first and a load cannot be detected after a period of time.
To achieve the above object, an embodiment of the present invention provides a USB insertion detection circuit, including: the device comprises a pulse interruption unit, a pulse repetition unit, an insertion detection unit and a Boost activation unit;
a first input end of the pulse interruption unit is connected with an output end of the insertion detection unit, a second input end of the pulse interruption unit is connected with an output end of the pulse repetition unit, and the pulse interruption unit is used for generating a pulse interruption signal;
the input end of the pulse repetition unit is connected with the first output end of the Boost activation unit, and the pulse repetition unit is used for controlling the repeated generation of the pulse interrupt signal;
the insertion detection unit is used for detecting the insertion state of the USB;
the input end of the Boost activation unit is connected with the output end of the pulse interruption unit, the Boost activation unit controls the start of a Boost mode according to the pulse interruption signal generated by the pulse interruption unit, and simultaneously outputs a voltage signal, the voltage signal is used for controlling the working state of the pulse repetition unit, and the Boost activation unit controls the close of the Boost mode after the Boost mode is started for a preset time.
Compared with the prior art, the USB plug-in detection circuit disclosed by the invention generates a pulse interrupt signal through the pulse interrupt unit; the pulse repetition unit controls the repeated generation of the pulse interrupt signal; the insertion detection unit detects the insertion state of the USB; the Boost activation unit controls the start of a Boost mode according to the pulse interruption signal generated by the pulse interruption unit, and simultaneously outputs a voltage signal, wherein the voltage signal is used for controlling the working state of the pulse repetition unit, and the Boost activation unit controls the close of the Boost mode after the Boost mode is started for a preset time. According to the technical scheme, the problems that in the prior art, the cost is high and the power loss is high due to the fact that the single chip microcomputer is needed to perform detection are solved, and meanwhile the problem that the USB is plugged firstly and the load cannot be detected after a period of time is inserted is solved. The invention can effectively save cost, reduce power consumption and avoid the phenomenon that the USB line is plugged first and the load cannot be detected after the USB line is plugged for a while.
As an improvement of the above scheme, the pulse interruption unit includes a first capacitor, a first switch tube, a first resistor, a second resistor, and a third resistor; the first end of the first capacitor is the output end of the pulse interruption unit, and the second end of the first capacitor is connected with the second end of the second resistor; the first end of the first resistor is connected with a power supply end, and the second end of the first resistor is connected with the first end of the first capacitor; the first end of the second resistor is connected with the second end of the first resistor, and the second end of the second resistor is connected with the third end of the first switching tube; the first end of the first switch tube is the second input end of the pulse interruption unit, and the second end of the first switch tube is the first input end of the pulse interruption unit; the first end of the third resistor is connected with the first end of the first switch tube, and the second end of the third resistor is grounded.
As a modification of the above scheme, the pulse repetition unit includes a second switch tube, a fourth resistor, a fifth resistor and a sixth resistor; a first end of the fourth resistor is connected with a power supply end, and a second end of the fourth resistor is an output end of the pulse repeating unit; the third end of the second switch tube is connected with the second end of the first resistor, the second end of the second switch tube is grounded, and the first end of the second switch tube is connected with the second end of the sixth resistor; the first end of the fifth resistor is connected with the first end of the second switching tube, and the second end of the fifth resistor is grounded; the first end of the sixth resistor is the input end of the pulse repetition unit.
Compared with the prior art, the USB plug-in detection circuit disclosed by the invention controls the repeated generation of the pulse interrupt signal through the pulse repetition unit, solves the problem that the USB line is plugged firstly and the load cannot be detected after a period of time, and can repeatedly detect the plug-in condition of the load.
As an improvement of the above scheme, the first switching tube is an N-channel field effect tube, the first end of the first switching tube is a gate of the N-channel field effect tube, the second end of the first switching tube is a source of the N-channel field effect tube, and the third end of the first switching tube is a drain of the N-channel field effect tube; the second switch tube is an N-channel field effect tube, the first end of the second switch tube is a grid electrode of the N-channel field effect tube, the second end of the second switch tube is a source electrode of the N-channel field effect tube, and the third end of the second switch tube is a drain electrode of the N-channel field effect tube.
As an improvement of the above-mentioned solution, the insertion detection unit includes at least one USB female socket chip, a first pin of each USB female socket chip is a first input end of the insertion detection unit, a second pin of each USB female socket chip is a second input end of the insertion detection unit, a third pin of each USB female socket chip is a third input end of the insertion detection unit, a fifth pin and a sixth pin of each USB female socket chip are connected to an output end of the insertion detection unit, and a fourth pin, a seventh pin, an eighth pin, a ninth pin, and a tenth pin of each USB female socket chip are all grounded.
As an improvement of the above scheme, each USB female socket chip further includes a first switch and a second switch; the fifth pin is connected with the first end of the first switch, and the second end of the first switch is grounded; the sixth pin is connected with a first end of the second switch, and a second end of the second switch is grounded.
As an improvement of the above scheme, the Boost activation unit includes a power management chip, a first capacitor module, a second capacitor module, a third capacitor module, a first inductor, a seventh resistor, and an eighth resistor; the fifth pin of the power management chip is connected with the first end of the first capacitor module, the twelfth pin of the power management chip is the input end of the insertion detection unit, the third pin of the power management chip is connected with the first end of the second capacitor module, the fourth pin of the power management chip is connected with the first end of the second capacitor module, a tenth pin of the power management chip is a third output terminal of the Boost activation unit, an eleventh pin of the power management chip is a fourth output end of the Boost activation unit, the second pin of the power management chip is connected with the first end of the first inductor, the twenty-second pin of the power management chip is connected with the second end of the first inductor, a twenty-first pin of the power management chip is connected with a first end of the third capacitor block; the second end of the first capacitor module is a second output end of the Boost activation unit, and the third end of the first capacitor module is grounded; a second end of the second capacitor module is a first output end of the Boost activation unit, and a third end of the second capacitor module is grounded; a second end of the third capacitor module is a fifth output end of the Boost activation unit, and a third end of the third capacitor module is grounded; a first end of the seventh resistor is connected with a second end of the first inductor, and a second end of the seventh resistor is connected with a second end of the third capacitor module; the first end of the eighth resistor is connected with the first end of the seventh resistor, and the second end of the eighth resistor is connected with the second end of the seventh resistor.
Compared with the prior art, the USB plug-in detection circuit disclosed by the embodiment of the invention solves the problem of higher cost caused by the fact that a singlechip is required to detect the pulse interrupt signal by detecting the pulse interrupt signal through the Boost activation unit, and can effectively reduce the cost.
As an improvement of the above scheme, the Boost activation unit further comprises a timer module; when the Boost mode is started, the Boost activation unit controls the timer module to be started, and the timer module controls the Boost mode to be closed after the timer module is started for preset time.
Compared with the prior art, the USB insertion detection circuit disclosed by the embodiment of the invention solves the problem that the static power consumption cannot be minimized due to the fact that the Boost circuit needs to be periodically opened in the prior art by controlling the starting duration of the Boost mode through the timer module, and obtains the beneficial effect of effectively reducing power loss.
As an improvement of the above scheme, the first capacitor module, the second capacitor module and the third capacitor module are respectively formed by combining N capacitors in parallel; n is an integer, and N is greater than or equal to 1.
An embodiment of the present invention provides a USB insertion detection device, including the USB insertion detection circuit according to any one of claims 1 to 9.
Compared with the prior art, the USB plug-in detection equipment disclosed by the embodiment of the invention generates a pulse interrupt signal through the pulse interrupt unit; the pulse repetition unit controls the repeated generation of the pulse interrupt signal; the insertion detection unit detects the insertion state of the USB; the Boost activation unit controls the start of a Boost mode according to the pulse interruption signal generated by the pulse interruption unit, and simultaneously outputs a voltage signal, wherein the voltage signal is used for controlling the working state of the pulse repetition unit, and the Boost activation unit controls the close of the Boost mode after the Boost mode is started for a preset time. According to the technical scheme, the problems that in the prior art, the cost is high and the power loss is high due to the fact that the single chip microcomputer is needed to perform detection are solved, and meanwhile the problem that a USB line is plugged firstly and a load cannot be detected after a period of time is inserted is solved. The invention can effectively save cost, reduce power consumption and avoid the phenomenon that the USB line is plugged first and the load cannot be detected after the USB line is plugged for a while.
Drawings
FIG. 1 is a circuit configuration diagram of a prior art USB insertion detection circuit;
FIG. 2 is a circuit configuration diagram of another prior art USB detection circuit;
FIG. 3 is a block diagram of a USB insertion detection circuit according to an embodiment of the present invention;
FIG. 4 is a circuit configuration diagram of a pulse interruption unit and a pulse repetition unit provided by an embodiment of the present invention;
fig. 5 is a circuit configuration diagram of an insertion detection unit provided in the embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a Boost activation unit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The USB comprises all devices provided with USB plugs; the USB line is a USB line which is provided with a USB plug and does not carry a load; the load includes, but is not limited to, a cell phone, a tablet computer, and a mobile power supply.
Referring to fig. 3, fig. 3 is a circuit block diagram of a USB insertion detection circuit according to an embodiment of the present invention; the embodiment provided by the invention comprises the following steps: an insertion detection unit 100, a pulse interruption unit 200, a pulse repetition unit 300, and a Boost activation unit 400;
a first input terminal IN1 of the pulse interruption unit is connected with an output terminal OUT1 of the insertion detection unit, a second input terminal IN2 of the pulse interruption unit is connected with an output terminal OUT2 of the pulse repetition unit, and the pulse interruption unit 100 is used for generating a pulse interruption signal;
an input end IN3 of the pulse repeating unit is connected with a first output end OUT3 of the Boost activating unit, and the pulse repeating unit 300 is used for controlling repeated generation of the pulse interrupt signal; the pulse interrupt signal is a low-level pulse signal;
the insertion detection unit 100 is used for detecting the insertion state of the USB;
an input end IN4 of the Boost activation unit is connected with an output end OUT4 of the pulse interruption unit, the Boost activation unit 400 controls the start of a Boost mode according to the pulse interruption signal generated by the pulse interruption unit 200, and simultaneously outputs a voltage signal, and the Boost activation unit 400 can start the Boost mode only when detecting a low-level pulse signal; the voltage signal is used for controlling the working state of the pulse repetition unit 300, and the Boost activation unit 400 controls the Boost mode to be closed after the Boost mode is started for a preset time;
in this embodiment, once the USB is plugged into the plug-in detection module, a load output signal of the USB female socket chip J1 is pulled low, and the load output signal is used as a first input signal of the pulse interrupt unit 200; at this time, the pulse interruption unit 200 generates a pulse interruption signal; the Boost activation unit 400 detects the pulse interrupt signal and starts a Boost mode, and outputs a voltage signal after the Boost mode is started, wherein the voltage signal is used as a pulse input signal of the pulse repetition unit 300; the pulse repetition unit 300 is in a working state due to the action of the voltage signal; the pulse interruption unit 100 recovers the normal state of the pulse interruption signal because the pulse repetition unit starts to work; when the Boost mode is turned off, the voltage signal output by the Boost activation unit 400 disappears, the pulse repetition unit 300 does not work due to no input of the voltage signal, and at this time, the pulse repetition unit 300 is in a turned-off state; the pulse interruption unit 200 generates the pulse interruption signal again; therefore, the pulse interrupt signal is generated in a circulating mode to activate the Boost mode, the condition that a load is inserted can be detected even if the load is inserted after the USB line is inserted for a while, and the cost can be effectively saved and the power consumption can be improved by the timed opening and closing of the Boost mode.
Referring to fig. 4, fig. 4 is a circuit configuration diagram of a pulse interruption unit and a pulse repetition unit provided in an embodiment of the present invention; the pulse interruption unit 200 comprises a first capacitor C1, a first switching tube Q1, a first resistor R1, a second resistor R2 and a third resistor R3; a first end of the first capacitor C1 is an output end OUT4 of the pulse interruption unit, and a second end of the first capacitor C1 is connected with a second end of the second resistor R2; a first end of the first resistor R1 is connected to a power supply terminal VCC1, and a second end of the first resistor R1 is connected to a first end of the first capacitor C1; a first end of the second resistor R2 is connected with a second end of the first resistor R1, and a second end of the second resistor R2 is connected with a third end of the first switch tube Q1; the first end of the first switch tube Q1 is the second input end IN2 of the pulse interruption unit, and the second end of the first switch tube Q1 is the first input end IN1 of the pulse interruption unit; a first end of the third resistor R3 is connected to the first end of the first switch Q1, and a second end of the third resistor R3 is grounded.
IN the embodiment, when the pulse interruption unit 200 is not plugged with a USB, the first input terminal IN1 of the pulse interruption unit 200 does not have a first input signal, and at this time, the first switch transistor Q1 is not turned on, the voltage across the first capacitor C1 is zero, and the output signal of the output terminal OUT4 is IN a high-level state due to the existence of the power supply terminal VCC1 and the action of the first resistor R1; the first resistor R1 is a pull-up resistor and plays a role in limiting current; the second resistor R2 is used as a voltage dividing resistor in the circuit and determines the full charge time of the first capacitor C1 together with the first resistor R1; the first switch tube Q1 is provided with a first diode D1, the anode of the first diode D1 is connected with the second end of the first switch tube Q1, the cathode of the first diode D1 is connected with the third end of the first switch tube Q1, and the first diode D1 is a parasitic diode, so that the reverse breakdown action of the first switch tube Q1 can be prevented; the first input signal of the pulse interruption unit 200 outputs a low level signal due to the USB insertion of the USB insertion detection unit 100, and the second switch Q2 of the pulse repetition unit 300 is turned off, so that the input signal of the power source terminal VCC2 of the pulse repetition unit 300 directly acts on the first switch Q1 as the second input signal IN2 of the pulse interruption unit, and the second input signal is greater than the first input signal, at this time, the first switch Q1 is turned on, and the first capacitor C1 starts to charge, so that the pulse interruption signal becomes a low level signal.
The pulse repetition unit 300 includes a second switching tube Q2, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6; a first end of the fourth resistor R4 is connected with a power supply terminal, and a second end of the fourth resistor R4 is an output terminal OUT2 of the pulse repeating unit; the third terminal of the second switch Q2 is connected to the second terminal of the first resistor R1, the second terminal of the second switch Q1 is grounded, and the first terminal of the second switch Q1 is connected to the second terminal of the sixth resistor R6; a first end of the fifth resistor R5 is connected to the first end of the second switch Q2, and a second end of the fifth resistor R5 is grounded; the first end of the sixth resistor R6 is the input end IN3 of the pulse repetition unit.
Preferably, the first switch Q1 is an N-channel fet, the first terminal of the first switch Q1 is a gate of the N-channel fet, the second terminal of the first switch Q1 is a source of the N-channel fet, and the third terminal of the first switch Q1 is a drain of the N-channel fet; the second switch tube Q2 is an N-channel fet, the first end of the second switch tube Q2 is the gate of the N-channel fet, the second end of the second switch tube Q2 is the source of the N-channel fet, and the third end of the second switch tube Q2 is the drain of the N-channel fet.
IN this embodiment, the input terminal IN3 of the pulse repetition unit 300 is turned on by the second switch Q2 under the action of the voltage signal, at this time, the first switch Q1 of the pulse interruption unit 200 turns off the first switch Q1 due to the action of the third resistor R3, the second input signal becomes a low-level signal, the third resistor R3 is a pull-down resistor, the R5 is a pull-down resistor, the sixth resistor R6 is a current-limiting resistor IN the circuit, and the R4 is a pull-up resistor; the second switch tube Q2 is provided with a second diode D2, the anode of the second diode D2 is connected with the second end of the second switch tube Q2, the cathode of the second diode D2 is connected with the third end of the second switch tube Q2, and the second diode D2 is a parasitic diode, which can prevent the reverse breakdown of the second switch tube Q2; after the first switch tube Q1 is turned off, the pulse interruption signal is changed into a high level signal under the action of the first resistor R1 and the power supply terminal VCC1, and the pulse interruption signal is recovered to be normal.
Referring to fig. 5, fig. 5 is a circuit structure diagram of an insertion detection unit according to an embodiment of the present invention; the insertion detection unit 100 comprises at least one USB female socket chip J1, wherein a first pin of each USB female socket chip J1 is a first input end IN5 of the insertion detection unit, a second pin of each USB female socket chip J1 is a second input end IN6 of the insertion detection unit, a third pin of each USB female socket chip J1 is a third input end IN7 of the insertion detection unit, a fifth pin and a sixth pin of each USB female socket chip J1 are connected with an output end OUT1 of the insertion detection unit, and a fourth pin, a seventh pin, an eighth pin, a ninth pin and a tenth pin of each USB female socket chip J1 are grounded. The embodiment shown in fig. 5 employs two USB female socket chips J1, and in other embodiments, different numbers of USB female socket chips J1 are designed according to the requirement, and the invention is also within the protection scope.
Preferably, each of the USB female socket chips J1 further includes a first switch G1 and a second switch G2; the fifth pin is connected with a first end of the first switch G1, and a second end of the first switch G1 is grounded; the sixth pin is connected to a first terminal of the second switch G2, and a second terminal of the second switch G2 is grounded.
In the present embodiment, when there is no USB plug in the USB female socket chip J1, the first switch G1 and the second switch G2 are both in an open state, and the USB female socket chip has no load output signal, and when there is a USB plug in, the first switch G1 and the second switch G2 become a closed state, and the USB plug-in unit generates a load output signal, but since the first switch G1 and the second switch G2 are both grounded, the load output signal is a low level signal, and the load output signal serves as a first input signal of the pulse interrupt unit 200; a first input end IN5 of the USB mother socket chip J1 is connected to a second output end OUT5 of the power management chip MP, a second input end IN6 of the USB mother socket chip J1 is connected to a third output end OUT6 of the power management chip MP, and a third input end IN7 of the power management chip MP is connected to a fourth output end OUT7 of the Boost activation unit.
Referring to fig. 6, fig. 6 is a schematic circuit composition diagram of a Boost activation unit provided by the present invention; the Boost activation unit 400 includes a power management chip MP, a first capacitor module C1, a second capacitor module C2, a third capacitor module C3, a first inductor L1, a seventh resistor R7, and an eighth resistor R8.
The fifth pin of the power management chip MP is connected to the first end of the first capacitor module C1, a twelfth pin of the power management chip MP is an input terminal IN4 of the Boost activation unit, the third pin of the power management chip MP is connected to the first end of the second capacitor module C2, the fourth pin of the power management chip MP is connected to the first end of the second capacitor module C2, a tenth pin of the power management chip MP is a third output terminal OUT6 of the Boost activation unit, an eleventh pin of the power management chip MP is a fourth output terminal OUT7 of the Boost activation unit, the second pin of the power management chip MP is connected to the first end of the first inductor L1, the twenty-second pin of the power management chip MP is connected to the second end of the first inductor L1, the twenty-first pin of the power management chip MP is connected to the first end of the third capacitor block C3; a second end of the first capacitor module C1 is a second output end OUT5 of the Boost activation unit, and a third end of the first capacitor module C1 is grounded; a second end of the second capacitor module C2 is a first output end OUT3 of the Boost activation unit, and a third end of the second capacitor module C2 is grounded; a second end of the third capacitor module C3 is a fifth output end OUT8 of the Boost activation unit, and a third end of the third capacitor module C2 is grounded; a first end of the seventh resistor R7 is connected to the second end of the first inductor L1, and a second end of the seventh resistor R7 is connected to the second end of the third capacitor module C3; a first end of the eighth resistor R8 is connected to a first end of the seventh resistor R7, and a second end of the eighth resistor R8 is connected to a second end of the seventh resistor R7.
Preferably, the first capacitor module 401, the second capacitor module 401 and the third capacitor module 403 are respectively formed by combining N capacitors in parallel; n is an integer, and N is greater than or equal to 1.
Preferably, the power management chip MP further includes a timer module 404; when the Boost mode is started, the Boost activation unit 400 controls the timer module 404 to be started, and the timer module 404 controls the Boost mode to be closed after a preset time is started.
In this embodiment, the power management chip MP takes a power management chip with a model number MP2632 as an example, but in other embodiments, other chips are adopted as the power management chip according to circuit requirements, which is also within the protection scope of the present invention; when the input end IN4 of the Boost activation unit 400 detects a low-level pulse signal, the Boost mode is started, and when the Boost mode is started, the first output end OUT3 outputs a voltage signal, which is an input signal of the pulse repetition unit 300; the timer module 404 is provided with a time limit for starting the Boost mode, and when the time is up, the Boost mode is automatically closed until the input end IN4 detects a low level signal again; after the Boost mode is automatically turned off, the first output end OUT3 does not output the voltage signal to the pulse repetition unit 300, and the second switching tube Q2 of the pulse repetition unit 300 does not work; thereby achieving the effect that the Boost mode is repeatedly activated.
In specific implementation, the USB insertion detection circuit of this embodiment includes: the device comprises a pulse interruption unit, a pulse repetition unit, a USB insertion detection unit and a Boost activation unit; when the insertion detection unit detects that a USB is inserted, the first switch and the second switch are closed, the insertion detection unit generates a load output signal, and the load output signal is used as a first input signal of the pulse interruption unit; at the moment, the pulse repeating unit is in a closed state, and a second switching tube of the pulse repeating unit does not work; the first switch tube of the pulse interruption unit is conducted to generate a pulse interruption signal; the input end of the Boost activation unit detects the pulse interrupt signal, and the Boost mode is started at the moment; after the Boost mode is activated, the Boost activation unit outputs a voltage signal which is used as an input signal of the pulse repetition unit; the pulse repetition unit is conducted by the second switch tube under the action of the voltage signal, and the pulse repetition unit is in a working state at the moment; the second switching tube is conducted to cause the first switching tube to be not conducted, and at the moment, the pulse interruption signal is recovered to be normal; when the timer module of the Boost activation unit is over the preset time, the Boost mode is automatically closed, and the voltage signal disappears; the second switch tube is not conducted, and the pulse repetition unit is in a non-working state; the first switch tube is conducted, and the pulse interruption unit generates a pulse interruption signal again, so that the Boost mode is activated again.
This embodiment has solved and has needed the singlechip to do and detect among the prior art and lead to with high costs and the high problem of power loss, has still solved earlier and has inserted the USB line simultaneously, inserts the unable phenomenon problem that detects of load again for the lag time. The invention can effectively save cost, reduce power consumption and avoid the phenomenon that the USB line is plugged first and the load cannot be detected after the USB line is plugged for a while.
An embodiment of the present invention provides a USB insertion detection device, including the USB insertion detection circuit provided in the embodiment of the present invention, and a specific structure of the USB insertion detection circuit may refer to the description of the USB insertion detection circuit provided in the embodiment of the present invention, which is not described herein again.
In specific implementation, the USB insertion detection device in this embodiment includes: the device comprises a pulse interruption unit, a pulse repetition unit, a USB insertion detection unit and a Boost activation unit; when the insertion detection unit detects that a USB is inserted, the first switch and the second switch are closed, the insertion detection unit generates a load output signal, and the load output signal is used as a first input signal of the pulse interruption unit; at the moment, the pulse repeating unit is in a closed state, and a second switching tube of the pulse repeating unit does not work; the first switch tube of the pulse interruption unit is conducted to generate a pulse interruption signal; the input end of the Boost activation unit detects the pulse interrupt signal, and the Boost mode is started at the moment; after the Boost mode is activated, the Boost activation unit outputs a voltage signal which is used as an input signal of the pulse repetition unit; the pulse repetition unit is conducted by the second switch tube under the action of the voltage signal, and the pulse repetition unit is in a working state at the moment; the second switching tube is conducted to cause the first switching tube to be not conducted, and at the moment, the pulse interruption signal is recovered to be normal; when the timer module of the Boost activation unit is over the preset time, the Boost mode is automatically closed, and the voltage signal disappears; the second switch tube is not conducted, and the pulse repetition unit is in a non-working state; the first switch tube is conducted, and the pulse interruption unit generates a pulse interruption signal again, so that the Boost mode is activated again.
This embodiment has solved and has needed the singlechip to do and detect among the prior art and lead to with high costs and the high problem of power loss, has still solved earlier and has inserted the USB line simultaneously, inserts the unable phenomenon problem that detects of load again for the lag time. The invention can effectively save cost, reduce power consumption and avoid the phenomenon that the USB line is plugged first and the load cannot be detected after the USB line is plugged for a while.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A USB insertion detection circuit, comprising: the device comprises a pulse interruption unit, a pulse repetition unit, an insertion detection unit and a Boost activation unit; the pulse interruption unit comprises a first switch tube, and the pulse repetition unit comprises a second switch tube;
a first input end of the pulse interruption unit is connected with an output end of the insertion detection unit, a second input end of the pulse interruption unit is connected with an output end of the pulse repetition unit, and the pulse interruption unit is used for generating a pulse interruption signal;
the input end of the pulse repetition unit is connected with the first output end of the Boost activation unit, and the pulse repetition unit is used for controlling the repeated generation of the pulse interrupt signal;
the insertion detection unit is used for detecting the insertion state of the USB;
the input end of the Boost activation unit is connected with the output end of the pulse interruption unit, the Boost activation unit controls the start of a Boost mode according to the pulse interruption signal generated by the pulse interruption unit, and simultaneously outputs a voltage signal, the voltage signal is used for controlling the working state in the pulse repetition unit, and the Boost activation unit controls the close of the Boost mode after the Boost mode is started for a preset time.
2. The USB insertion detection circuit of claim 1, wherein the pulse interruption unit further comprises a first capacitor, a first resistor, a second resistor, and a third resistor;
the first end of the first capacitor is the output end of the pulse interruption unit, and the second end of the first capacitor is connected with the second end of the second resistor; the first end of the first resistor is connected with a power supply end, and the second end of the first resistor is connected with the first end of the first capacitor; the first end of the second resistor is connected with the second end of the first resistor, and the second end of the second resistor is connected with the third end of the first switching tube; the first end of the first switch tube is the second input end of the pulse interruption unit, and the second end of the first switch tube is the first input end of the pulse interruption unit; the first end of the third resistor is connected with the first end of the first switch tube, and the second end of the third resistor is grounded.
3. The USB insertion detection circuit of claim 2 wherein the pulse repetition unit further comprises a fourth resistor, a fifth resistor, and a sixth resistor;
a first end of the fourth resistor is connected with a power supply end, and a second end of the fourth resistor is an output end of the pulse repeating unit; the third end of the second switch tube is connected with the second end of the first resistor, the second end of the second switch tube is grounded, and the first end of the second switch tube is connected with the second end of the sixth resistor; the first end of the fifth resistor is connected with the first end of the second switching tube, and the second end of the fifth resistor is grounded; the first end of the sixth resistor is the input end of the pulse repetition unit.
4. The USB insertion detection circuit according to claim 2 or 3, wherein the first switch tube is an N-channel FET, the first terminal of the first switch tube is a gate of the N-channel FET, the second terminal of the first switch tube is a source of the N-channel FET, and the third terminal of the first switch tube is a drain of the N-channel FET; the second switch tube is an N-channel field effect tube, the first end of the second switch tube is a grid electrode of the N-channel field effect tube, the second end of the second switch tube is a source electrode of the N-channel field effect tube, and the third end of the second switch tube is a drain electrode of the N-channel field effect tube.
5. The USB insertion detection circuit according to claim 1, wherein the insertion detection unit comprises at least one USB female socket chip, the first pin of each USB female socket chip is a first input terminal of the insertion detection unit, the second pin of each USB female socket chip is a second input terminal of the insertion detection unit, the third pin of each USB female socket chip is a third input terminal of the insertion detection unit, the fifth pin and the sixth pin of each USB female socket chip are connected to an output terminal of the insertion detection unit, and the fourth pin, the seventh pin, the eighth pin, the ninth pin and the tenth pin of each USB female socket chip are grounded.
6. The USB insertion detection circuit of claim 5 wherein each of the USB female socket chips further comprises a first switch and a second switch; the fifth pin is connected with the first end of the first switch, and the second end of the first switch is grounded; the sixth pin is connected with a first end of the second switch, and a second end of the second switch is grounded.
7. The USB insertion detection circuit of claim 1, wherein the Boost activation unit comprises a power management chip, a first capacitance module, a second capacitance module, a third capacitance module, a first inductor, a seventh resistor, and an eighth resistor;
the fifth pin of the power management chip is connected with the first end of the first capacitor module, the twelfth pin of the power management chip is the input end of the insertion detection unit, the third pin of the power management chip is connected with the first end of the second capacitor module, the fourth pin of the power management chip is connected with the first end of the second capacitor module, a tenth pin of the power management chip is a third output terminal of the Boost activation unit, an eleventh pin of the power management chip is a fourth output end of the Boost activation unit, the second pin of the power management chip is connected with the first end of the first inductor, the twenty-second pin of the power management chip is connected with the second end of the first inductor, a twenty-first pin of the power management chip is connected with a first end of the third capacitor block; the second end of the first capacitor module is a second output end of the Boost activation unit, and the third end of the first capacitor module is grounded; a second end of the second capacitor module is a first output end of the Boost activation unit, and a third end of the second capacitor module is grounded; a second end of the third capacitor module is a fifth output end of the Boost activation unit, and a third end of the third capacitor module is grounded; a first end of the seventh resistor is connected with a second end of the first inductor, and a second end of the seventh resistor is connected with a second end of the third capacitor module; the first end of the eighth resistor is connected with the first end of the seventh resistor, and the second end of the eighth resistor is connected with the second end of the seventh resistor.
8. The USB insertion detection circuit according to claim 7, wherein the Boost activation unit further includes a timer module, and when the Boost mode is turned on, the Boost activation unit controls the timer module to be turned on, and after a preset time is turned on, the timer module controls the Boost mode to be turned off.
9. The USB insertion detection circuit of claim 8 wherein the first, second and third capacitive modules are each formed by combining N capacitors in parallel; n is an integer, and N is greater than or equal to 1.
10. A USB insertion detection device comprising the USB insertion detection circuit according to any one of claims 1 to 9.
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| CN109557846B (en) * | 2018-11-22 | 2021-06-22 | 青岛海信移动通信技术股份有限公司 | Detection identification circuit, detection identification method thereof and electronic equipment |
| CN110109792A (en) * | 2019-05-24 | 2019-08-09 | 珠海多士科技有限公司 | USB device plug-pull detecting circuit under a kind of operating system off-line state |
| CN114116546A (en) * | 2021-11-19 | 2022-03-01 | Oppo广东移动通信有限公司 | Device unplugging reporting method and device, computer readable medium and electronic device |
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