CN216597621U

CN216597621U - Support plate structure and assembly for improving efficiency of heterojunction battery and heterojunction battery

Info

Publication number: CN216597621U
Application number: CN202123314258.3U
Authority: CN
Inventors: 杨骥; 鲁林峰; 黄金; 李东栋; 杨立友; 王继磊; 贾慧君
Original assignee: Jinneng Clean Energy Technology Ltd
Current assignee: Jinneng Clean Energy Technology Ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2022-05-24
Anticipated expiration: 2031-12-27

Abstract

The utility model provides a promote support plate structure, subassembly and heterojunction battery of heterojunction battery efficiency, the support plate structure includes supporting baseplate, supporting baseplate's both ends are fixed to be set up one respectively and are erected 115 chamfers on erecting the fagging, make two erect the fagging with supporting baseplate forms a 5 mm's recess. The utility model discloses can effectively avoid the poor problem of thick homogeneity of membrane on the different silicon chips that appear on same carrier and the same silicon chip different zone, the transparent conductive thin film that this kind of structure support silicon chip was sputtered, the homogeneity is better, and electric conductivity is better to promote heterojunction solar cell's conversion efficiency.

Description

Support plate structure and assembly for improving efficiency of heterojunction battery and heterojunction battery

Technical Field

The utility model relates to a solar cell technical field, in particular to promote support plate structure, subassembly and heterojunction battery of heterojunction battery efficiency.

Background

The solar cell is a semiconductor device which can convert solar energy into electric energy, and photo-generated current is generated in the solar cell under the illumination condition, and the electric energy is output through an electrode. With the continuous progress of solar cell production technology, the development of high efficiency cells with more advantageous conversion efficiency is more and more emphasized. Among them, a silicon-based heterojunction solar cell (HJT cell) in which the surface is passivated with an amorphous silicon intrinsic layer (a-Si: h (i)) is one of the important research directions. It is known that silicon-based heterojunction solar cells not only have high conversion efficiency and high open-circuit voltage, but also have the advantages of low temperature coefficient, no induced degradation (LID), no induced degradation (PID), low preparation process temperature and the like [2 ]. In addition, the silicon-based heterojunction battery can ensure high conversion efficiency, and the thickness of the silicon wafer can be reduced to 100 mu m, so that the consumption of silicon materials is effectively reduced, and the silicon-based heterojunction battery can be used for preparing a bendable battery component.

HJT (heterojunction) cells are also N-type cells, a type of photovoltaic cell made with crystalline (c-Si) and amorphous (α -Si) silicon films. The HJT battery technology is simpler than PERC and PERT, and the main processes comprise wool making and cleaning, amorphous silicon film growth (CVD deposition of boron and phosphorus), double-sided TCO (transparent conductive film) plating, screen printing and sintering.

Technical advantages of HJT cells include: 1) the battery has simple structure and short process flow. 2) The battery is high in open voltage. 3) The HJT battery technology is generally below 200 ℃, and the requirement on silicon substrate materials is low; the heat energy input is less, and the requirement on environment cleanliness is lower. 4) Can generate electricity on two sides. 5) The flexibility is good, and a flexible component can be prepared. The HJT battery is expected by virtue of very high conversion efficiency (the average efficiency in 2019 reaches 23 percent, which is 1 to 2 percent higher than that of a P-type battery), but the current production equipment of the HJT battery is expensive, the investment cost is high, and the cost reduction is a primary task. In a comprehensive view, the HJT battery has the advantages of short process flow, high conversion efficiency and the like, and is expected to become the next generation of mainstream battery technology.

The HJT battery has a double-sided characteristic, the front surface and the back surface of the HJT battery are provided with the amorphous silicon layers at the same time, and the transparent conductive film needs to be covered at the same time, but when the transparent conductive film is sputtered and deposited, the thickness and the uniformity of ITO sputtered on the surface of the silicon wafer can be influenced by the design of a silicon wafer carrier, the effect of the double-sided transparent conductive film is influenced, the loss on efficiency is brought, the performance of a conductive layer is improved by breaking through the prior art, the mass production efficiency of the HJT battery is further improved, and the large-area industrialization process is accelerated, so that the HJT battery is the challenge at present.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem that needs to solve is the not high condition of transparent conductive film homogeneity of conventional HJT battery. Note that the transparent conductive film described herein is a film such as ITO, IWO, etc. sputtered on an amorphous silicon film layer, and uniformity refers to the problem of film thickness uniformity on different silicon wafers and different regions of the same silicon wafer on the same carrier. The uniformity of the conductive thin film layer formed at present is poor on a silicon wafer positioned in the edge area of the carrier, so that the thickness of the transparent conductive thin film sputtered on the silicon wafer in the area is directly low, the surface conductivity of the silicon wafer in the area is influenced, and the electrical property of a battery piece is influenced.

In order to solve the problem, the utility model provides a promote support plate structure, subassembly and heterojunction battery of heterojunction battery efficiency, the technical scheme of its adoption as follows:

according to the utility model discloses a first technical scheme provides a promote support plate structure of heterojunction battery efficiency, support plate structure includes supporting baseplate, supporting baseplate's both ends are fixed and are set up one respectively and erect the fagging do 115 chamfers on erecting the fagging, make two erect the fagging with supporting baseplate forms a 5 mm's recess.

Preferably, the vertical supporting plate and the supporting bottom plate are connected into a whole.

According to the utility model discloses a second technical scheme provides a promote support plate subassembly of heterojunction battery efficiency, the support plate subassembly includes the silicon chip and according to the utility model discloses any embodiment the support plate structure, through the recess installation the silicon chip.

Preferably, the silicon wafer comprises N-type monocrystalline silicon, an amorphous silicon film layer and an N-type amorphous silicon layer deposited on the front surface of the N-type monocrystalline silicon, and an amorphous silicon film layer and a P-type amorphous silicon layer deposited on the back surface of the N-type monocrystalline silicon.

According to the utility model discloses a third technical scheme provides an utilize and is according to the utility model discloses the heterojunction battery that support plate structure preparation obtained, the heterojunction battery include N type monocrystalline silicon front sedimentary positive deposit amorphous silicon rete and N type amorphous silicon layer and deposited back deposit amorphous silicon rete and the P type amorphous silicon layer of N type monocrystalline silicon back the first transparent electrically conductive rete of one deck has been plated on the N type amorphous silicon layer one deck transparent electrically conductive rete has been plated on the P type amorphous silicon layer first transparent electrically conductive rete with set up first metal electrode and second metal electrode on the transparent electrically conductive rete of second respectively.

The utility model has the advantages that: the utility model discloses can effectively avoid the poor problem of thick homogeneity of membrane on the different silicon chips that appear on same carrier and the same silicon chip different zone, the transparent conductive thin film that this kind of structure support silicon chip was sputtered, the homogeneity is better, and electric conductivity is better to promote heterojunction solar cell's conversion efficiency.

Drawings

Fig. 1 shows a plan view of a carrier plate structure for improving efficiency of a heterojunction cell according to an embodiment of the present invention.

Fig. 2 shows a partially enlarged schematic view of fig. 1.

Fig. 3 shows a uniformity spotting method according to an embodiment of the present invention.

Fig. 4 shows a plan view of a carrier plate assembly for improving efficiency of a heterojunction cell according to an embodiment of the present invention.

Fig. 5 shows a silicon wafer structure diagram of a carrier plate assembly for improving efficiency of a heterojunction cell according to an embodiment of the present invention.

FIG. 6 shows a "class-Eff" single factor analysis contrast plot.

Fig. 7 shows a schematic structural diagram of a heterojunction cell according to an embodiment of the invention.

Detailed Description

The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.

In the description of the present invention, "a plurality" means two or more unless otherwise specified; the terms "upper", "lower", "left", "right", "inner", "outer", "front", "rear", "head", "tail", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are merely for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; may be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Example 1:

fig. 1 shows a plan view of a carrier plate structure for improving efficiency of a heterojunction cell according to an embodiment of the present invention. Fig. 2 shows a partially enlarged schematic view of fig. 1. As shown in fig. 1 and 2, the carrier plate structure includes a support base plate 10, wherein two ends of the support base plate 10 are respectively fixedly provided with a vertical support plate 11, and a 115 ° chamfer is formed on the vertical support plate 11, so that two vertical support plates 11 and the support base plate 10 form a 5mm groove 12; and the vertical supporting plate 11 is connected with the supporting bottom plate 10 to form a whole.

The effect of the carrier plate structure provided by the embodiment of the present invention will be described below with reference to a specific battery manufacturing method.

In the prior art, a method for preparing an HJT battery includes the following steps:

the method comprises the following steps: and finishing the amorphous silicon coating of the silicon wafer by a conventional HJT production process.

Step two: and supporting the silicon wafer, and sputtering the transparent conductive film.

Step three: and (4) screen printing, testing and sorting.

In the embodiment of the present invention, in the above step two, the embodiment of the present invention provides a support plate structure for supporting a silicon wafer, and other steps are not changed. The utility model discloses it is leading-in simple to have, effect obvious. The specific experimental procedure is as follows:

the first step of the HJT production process flow is the texturing and cleaning of a primary silicon wafer, an N-type monocrystalline silicon wafer is required to be used, the resistivity of the N-type monocrystalline silicon wafer is required to be 1-7.0 omega-cm, the thickness of the N-type monocrystalline silicon wafer is 50-200 mu m, the edge width of the N-type monocrystalline silicon wafer is 166mm, the texturing is carried out through an alkaline solution, the cleaning is carried out through an ammonia hydrogen peroxide solution, the size of the textured surface is controlled to be 1-9 mu m, and KOH or NaOH solution is used as the alkaline solution; and the second step is to complete the deposition of the amorphous silicon film layer of the HJT battery, which is realized by using plasma enhanced chemical vapor deposition or catalytic chemical vapor deposition, wherein the amorphous silicon film layer is deposited on the front surface and the back surface of the silicon wafer, the amorphous silicon film layer is divided into a front layer and a back layer, the front layer is an intrinsic amorphous silicon layer and a P-type amorphous silicon film layer or an N-type amorphous silicon film layer from the base body, the back layer is an intrinsic amorphous silicon layer and an N-type amorphous silicon film layer or a P-type amorphous silicon film layer from the base body, the intrinsic amorphous silicon film layer is 5-20nm in thickness, the P-type amorphous silicon film layer is 5-20nm in thickness, the N-type amorphous silicon film layer is 5-30nm in thickness, the process temperature is 180-250 ℃ and the process time is 3-10 min.

Step two is doping amorphous silicon surface deposit transparent conductive thin film, and its deposition mode is PVD method or RPD method, and its transparent conductive thin film material is ITO, IWO or AZO, and coating thickness is 60-120nm, and is different with traditional coating carrier, utilizes the embodiment of the utility model provides a support plate structure has increased the chamfer as the carrier to 115 chamfer angles have been designed, make the recess degree of depth 5mm, thereby improved the inhomogeneous phenomenon of silicon chip edge region coating.

Printing metal electrodes on the front and back surfaces of the fully covered conductive thin film layer, wherein the metal electrodes are silver electrodes, the printing mode is screen printing, and the front and back surfaces of the silver electrodes are required to comprise main grids and fine grid lines, the number of the main grid lines is 0-20, the width of the grid lines is 0-1.2mm, the number of the auxiliary grid lines is 80-200, and the width of the grid lines is 20-60 mu m; and then solidifying the metal electrode, wherein the solidifying temperature is 0-200 ℃, and the solidifying time is 10-30 min. The test sorting is required to be carried out under standard test conditions, and specifically, the irradiance of a light source is as follows: 1000W/m2, test temperature: 25 ± 20C, AM1.5 ground solar spectral irradiance distribution.

Through the test, use the utility model discloses the homogeneity of HTJ battery that the support plate structure that the embodiment innovation designed obtained is prepared according to above-mentioned method is very good. In addition, in this embodiment, a uniformity test is performed according to the uniformity point-taking mode shown in fig. 4, and the uniformity reaches 2.62%. The cells prepared in the conventional carrier plate structure were tested in the same spot picking manner and had a uniformity of 3.38%. Therefore, use the embodiment of the utility model provides a support plate structure that innovative design comes out has improved the poor problem of homogeneity that traditional coating film in-process appears according to the transparent conductive film that above-mentioned process formed, and then has solved poor conductivity, the undulant big problem of electrical property.

Example 2:

fig. 4 shows a plan view of a carrier plate assembly for improving efficiency of a heterojunction cell according to an embodiment of the present invention. As shown in fig. 4, an embodiment of the present invention provides a carrier plate assembly for improving efficiency of a heterojunction battery. This support plate subassembly includes the silicon chip and according to the utility model discloses embodiment 1 support plate structure 13, through recess 12 installation silicon chip 14.

Fig. 5 shows a silicon wafer structure diagram of a carrier plate assembly for improving efficiency of a heterojunction cell according to an embodiment of the present invention. As shown in fig. 5, the silicon wafer 13 includes an N-type single crystal silicon 5, an amorphous silicon film layer 4 and an N-type amorphous silicon layer 5 deposited on the front surface of the N-type single crystal silicon 5, and an amorphous silicon film layer 6 and a P-type amorphous silicon layer 7 deposited on the back surface of the N-type single crystal silicon 5.

Utilize the embodiment of the utility model provides a when the support plate subassembly preparation battery that provides, can adopt following step:

printing metal electrodes on the front and back surfaces of the fully covered conductive thin film layer, wherein the metal electrodes are silver electrodes, the printing mode is screen printing, and the front and back surfaces of the silver electrodes are required to comprise main grids and fine grid lines, the number of the main grid lines is 0-20, the width of the grid lines is 0-1.2mm, the number of the auxiliary grid lines is 80-200, and the width of the grid lines is 20-60 mu m; and then solidifying the metal electrode, wherein the solidifying temperature is 0-200 ℃, and the solidifying time is 10-30 min. The test sorting is required to be carried out under standard test conditions, specifically, the irradiance of a light source is as follows: 1000W/m2, test temperature: 25 ± 20C, AM1.5 ground solar spectral irradiance distribution.

FIG. 6 shows a "class-Eff" single factor analysis contrast plot. As can be seen from the figure, the electrical performance achieved by the improved cell assembly is even greater.

Through the test, owing to used the embodiment of the utility model provides a support plate subassembly that innovative design came out, through the transparent conductive film that above-mentioned process formed, improved the poor problem of homogeneity that traditional coating film in-process appeared, and then solved the electric conductivity poor, the undulant big problem of electrical property.

Example 3:

fig. 7 shows a schematic structural diagram of a heterojunction cell according to an embodiment of the invention. As shown in fig. 7, an embodiment of the present invention provides a heterojunction battery prepared by using the support plate structure according to embodiment 1 of the present invention. The heterojunction battery comprises N-type monocrystalline silicon 5, a front deposited amorphous silicon film layer 4 and an N-type amorphous silicon layer 5 deposited on the front surface of the N-type monocrystalline silicon 5, and a back deposited amorphous silicon film layer 6 and a P-type amorphous silicon layer 7 deposited on the back surface of the N-type monocrystalline silicon 5, wherein a first transparent conductive film layer 2 is plated on the N-type amorphous silicon layer 5, a second transparent conductive film layer 8 is plated on the P-type amorphous silicon layer 7, and a first metal electrode 1 and a second metal electrode 9 are respectively arranged on the first transparent conductive film layer 2 and the second transparent conductive film layer 7.

The embodiment of the utility model provides a, can adopt following method to prepare:

using an N-type monocrystalline silicon wafer to carry out texturing and cleaning to form a surface textured suede;

as shown in fig. 4, plasma enhanced chemical vapor deposition is used to deposit an amorphous silicon film layer 4 and an N-type amorphous silicon layer 3 on the textured N-type single crystal silicon 5 on the front surface, and an amorphous silicon film layer 6 and a P-type amorphous silicon layer 7 on the back surface;

carrying out conventional sputtering coating operation by using a PVD method and using the improved carrier to support the silicon wafer;

printing a first metal electrode 1 and a second metal electrode 9 on the front surface and the back surface of the N-type silicon wafer which are all covered with the conductive thin film layer;

and finally, testing the battery piece under the standard test condition.

Compared with the conventional process method, the electrical performance of the HJT battery prepared by the method is improved by 0.2% on each carrier plate, and is mainly improved by the average value caused by the reduction of lower points.

The above embodiments are only used for illustrating the present invention, and not for limiting the present invention, and those skilled in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention, so that all equivalent technical solutions also belong to the scope of the present invention, and the protection scope of the present invention should be defined by the claims.

Claims

1. The utility model provides a promote support plate structure of heterojunction battery efficiency, a serial communication port, support plate structure includes supporting baseplate, supporting baseplate's both ends are fixed to set up a perpendicular fagging respectively do 115 chamfers on the perpendicular fagging, make two perpendicular fagging with supporting baseplate forms a 5 mm's recess.

2. The carrier plate structure of claim 1 wherein said vertical support plates are integrally connected to said support chassis.

3. A carrier plate assembly for improving efficiency of a heterojunction cell, comprising a silicon wafer and the carrier plate structure of claim 1 or 2, wherein the silicon wafer is mounted through the groove.

4. The carrier assembly of claim 3, wherein the silicon wafer comprises N-type single crystal silicon, an amorphous silicon film layer and an N-type amorphous silicon layer are deposited on the front surface of the N-type single crystal silicon, and an amorphous silicon film layer and a P-type amorphous silicon layer are deposited on the back surface of the N-type single crystal silicon.

5. A heterojunction cell prepared by using the carrier plate structure of claim 1 or 2, wherein the heterojunction cell comprises N-type monocrystalline silicon, an amorphous silicon film layer and an N-type amorphous silicon layer deposited on the front surface of the N-type monocrystalline silicon, and an amorphous silicon film layer and a P-type amorphous silicon layer deposited on the back surface of the N-type monocrystalline silicon, wherein a first transparent conductive film layer is plated on the N-type amorphous silicon layer, a second transparent conductive film layer is plated on the P-type amorphous silicon layer, and a first metal electrode and a second metal electrode are respectively arranged on the first transparent conductive film layer and the second transparent conductive film layer.