CN115377254B - Heterojunction solar cell and molding process of heterojunction solar cell component - Google Patents
Heterojunction solar cell and molding process of heterojunction solar cell component Download PDFInfo
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- CN115377254B CN115377254B CN202211315205.XA CN202211315205A CN115377254B CN 115377254 B CN115377254 B CN 115377254B CN 202211315205 A CN202211315205 A CN 202211315205A CN 115377254 B CN115377254 B CN 115377254B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/03529—Shape of the potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
- H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a forming process of heterojunction solar cells and components, which comprises the following steps: s1, processing a battery piece; s2, assembling the assembly. The battery piece does not need screen printing, and the circuit is conducted under the alignment lamination and positive and negative connection of the upper and lower conductive adhesive films, so that the silver consumption is greatly reduced, the cost is reduced, the tailing phenomenon caused by the power reduction, photo-thermal attenuation and relative dispersion of the battery piece due to high temperature is avoided, the battery conversion efficiency is improved, in addition, the symmetrical structure can eliminate silicon chip deformation and thermal damage caused by heat or film formation, the efficient manufacture of thin silicon chips is facilitated, and meanwhile, the symmetrical structure can effectively absorb ground reflected light, and the output power of the assembly is further increased.
Description
Technical Field
The invention belongs to the technical field of photovoltaics, and particularly relates to a heterojunction solar cell and a molding process of a component.
Background
Heterojunction solar cells, for example: HJT cell (which is an abbreviation for Heterojunction with Intrinsic Thin Film) is also an N-type single crystal double sided cell. HJT is to HJT battery section makes HJT battery section series connection to become photovoltaic module through folding tile process or conventional welding tape welding process to reduce the self loss of electric current in the inside of subassembly.
Currently, the molding process of HJT battery includes the following steps:
cleaning texturing (texturing and cleaning an N-type monocrystalline silicon wafer), PECVD to manufacture a double-sided amorphous silicon doped layer (a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer are respectively formed on the front side and the back side of the N-type monocrystalline silicon wafer through an intrinsic PECVD process, an N-type amorphous silicon/microcrystalline silicon layer is formed on the first intrinsic amorphous silicon layer through an N-type PECVD process, a P-type amorphous silicon/microcrystalline silicon layer is formed on the second intrinsic amorphous silicon layer through a P-type PECVD process, & gt PVD to manufacture a double-sided TCO (TCO conducting film is deposited on two sides of the wafer, & gt screen printing and sintering (Ag electrodes are manufactured on two sides of the wafer by using a screen printing technology, & gt light injection annealing synergy & gt cell test sorting (current and voltage) & gt welding (welding tandem is performed after a standard cell is cut into two half cells with the same standard specification along the direction perpendicular to a main grid line of the wafer by using a laser cutting method), specifically placing the cells onto a welding frame in a head-tail overlapping mode in a tile mode, and laminating the cells by adopting a welding tape → laminating, carrying out lamination → lamination, packaging test and packaging, and testing and packaging.
However, the above molding has the following drawbacks:
1) The adopted screen printing generally uses low-temperature silver paste, the cost of the silver paste accounts for about 20% of the cost of the battery, and the cost of the silver paste is 40% of the non-silicon cost, so that the silver consumption is reduced, and the silver paste has great significance on HJT batteries;
2) Before the batteries are bonded together by the shingle technology, a large battery is still required to be cut into small-sized battery pieces by laser, and the local temperature of the laser energy acting on the surface of the battery is too high, because the HJT battery is a low-temperature technology in the whole manufacturing process, the passivation effect of the amorphous silicon film on the surface of the material is rapidly reduced after the amorphous silicon film is subjected to high temperature, and the laser cutting seriously affects the battery efficiency of HJT, so that when HJT is combined with the shingle technology, the power output of a HJT shingle assembly is reduced; meanwhile, the tailing phenomenon caused by relative dispersion directly affects the conversion efficiency;
3) The welding employed, conventional such as infrared welding, is not only light but also heat, and therefore, causes photo-thermal decay.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide an improved heterojunction solar cell and a molding process of a component.
In order to solve the technical problems, the invention adopts the following technical scheme:
a forming process of heterojunction solar cells and components comprises the following steps:
s1, processing of battery pieces
Firstly, texturing and cleaning an N-type monocrystalline silicon wafer, then manufacturing a double-sided amorphous silicon doped layer, preparing a double-sided TCO conductive film, and sequentially forming a symmetrical structure of TCO-N-i-N-i-P-TCO from top to bottom; secondly, performing light injection efficiency improvement and PID attenuation resistance, and then performing test sorting to finish the same-level grading of the battery piece;
s2, assembly of components
Firstly, paving a lower conductive adhesive film on glass, and placing the sorted battery pieces of the same level on the lower conductive adhesive film according to the alignment of electrode patterns, wherein the electrode patterns of the lower conductive adhesive film are upward; secondly, paving an upper conductive adhesive film on the battery piece from the electrode pattern downwards in an aligned manner, and then connecting the anode and the cathode; and finally, performing circuit connection on the upper conductive adhesive film, the battery piece and the lower conductive adhesive film in lamination, and then framing/wiring the box.
Preferably, the sorting process sorts by different brightness in the same level of grading at S1. The conversion efficiency of the formed battery piece is close to that of the formed battery piece, and the formed battery piece cannot be scattered, so that the output power of the component is increased.
According to one embodiment and preferred aspect of the present invention, the brightness is classified into four grades of 50 millicandela per square meter or less, 50 to 100 millicandela per square meter, 100 to 150 millicandela per square meter, and greater than 150 millicandela per square meter. Through the division of the four level gears, the classification mode can effectively ensure that the battery piece current at the component end is in the same gear, and avoid the phenomenon that the power of the whole component is reduced and the hot spot phenomenon is reduced due to the wooden barrel effect.
Preferably, in the step S2, the positive and negative electrodes are connected by laser or electromagnetic welding, and the welding is mainly electrode connection, is not in direct contact with the battery piece or is not affected by the production line, so that the phenomena of power attenuation or bright and dark pieces caused by high temperature and illumination in the conventional HJT battery piece welding process can be effectively avoided.
According to a further specific and preferred aspect of the invention, the lamination in S2 is performed under vacuum and at 170-180 ℃. The lamination process has great influence on the performance of the heterojunction battery piece, the amorphous silicon film of the HJT battery piece is abnormal due to the fact that the temperature is too high, and the adhesion between an adhesive film layer used by the assembly and packaging materials such as glass and the battery piece is problematic due to the fact that the temperature is too low.
Preferably, in S2, circuits are formed on both the front and back surfaces of the lower conductive adhesive film and the upper conductive adhesive film.
According to still another specific and preferred aspect of the present invention, the cell sheet includes a symmetrical structure in which TCO-N-i-P-TCO is sequentially formed from top to bottom in S1, wherein a PN junction is formed between the crystalline silicon and the amorphous silicon thin film. The symmetrical structure has relatively simple forming process, and adopts a heterojunction structure, so that the battery has higher open-circuit voltage, and the symmetrical structure can eliminate silicon wafer deformation and thermal damage caused by heat or film forming, thereby being beneficial to efficiently manufacturing thin silicon wafers, and in addition, the symmetrical structure can effectively absorb ground reflected light and increase the output power of the assembly (6% -10%).
Preferably, intrinsic layers with the thickness of 5-10 mu m are sequentially deposited on the front side and the back side of the N-type crystal silicon wafer, and the band gap of the intrinsic layers is wider than that of SiNx or SiO 2. The intrinsic amorphous silicon film is inserted into the heterojunction interface, thereby effectively passivating the surface of the battery, and simultaneously, the alpha-Si passivation layer is opposite to SiNx or SiO 2 The band gap is wider; the light-receiving surface is a p-i type alpha-Si film (thickness 5-10 μm).
Preferably, the TCO conductive film is a transparent oxide film and the deposition of the TCO conductive film includes reactive plasma evaporation and physical vapor deposition. The emitter adopts a wide band gap amorphous silicon film, and a transparent oxide (TCO) film is covered on the emitter, so that the light transmittance of the battery and the conductivity of the surface of the battery are improved.
Further, a front transparent conductive film is deposited by a reactive plasma coating device, a back transparent conductive film is deposited by a magnetron sputtering coating device, and the two coating devices are integrated into the same vacuum device.
TCO conductive film deposition includes RPD (reactive plasma evaporation) and PVD (physical vapor deposition). PVD techniques use ITO, SCOT, RPD with IWO, ICO as targets. PVD processes mainly include vacuum evaporation and sputtering. The HJT battery mainly adopts a magnetron sputtering method, and the principle is that thin gas bombards the surface of a cathode target under the action of an electric field by plasma generated by abnormal glow discharge, and molecules, atoms, ions, electrons and the like on the surface of the target are sputtered out and are shot to the surface of a silicon wafer to form a coating; the RPD has better film growth rate, film forming quality and electrical property, but the cost of the target material is higher.
Preferably, the highest temperature in the molding process is the formation temperature of the amorphous silicon thin film and is below 200 ℃. So that the carrier lifetime of the silicon wafer is not reduced by high temperature sintering during the manufacturing process.
According to a further specific and preferred aspect of the invention, after the same stage of the battery cells is completed, the array type arrangement of the battery cells is first performed and then laminated. And subsequent positive and negative electrode connection is convenient to implement.
In addition, the test sorting of the components is also performed after the framing/junction box is completed. The assembly using the new packaging technology has the advantages of low noble metal content, centralized efficiency gear, attractive appearance and the like.
Due to the implementation of the technical scheme, compared with the prior art, the invention has the following advantages:
the battery piece does not need screen printing, and the circuit is conducted under the alignment lamination and positive and negative connection of the upper and lower conductive adhesive films, so that the silver consumption is greatly reduced, the cost is reduced, the tailing phenomenon caused by the power reduction, photo-thermal attenuation and relative dispersion of the battery piece due to high temperature is avoided, the battery conversion efficiency is improved, in addition, the symmetrical structure can eliminate silicon chip deformation and thermal damage caused by heat or film formation, the efficient manufacture of thin silicon chips is facilitated, and meanwhile, the symmetrical structure can effectively absorb ground reflected light, and the output power of the assembly is further increased.
Detailed Description
The foregoing objects, features, and advantages of the present application will become more apparent from the following detailed description of the preferred embodiment. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is, however, susceptible of embodiment in many other forms than those described herein and similar modifications can be made by those skilled in the art without departing from the spirit of the application, and therefore the application is not to be limited to the specific embodiments disclosed below.
In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," etc. indicate orientations or positional relationships, merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices or elements being referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise.
In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
In this application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
It will be understood that when an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
The heterojunction solar cell and the forming process of the component of the embodiment comprise the following steps: s1, processing a battery piece; s2, assembling the assembly.
Specifically, S1, processing of a battery piece, which comprises the following steps: cleaning and texturing (texturing and cleaning an N-type monocrystalline silicon wafer), manufacturing a double-sided amorphous silicon doped layer by PECVD (forming a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front side and the back side of the N-type monocrystalline silicon wafer respectively through an intrinsic PECVD process, forming an N-type amorphous silicon/microcrystalline silicon layer on the first intrinsic amorphous silicon layer through an N-type PECVD process, forming a P-type amorphous silicon/microcrystalline silicon layer on the second intrinsic amorphous silicon layer through a P-type PECVD process, preparing a double-sided TCO (double-sided deposited TCO conducting film) by PVD, performing photo-injection annealing synergy, and testing and sorting the battery pieces.
S2, assembling components, wherein the assembling steps comprise: typesetting, lamination, anode and cathode connection, lamination, framing/junction box assembly and component test sorting of the battery pieces.
In S1, firstly, texturing and cleaning are carried out on an N-type monocrystalline silicon wafer, and then, a double-sided amorphous silicon doped layer is manufactured and a double-sided TCO conductive film is prepared; secondly, light injection efficiency improvement and PID attenuation resistance are carried out, and then test sorting is carried out to finish the same-level grading of the battery piece.
The cell comprises a symmetrical structure of TCO-N-i-N-i-P-TCO formed sequentially from top to bottom, wherein PN junctions are formed between the crystalline silicon and the amorphous silicon films. The symmetrical structure has relatively simple forming process, and adopts a heterojunction structure, so that the battery has higher open-circuit voltage, and the symmetrical structure can eliminate silicon wafer deformation and thermal damage caused by heat or film forming, thereby being beneficial to efficiently manufacturing thin silicon wafers, and in addition, the symmetrical structure can effectively absorb ground reflected light and increase the output power of the assembly (6% -10%).
And sequentially depositing an intrinsic layer with the thickness of 5-10 mu m on the front side and the back side of the N-type crystalline silicon wafer, wherein the intrinsic layer has wider band gap with SiNx or SiO 2. The intrinsic amorphous silicon film is inserted into the heterojunction interface, thereby effectively passivating the surface of the battery, and simultaneously, the alpha-Si passivation layer is opposite to SiNx or SiO 2 The band gap is wider; the light-receiving surface is a p-i type alpha-Si film (thickness 5-10 μm).
The TCO conductive film is a transparent oxide film, and the deposition of the TCO conductive film comprises reactive plasma evaporation and physical vapor deposition. The emitter adopts a wide band gap amorphous silicon film, and a transparent oxide (TCO) film is covered on the emitter, so that the light transmittance of the battery and the conductivity of the surface of the battery are improved.
In this example, a front transparent conductive film is deposited by a reactive plasma coating apparatus, a back transparent conductive film is deposited by a magnetron sputtering coating apparatus, and the two coating apparatuses are integrated into the same vacuum apparatus.
Meanwhile, TCO conductive film deposition includes RPD (reactive plasma evaporation) and PVD (physical vapor deposition). PVD techniques use ITO, SCOT, RPD with IWO, ICO as targets. PVD processes mainly include vacuum evaporation and sputtering. The HJT battery mainly adopts a magnetron sputtering method, and the principle is that thin gas bombards the surface of a cathode target under the action of an electric field by plasma generated by abnormal glow discharge, and molecules, atoms, ions, electrons and the like on the surface of the target are sputtered out and are shot to the surface of a silicon wafer along a certain direction to form a coating; the RPD has better film growth rate, film forming quality and electrical property, but the cost of the target material is higher.
In this example, the battery test and sorting are performed by the same-level classification of the battery with the brightness as the standard, and specifically, the classification is divided into a first classification of 50 millicandelas per square meter or less, a second classification of 50 to 100 millicandelas per square meter, a third classification of 100 to 150 millicandelas per square meter, and a fourth classification of more than 150 millicandelas per square meter. And after the grading is finished, assembling the battery components on the battery pieces in the same grade respectively.
Specifically, in assembly of the assembly, firstly, after the same-level grading of the battery pieces is completed, firstly typesetting the battery pieces in an array mode, then paving a lower conductive adhesive film on glass, enabling electrode patterns of the lower conductive adhesive film to be upward, and placing the battery pieces of the same level on the lower conductive adhesive film according to the electrode patterns; secondly, paving an upper conductive adhesive film on the battery piece from the electrode pattern downwards in an aligned manner, and then connecting the anode and the cathode by adopting laser or electromagnetic welding; and finally, carrying out lamination on the upper conductive adhesive film, the battery piece and the lower conductive adhesive film at the temperature of 170-180 ℃ under vacuumizing to finish circuit connection, then carrying out framing/junction box assembly, and finally carrying out test sorting on battery components.
Meanwhile, the highest temperature in the whole forming process is the forming temperature of the amorphous silicon film and is below 200 ℃. In this way, the carrier lifetime of the silicon wafer is not reduced by high temperature sintering during the manufacturing process.
In summary, the HJT battery manufactured by the present embodiment has the following advantages:
(1) the structure is symmetrical, the process is simple, the equipment required by processing is less, namely, the HJT battery is formed by respectively depositing an intrinsic layer, a doped layer, TCO (transparent conductive oxide) and double-sided lamination and positive and negative electrode connection on two sides of a monocrystalline silicon wafer, so that the battery piece does not need to adopt screen printing, and a circuit is conducted under the counterpoint lamination and positive and negative electrode connection of upper and lower conductive adhesive films, thereby greatly reducing the silver consumption and the cost, simultaneously avoiding tailing phenomena caused by power reduction, photo-thermal attenuation and relative dispersion of the battery piece due to high temperature, and improving the conversion efficiency of the battery so as to increase the output power of the component;
(2) the low-temperature manufacturing process is adopted to form a PN junction emission region by a HJT battery through a silicon-based film process, and the highest temperature in the manufacturing process is the forming temperature of an amorphous silicon film, so that the PN junction formed by the traditional crystalline silicon battery is avoided;
(3) the intrinsic thin film in the HJT battery can effectively passivate the interface defects of crystalline silicon and doped amorphous silicon to form higher open-circuit voltage;
(4) because the upper surface of the cell is TCO conductive glass, the charge can not generate polarization phenomenon and PID phenomenon (potential induced attenuation) on the TCO on the surface of the cell;
(5) the graph of the battery can be set or selected at will so as to increase the practicability; meanwhile, through brightness screening, the battery piece current at the component end can be effectively ensured to be in the same gear, the phenomenon that the power of the whole component is reduced and the hot spot phenomenon is reduced due to the wooden barrel effect is avoided; in addition, the welding is mainly electrode connection, and is not in direct contact with the battery piece or affected by production lines, so that the phenomenon of power attenuation or bright and dark piece caused by high temperature and illumination in the conventional HJT battery piece welding process can be effectively avoided; meanwhile, the lamination process has great influence on the performance of the heterojunction battery piece, the amorphous silicon film of the HJT battery piece is abnormal due to the fact that the temperature is too high, and the adhesion between an adhesive film layer used by the assembly and packaging materials such as glass and the battery piece is problematic due to the fact that the temperature is too low;
(6) the highest temperature in the molding process is the forming temperature of the amorphous silicon film and is below 200 ℃. The service life of the current carrier of the silicon wafer is not reduced due to high-temperature sintering in the manufacturing process; after the same-level grading of the battery pieces is finished, firstly typesetting the battery pieces in an array mode, and then laminating the battery pieces, so that the subsequent connection of the positive electrode and the negative electrode is convenient to implement; in addition, the test and sorting of the components are also carried out after the framing/junction box is assembled, and the components using the new packaging technology have the advantages of low noble metal content, concentrated efficiency gear, attractive appearance and the like.
In addition, the device formed by the heterojunction solar cell formed by the above process is compared with the device formed in the prior art in terms of performance (on the premise that the device dimensions are the same), and the results are as follows.
Current HJT cell and assembly (traditional process), silver consumption: 1.48g; whether there is photo-thermal decay: presence; whether tailing occurs: presence; component output power (e.g., 182mm series component): 580W.
The HJT battery and assembly (process of the application) of the application, the silver consumption: 0.7g; whether there is photo-thermal decay: absence of; whether tailing occurs: absence of; component output power (e.g., 182mm series component): 590W.
As can be seen from the comparison of the above data, the consumption of silver paste in the assembly formed by the prior art of the present application is less than half of the silver paste required by screen printing in the prior art, and the output power of the assembly is at least 10W (generally, it is very difficult to increase 5W) more than that of the assembly in the prior art, so that the effect of silver paste is reduced, and the cost is reduced; and no photo-thermal attenuation and tailing phenomena exist, so that the output power of the component (relative to the component with the same size) is obviously increased.
The present invention has been described in detail with the purpose of enabling those skilled in the art to understand the contents of the present invention and to implement the same, but not to limit the scope of the present invention, and all equivalent changes or modifications made according to the spirit of the present invention should be included in the scope of the present invention.
Claims (11)
1. The forming process of the heterojunction solar cell and the assembly is characterized by comprising the following steps of:
s1, processing of battery pieces
Firstly, texturing and cleaning an N-type monocrystalline silicon wafer, then manufacturing a double-sided amorphous silicon doped layer, preparing a double-sided TCO conductive film, sequentially forming a symmetrical structure of TCO-N-i-N-i-P-TCO from top to bottom, simultaneously forming a PN junction between the crystalline silicon and the amorphous silicon film, sequentially depositing an intrinsic layer with the thickness of 5-10 mu m on the front side and the back side of the N-type crystalline silicon wafer, wherein the intrinsic layer has wider band gap relative to SiNx or SiO2,
at the heterojunction interfaceInserting an intrinsic amorphous silicon film with an alpha-Si passivation layer opposite to SiNx or SiO 2 The band gap is wider, the light receiving surface is a p-i type alpha-Si film, and the thickness is 5-10 mu m; secondly, performing light injection efficiency improvement and PID attenuation resistance, and then performing test sorting to finish the same-level grading of the battery pieces, wherein the sorting process sorts according to different brightness so as to enable the battery piece currents at the component end to be in the same gear;
s2, assembly of components
Firstly, paving a lower conductive adhesive film on glass, and placing the sorted battery pieces of the same level on the lower conductive adhesive film according to the alignment of electrode patterns, wherein the electrode patterns of the lower conductive adhesive film are upward; secondly, paving an upper conductive adhesive film on the battery piece from the electrode pattern downwards in an aligned manner, and then connecting the anode and the cathode; and finally, performing circuit connection on the upper conductive adhesive film, the battery piece and the lower conductive adhesive film in lamination, and then framing/wiring the box.
2. The process for forming heterojunction solar cells and modules as claimed in claim 1, wherein: the brightness is classified into four grades of 50 millicandela/square meter or less, 50-100 millicandela/square meter, 100-150 millicandela/square meter and more than 150 millicandela/square meter.
3. The process for forming heterojunction solar cells and modules as claimed in claim 1, wherein: in S2, the positive electrode and the negative electrode are connected by laser or electromagnetic welding.
4. The process for forming heterojunction solar cells and modules as claimed in claim 1, wherein: the lamination in S2 is carried out in the vacuum pumping and at 170-180 ℃.
5. The process for forming heterojunction solar cells and modules as claimed in claim 1, wherein: in the step S2, circuits are formed on the front and back surfaces of the lower conductive adhesive film and the upper conductive adhesive film.
6. The process for forming heterojunction solar cells and modules as claimed in claim 1, wherein: the TCO conductive film is a transparent oxide film.
7. The process for forming heterojunction solar cells and modules as claimed in claim 1, wherein: the deposition of TCO conductive films includes reactive plasma evaporation and physical vapor deposition.
8. The process for forming heterojunction solar cells and modules as claimed in claim 7, wherein: and depositing the front transparent conductive film by using a reactive plasma coating device, depositing the back transparent conductive film by using a magnetron sputtering coating device, and integrating the two coating devices into the same vacuum device.
9. The process for forming heterojunction solar cells and modules as claimed in claim 1, wherein: the highest temperature in the molding process is the forming temperature of the amorphous silicon film and is below 200 ℃.
10. The process for forming heterojunction solar cells and modules as claimed in claim 1, wherein: after the same-level grading of the battery pieces is completed, array typesetting of the battery pieces is performed first, and then lamination is performed.
11. The process for forming heterojunction solar cells and modules as claimed in claim 1, wherein: after the framing/junction box is completed, the test sorting of the components is also performed.
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