CN216250714U - 一种垂直堆叠多颗粒封装的to-247 - Google Patents

一种垂直堆叠多颗粒封装的to-247 Download PDF

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CN216250714U
CN216250714U CN202122800823.0U CN202122800823U CN216250714U CN 216250714 U CN216250714 U CN 216250714U CN 202122800823 U CN202122800823 U CN 202122800823U CN 216250714 U CN216250714 U CN 216250714U
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尹其言
张旭文
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Hunan Titanium Core Electronic Technology Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/4917Crossed wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312Aligning
    • H01L2224/83136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314Guiding structures outside the body

Abstract

本实用新型公开了一种垂直堆叠多颗粒封装的TO‑247,包括封装壳体和连接在封装壳体上的引脚,所述封装壳体内设有金属导电架,所述金属导电架上安装有颗粒件,用于接通引脚和芯片的线路;所述颗粒件包括连接在金属导电架上的第一颗粒,所述第一颗粒顶部连接有第二颗粒,所述第二颗粒和第一颗粒并联在引脚和芯片的线路中;本实用新型中多个颗粒呈垂直摆放,使颗粒并联在引脚和芯片的线路中,减少封装的总电阻,从而减小封装所在系统中的消耗总功率,减少热量的产生,具有省电的效果。

Description

一种垂直堆叠多颗粒封装的TO-247
技术领域
本实用新型涉及封装技术领域,具体是一种垂直堆叠多颗粒封装的TO-247。
背景技术
TO-247是比较常用的小外形封装。主要包括芯片和设置在芯片外的外壳,外壳具有支撑、保护和冷却的作用,同时还为芯片提供电气连接和隔离,以便于外壳内元器件构成完整的电路。封装主要包括插入式和表面贴装式,插入式就是将管脚穿过PCB的安装孔焊接在PCB上,表面封装式就是将管脚以及部件焊接在PCB表面的焊盘上。
现有的TO-247中,引脚和芯片的连接线路中设置有颗粒,用于接通引脚和芯片的线路,引脚和芯片的引出线均焊接在颗粒上。封装接在其他部件上使用时,电阻过大,会产生大量的热,不利于封装的长期使用。本申请提出一种可减小封装工作消耗功率的垂直堆叠多颗粒封装的TO-247。
实用新型内容
本实用新型的目的在于提供一种垂直堆叠多颗粒封装的TO-247,以解决上述背景技术中提出的问题。
为实现上述目的,本实用新型提供如下技术方案:
一种垂直堆叠多颗粒封装的TO-247,包括封装壳体和连接在封装壳体上的引脚,所述封装壳体内设有金属导电架,所述金属导电架上安装有颗粒件,用于接通引脚和芯片的线路;
所述颗粒件包括连接在金属导电架上的第一颗粒,所述第一颗粒顶部连接有第二颗粒,所述第二颗粒和第一颗粒并联在引脚和芯片的线路中。
优选的,所述引脚件包括连接在封装壳体上的栅极、第一源极、第二源极和漏极。
优选的,所述栅极、第一源极和第二源极均连接设置在封装壳体内的内引脚,所述漏极延伸至封装壳体内连接金属导电架。
优选的,与所述栅极、第一源极和第二源极配合的三组内引脚上均连接有两组第一引线,所述第一引线一端连接内引脚,所述第一引线另一端连接第二颗粒或第一颗粒。
优选的,所述第二颗粒和第一颗粒上均连接有第二引线,所述第二引线一端连接第二颗粒或第一颗粒,所述第二引线另一端连接芯片。
优选的,所述第二颗粒和第一颗粒底部均设有颗粒漏极,所述第二颗粒靠近第一颗粒一侧连接有连接金属片,所述连接金属片远离第二颗粒一端连接金属导电架。
与现有技术相比,本实用新型的有益效果是:
本实用新型中多个颗粒呈垂直摆放,使颗粒并联在引脚和芯片的线路中,减少封装的总电阻,从而减小封装所在系统中的消耗总功率,减少热量的产生,具有省电的效果。
附图说明
图1为本实用新型的结构示意图。
图2为本实用新型中第一颗粒和第二颗粒摆放的结构示意图。
图3为本实用新型中第一颗粒或第二颗粒的剖视结构示意图。
图中:11--封装壳体、12--金属导电架、13--第二颗粒、14--第一颗粒、15--栅极、16--第一源极、17--第二源极、18--漏极、19--连接金属片、20--颗粒漏极。
具体实施方式
下面将结合本实用新型实施例中的附图,对本实用新型实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本实用新型一部分实施例,而不是全部的实施例。基于本实用新型中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本实用新型保护的范围。
请参阅图1-图3,本实用新型实施例中,一种垂直堆叠多颗粒封装的TO-247,包括封装壳体11和连接在封装壳体11上的引脚,所述封装壳体11内设有金属导电架12,所述金属导电架12上安装有颗粒件,用于接通引脚和芯片的线路;
所述颗粒件包括连接在金属导电架12上的第一颗粒14,所述第一颗粒14顶部连接有第二颗粒13,所述第二颗粒13和第一颗粒14并联在引脚和芯片的线路中;
第二颗粒13和第一颗粒14并联在引脚和芯片的线路中,减少封装的总电阻,从而减小封装所在系统中的消耗总功率,减少热量的产生,具有省电的效果;
第二颗粒13和第一颗粒14并联线路中时,电阻跟颗粒数量成反比,设置两组颗粒时,总电阻为原本单颗的1/2,如果三颗,则总电阻会为原本的1/3。
实际生产中,还可根据需求或封装壳体11内的空间,继续在第二颗粒13上安装颗粒,以进一步减小总电阻。
所述引脚件包括连接在封装壳体11上的栅极15、第一源极16、第二源极17和漏极18。
所述栅极15、第一源极16和第二源极17均连接设置在封装壳体11内的内引脚,所述漏极18延伸至封装壳体11内连接金属导电架12。
与所述栅极15、第一源极16和第二源极17配合的三组内引脚上均连接有两组第一引线,所述第一引线一端连接内引脚,所述第一引线另一端连接第二颗粒13或第一颗粒14。
所述第二颗粒13和第一颗粒14上均连接有第二引线,所述第二引线一端连接第二颗粒13或第一颗粒14,所述第二引线另一端连接芯片;
引线、内引脚、颗粒之间的接线方式,能使第一颗粒17和第二颗粒18并联在引脚与芯片的线路中。
所述第二颗粒13和第一颗粒14底部均设有颗粒漏极20,所述第二颗粒13靠近第一颗粒14一侧连接有连接金属片19,所述连接金属片19远离第二颗粒13一端连接金属导电架12;连接金属片19的设置,能使第二颗粒13能与金属导电架12实现电连接。
本实用新型的工作原理是:在使用该一种垂直堆叠多颗粒封装的TO-247时,电流经过封装时,能经过第二颗粒13和第一颗粒14,第二颗粒13和第一颗粒14的设置,使封装总电阻减小,进而减小封装所在系统中的消耗总功率,减少热量的产生,具有省电的效果。
对于本领域技术人员而言,显然本实用新型不限于上述示范性实施例的细节,而且在不背离本实用新型的精神或基本特征的情况下,能够以其他的具体形式实现本实用新型。

Claims (6)

1.一种垂直堆叠多颗粒封装的TO-247,包括封装壳体(11)和连接在封装壳体(11)上的引脚,其特征在于:所述封装壳体(11)内设有金属导电架(12),所述金属导电架(12)上安装有颗粒件,用于接通引脚和芯片的线路;
所述颗粒件包括连接在金属导电架(12)上的第一颗粒(14),所述第一颗粒(14)顶部连接有第二颗粒(13),所述第二颗粒(13)和第一颗粒(14)并联在引脚和芯片的线路中。
2.根据权利要求1所述的一种垂直堆叠多颗粒封装的TO-247,其特征在于:所述引脚包括连接在封装壳体(11)上的栅极(15)、第一源极(16)、第二源极(17)和漏极(18)。
3.根据权利要求2所述的一种垂直堆叠多颗粒封装的TO-247,其特征在于:所述栅极(15)、第一源极(16)和第二源极(17)均连接设置在封装壳体(11)内的内引脚,所述漏极(18)延伸至封装壳体(11)内连接金属导电架(12)。
4.根据权利要求3所述的一种垂直堆叠多颗粒封装的TO-247,其特征在于:与所述栅极(15)、第一源极(16)和第二源极(17)配合的三组内引脚上均连接有两组第一引线,所述第一引线一端连接内引脚,所述第一引线另一端连接第二颗粒(13)或第一颗粒(14)。
5.根据权利要求4所述的一种垂直堆叠多颗粒封装的TO-247,其特征在于:所述第二颗粒(13)和第一颗粒(14)上均连接有第二引线,所述第二引线一端连接第二颗粒(13)或第一颗粒(14),所述第二引线另一端连接芯片。
6.根据权利要求1所述的一种垂直堆叠多颗粒封装的TO-247,其特征在于:所述第二颗粒(13)和第一颗粒(14)底部均设有颗粒漏极(20),所述第二颗粒(13)靠近第一颗粒(14)一侧连接有连接金属片(19),所述连接金属片(19)远离第二颗粒(13)一端连接金属导电架(12)。
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