CN215452914U

CN215452914U - High-performance level shift circuit

Info

Publication number: CN215452914U
Application number: CN202121532386.2U
Authority: CN
Inventors: 辛晓宁; 周继民; 任建; 宋嘉欣; 王松; 郭楷楷
Original assignee: Shenyang University of Technology
Current assignee: Shenyang University of Technology
Priority date: 2021-07-07
Filing date: 2021-07-07
Publication date: 2022-01-07
Anticipated expiration: 2031-07-07

Abstract

The utility model relates to a high-performance level shift circuit, wherein the voltage of a VG point can float along with the voltage of a VS point, the voltage difference is controlled by the voltage of a point A, and the maximum voltage difference is within 5V, so that the VGS of a driven NMOS tube can be ensured not to exceed the voltage endurance capability. The utility model accelerates the level conversion rate, ensures that the high-end power tube can be fully conducted by raising the 5V logic level to 45V, keeps the voltage difference within 5V by the grid-source voltage of the H bridge high-end tube, and ensures that the power tube is not broken down. The utility model has the advantages of simpler circuit, lower cost and stable and reliable operation.

Description

High-performance level shift circuit

Technical Field

The utility model relates to the technical field of motor control, in particular to a high-performance level shift circuit of a stepping motor driving chip.

Background

The motor is widely applied to the fields of industrial production, agriculture, transportation, mining industry, aerospace and other industries.

The pulse modulation type motor powered by the direct current power supply is developed quickly due to the advantages of high control precision, energy conservation, large torque and the like. Such as various stepping motors, switched reluctance motors and the like, the rotating speed, the torque and the power of the stepping motors and the switched reluctance motors are regulated and controlled by adopting a pulse modulation type control circuit. Almost every such motor needs to be equipped with a controller, and the form of the circuit structure adopted by the controller directly determines the running performance and safety and reliability of the controlled motor.

Therefore, some motor controllers adopt a driving circuit with an overvoltage protection function, and as shown in fig. 1, when the power tube in the controller is overvoltage due to short circuit of a motor winding, electric leakage and the like, the controller takes appropriate technical measures to perform "overvoltage protection".

However, the overpressure resistant protection measures of the prior art have the following technical problems:

1. the conversion rate is reduced because the conversion circuit does not have the charge and discharge of the capacitor;

2. because the inductor has current, the source end potential of the high-end power tube is uncertain, so that the conventional level shift circuit can cause the H-bridge high-end power tube to exceed withstand voltage;

3. many existing protection circuits are used for sending a sampling voltage detected by a sampling element to a central processing chip, and the chip sends a gate driving pulse for closing a power tube to obtain protection, so that a controller with the protection circuit still has a considerable overcurrent damage rate due to the complex circuit and the low reliability of software operation.

Disclosure of Invention

Utility model purpose: the utility model relates to a high-performance level shift circuit, which aims to solve the technical problem of an over-withstand voltage protection measure of a control circuit in the existing motor controller.

The technical scheme is as follows:

a high-performance level shift circuit is disclosed, wherein VCP of the circuit is connected with sources of a first PMOS tube M1, a second PMOS tube M2, a first protection tube, a second protection tube, a ninth PMOS tube M9 and a tenth PMOS tube M10 in parallel, a grid electrode of the first PMOS tube M1 is connected with a drain electrode of a second PMOS tube M2, a grid electrode of the second PMOS tube M2 is connected with a drain electrode of the first PMOS tube M1, the first protection tube is connected with a drain electrode of the first PMOS tube M1 and a grid electrode of the tenth PMOS tube M10, and the second protection tube is connected with a drain electrode of the second PMOS tube M2 and a grid electrode of the ninth PMOS tube M9; the drain of the first PMOS transistor M1 is connected to the gate of the tenth PMOS transistor M10;

the drain electrode of the first protective tube, the drain electrode of the first PMOS tube M1 and the grid electrode of the tenth PMOS tube M10 are connected in parallel and then connected with the positive plate of a first capacitor C1, and the negative plate of the first capacitor C1 is connected with the drain electrode of the eleventh PMOS tube M11, the drain electrode of the first NMOS tube M12, the grid electrode of the thirteenth PMOS tube M13 and the grid electrode of the second NMOS tube M14;

the second protection tube, the drain electrode of the second PMOS tube M2 and the grid electrode of the ninth PMOS tube M9 are connected in parallel and then connected with the positive plate of a second capacitor C2, and the negative plate of the second capacitor C2 is connected with the drain electrode of a thirteenth PMOS tube M13 and the drain electrode of a second NMOS tube M14;

the source electrode of an eleventh PMOS tube M11 and the source electrode of a thirteenth PMOS tube M13 are connected to VDD in parallel, the grid electrode of the eleventh PMOS tube M11 is connected with the grid electrode of a first NMOS tube M12 and simultaneously connected with the input end A of digital control, and the drain electrode of the eleventh PMOS tube M11 is connected with the drain electrode of a first NMOS tube M12 and simultaneously connected with the grid electrode of a thirteenth PMOS tube M13 and the grid electrode of a second NMOS tube M14; the drain of the thirteenth PMOS transistor M13 is connected to the drain of the second NMOS transistor M14; the source electrode of the first NMOS transistor M12 and the source electrode of the second NMOS transistor M14 are connected to the ground in parallel;

the drain electrode of the ninth PMOS tube M9 is connected with one end of the first resistor R1 and one end of the second resistor R2, the other end of the first resistor R1 is connected with the source electrode VS of the H-bridge power tube and the emitter electrode of the triode Q1, the other end of the second resistor R2 is connected with the base electrode of the triode Q1, and the collector electrode of the triode Q1 is connected with the grid electrode VS of the H-bridge power tube.

Further, the first protection tube includes a third PMOS tube M3, a fourth PMOS tube M4 and a fifth PMOS tube M5, the source of the third PMOS tube M3 is connected to VCP, the gate of the third PMOS tube M3 is connected to the drain of the third PMOS tube M3 and the source of the fourth PMOS tube M4, the gate of the fourth PMOS tube M4 is connected to the drain of the fourth PMOS tube M4 and the source of the fifth PMOS tube M5, the gate of the fifth PMOS tube M5 is connected to the drain of the fifth PMOS tube M5, the drain of the first PMOS tube M1 and the gate of the tenth PMOS tube M10, and the gate of the fifth PMOS tube M5 and the drain of the fifth PMOS tube M5 are connected to the positive plate of the first capacitor C1.

Further, the second protection tube includes a sixth PMOS tube M6, a seventh PMOS tube M7 and an eighth PMOS tube M8, the source of the sixth PMOS tube M6 is connected to VCP, the gate of the sixth PMOS tube M6 is connected to the drain of the sixth PMOS tube M6 and the source of the seventh PMOS tube M7, the gate of the seventh PMOS tube M7 is connected to the drain of the seventh PMOS tube M7 and the source of the eighth PMOS tube M8, the gate of the eighth PMOS tube M8 is connected to the drain of the eighth PMOS tube M8, the drain of the second PMOS tube M2 and the gate of the ninth PMOS tube M9, and the drain of the second PMOS tube M2, the gate of the eighth PMOS tube M8 and the gate of the ninth PMOS tube M9 are connected to the positive plate of the second capacitor C2.

Furthermore, a power supply VM of the H-bridge internal circuit is connected in parallel with a drain electrode of the third NMOS transistor HP1 and a drain electrode of the fourth NMOS transistor HP2, a source electrode of the third NMOS transistor HP1 is connected with a drain electrode of the fifth NMOS transistor LP1, and is also connected with one end of the inductor L1; the source electrode of the fourth NMOS transistor HP2 is connected to the drain electrode of the sixth NMOS transistor LP2, and is connected to the other end of the inductor L1; the sources of the fifth NMOS transistor LP1 and the sixth NMOS transistor LP2 are connected in parallel and grounded.

Furthermore, the power supply voltage in the internal circuit of the H bridge is 40V, and the inductor L1 is an adjustable inductor.

Further, VDD is 5V.

Advantages and effects

All MOS tubes of the whole migration circuit do not exceed the withstand voltage, meanwhile, the voltage of a VG point can float along with the voltage of a VS point, the voltage difference is controlled by the voltage of a point A, and the maximum voltage difference is within 5V, so that the VGS of the driven NMOS tube can be ensured not to exceed the withstand voltage capability.

The utility model accelerates the level conversion rate, ensures that the high-end power tube can be fully conducted by raising the 5V logic level to 45V, keeps the voltage difference within 5V by the grid-source voltage of the H bridge high-end tube, and ensures that the power tube is not broken down. The conversion rate of level migration can reach 20Mbps by simulation of Cadence software, and the problem of super voltage resistance among devices does not exist. The utility model has the advantages of simpler circuit, lower cost and stable and reliable operation.

Drawings

FIG. 1 is a conventional level shift circuit;

FIG. 2 is a level shift circuit according to the present invention;

FIG. 3 is an H-bridge internal circuit;

FIG. 4 shows a simulation result of a gate-source voltage transient of an H-bridge power transistor;

the figure is marked with: 1. VCP, 2, H-bridge, 3, VDD.

Detailed Description

The utility model is described in more detail below with reference to the accompanying drawings.

Because the CSMCCD 180um is adopted in the process, the voltage endurance capability of the high-end tube is required to be considered, and therefore a high-performance level shift circuit needs to be invented.

As shown in fig. 2, a high performance level shift circuit, in which a VCP1 (Voltage Charge Pump Voltage) is connected in parallel with a source of a first PMOS transistor M1, a source of a second PMOS transistor M2, a first protection transistor, a second protection transistor, a source of a ninth PMOS transistor M9, and a source of a tenth PMOS transistor M10, a gate of the first PMOS transistor M1 is connected to a drain of the second PMOS transistor M2, a gate of the second PMOS transistor M2 is connected to a drain of the first PMOS transistor M1, the first protection transistor is connected to a drain of the first PMOS transistor M1 and a gate of the tenth PMOS transistor M10, and the second protection transistor is connected to a drain of the second PMOS transistor M2 and a gate of the ninth PMOS transistor M9; the drain electrode of the first PMOS tube M1 is connected with the grid electrode of a tenth PMOS tube M10, the drain electrodes of the first protective tube, the first PMOS tube M1 and the tenth PMOS tube M10 are connected in parallel and then connected with the positive plate of a first capacitor C1, and the negative plate of the first capacitor C1 is connected with the drain electrode of an eleventh PMOS tube M11, the drain electrode of a first NMOS tube M12, the grid electrode of a thirteenth PMOS tube M13 and the grid electrode of a second NMOS tube M14;

the drain electrode of the second protection tube, the drain electrode of the second PMOS tube M2 and the grid electrode of the ninth PMOS tube M9 are connected in parallel and then connected with the positive plate of a second capacitor C2, and the negative plate of the second capacitor C2 is connected with the drain electrodes of the thirteenth PMOS tube M13 and the second NMOS tube M14;

the sources of an eleventh PMOS tube M11 and a thirteenth PMOS tube M13 are connected to VDD (5V power supply) in parallel, the grid of the eleventh PMOS tube M11 is connected with the grid of a first NMOS tube M12 and is also connected with the input end A of digital control, the drain of the eleventh PMOS tube M11 is connected with the drain of the first NMOS tube M12 and is also connected with the grids of the thirteenth PMOS tube M13 and a second NMOS tube M14; the drain of the thirteenth PMOS transistor M13 is connected to the drain of the second NMOS transistor M14; the sources of the first NMOS transistor M12 and the second NMOS transistor M14 are connected to the ground GND in parallel;

one end of the first resistor R1 and one end of the second resistor R2 are connected and then connected with the drain electrode of the ninth PMOS tube M9, the other end of the first resistor R1 is connected with the emitter electrode of the triode Q1, the output end of the emitter electrode of the first resistor R1 is connected with the source electrode VS of the high-end power tube of the H-bridge 2, the other end of the second resistor R2 is connected with the base electrode of the triode Q1, and the collector electrode of the triode Q1 is connected with the grid electrode VG of the high-end power tube of the H-bridge 2.

As shown in fig. 2, the first protection transistor includes a third PMOS transistor M3, a fourth PMOS transistor M4 and a fifth PMOS transistor M5, the source of the third PMOS transistor M3 is connected to the VCP1, the gate of the third PMOS transistor M3 is connected to the drain of the third PMOS transistor M3 and the source of the fourth PMOS transistor M4, the gate of the fourth PMOS transistor M4 is connected to the drain of the fourth PMOS transistor M4 and the source of the fifth PMOS transistor M5, the gate of the fifth PMOS transistor M5 is connected to the drain of the fifth PMOS transistor M5, the drain of the first PMOS transistor M1 and the gate of the tenth PMOS transistor M10, and the gate of the fifth PMOS transistor M5 and the drain of the fifth PMOS transistor M5 are connected to the positive plate of the first capacitor C1; the main function of the first protection tube is to limit the gate voltages of the second PMOS transistor M1 and the tenth PMOS transistor M10, so that the voltage difference between the gate voltages of the second PMOS transistor M2 and the tenth PMOS transistor M10 and the voltage of the VCP1 is limited to 3VTHP which is about 3V.

The second protection tube comprises a sixth PMOS tube M6, a seventh PMOS tube M7 and an eighth PMOS tube M8, the source of the sixth PMOS tube M6 is connected with VCP1, the gate of the sixth PMOS tube M6 is connected with the drain of the sixth PMOS tube M6 and the source of the seventh PMOS tube M7, the gate of the seventh PMOS tube M7 is connected with the drain of the seventh PMOS tube M7 and the source of the eighth PMOS tube M8, the gate of the eighth PMOS tube M8 is connected with the drain of the eighth PMOS tube M8, the drain of the second PMOS tube M2 and the gate of the ninth PMOS tube M9, and the drain of the second PMOS tube M2, the gate of the eighth PMOS tube M8 and the gate of the ninth PMOS tube M9 are connected with the positive plate of the second capacitor C2. The second protection tube mainly functions to limit the voltage of the gates of the first PMOS transistor M1 and the ninth PMOS transistor M9, so that the voltage difference between the gates of the first PMOS transistor M1 and the ninth PMOS transistor M9 and the voltage of the VCP1 is limited to 3VTHP which is about 3V.

As shown in fig. 3, the internal circuit of the H-bridge 2 includes a power supply VM, a third NMOS transistor HP1, a fourth NMOS transistor HP2, a fifth NMOS transistor LP1, a sixth NMOS transistor LP2, and an inductor L1, the third NMOS transistor HP1 and the fourth NMOS transistor HP2 are high-side power transistors, and the fifth NMOS transistor LP1 and the sixth NMOS transistor LP2 are low-side power transistors. The gate VG of the H-bridge 2 high-side power transistor may be the gate of the third NMOS transistor HP1, or may be the gate of the fourth NMOS transistor HP 2; the source VS of the H-bridge 2 high-side power transistor may be the source of the third NMOS transistor HP1, or may be the source of the fourth NMOS transistor HP 2; in the following description, the gate VG of the H-bridge 2 high-side power transistor is used as the gate of the third NMOS transistor HP1, and the source VS of the H-bridge 2 high-side power transistor is used as the source of the third NMOS transistor HP 1.

The drain electrodes of the power supply VM and the third NMOS transistor HP1 and the drain electrode of the fourth NMOS transistor HP2 are connected in parallel, and the source electrode VS of the third NMOS transistor HP1 is connected with the drain electrode of the fifth NMOS transistor LP1 and is also connected with one end of the inductor L1; the source of the fourth NMOS transistor HP2 is connected to the drain of the sixth NMOS transistor LP2, and is also connected to the other end of the inductor L1. The sources of the fifth NMOS transistor LP1 and the sixth NMOS transistor LP2 are connected in parallel and grounded.

VM is a power supply 40V, i.e., the power supply voltage in the internal circuit of the H-bridge 2 is 40V, and the inductor L1 is an adjustable inductor.

VDD is a 5V power supply.

The gate VG end of the H-bridge 2 power transistor in fig. 2 is connected to the gate of the third NMOS transistor HP1 of the high-end power transistor in the H-bridge 2 in fig. 3, and the source VS end of the H-bridge 2 power transistor is connected to the source of the third NMOS transistor HP1 of the high-end power transistor in the H-bridge in fig. 3. When the voltage at the input end a of the digital control is dynamically changed, the gate voltages of the positive plates of the first capacitor C1 and the second capacitor C2, that is, the gate voltages of the ninth PMOS transistor M9 and the tenth PMOS transistor M10 are changed accordingly, the conversion rates are increased by the first capacitor C1 and the second capacitor C2, when the ninth PMOS transistor M9 is turned on, the voltage is generated on the first resistor R1, the transistor Q1 is turned on, and the tenth PMOS transistor M10 is turned off, so that there is substantially no voltage difference between the gate VG and the source VS of the high-side power transistor of the H bridge 2, and the third NMOS transistor HP1 of the high-side power transistor in the H bridge 2 is turned off. On the contrary, when the tenth PMOS transistor M10 is turned on and the ninth PMOS transistor M9 is turned off, the voltage at the gate VG of the H-bridge 2 power transistor will be equal to the charge pump voltage VCP1, while the voltage at the source VS of the H-bridge 2 power transistor can only reach VM at the highest level, and since VCP1-VM is greater than 3V and is used as a driving circuit of the H-bridge 2 to control the switching of the H-bridge 2 high-end power transistor, the H-bridge 2 high-end power transistor can be fully turned on, thereby better realizing the function of the stepping motor driving chip.

The simulation result of fig. 4 shows that the gate-source voltage of the high-side power tube is always within 5V. According to the high-performance stepping motor driving circuit, the voltage of the gate VG point of the high-end power tube of the H bridge 2 can float along with the voltage of the source VS point of the high-end power tube of the H bridge 2, the voltage difference is controlled by the voltage of the point A of the input end under digital control, the maximum voltage difference is within 5V, and the situation that VGS of the third NMOS tube HP1 of the high-end power tube driven by the high-end power tube does not exceed the voltage withstanding capability can be guaranteed.

Claims

1. A high performance level shifting circuit, comprising: the VCP (1) of the circuit is connected with sources of a first PMOS (M1), a second PMOS (M2), a first protection tube, a second protection tube, a ninth PMOS (M9) and a tenth PMOS (M10) in parallel, a grid electrode of the first PMOS (M1) is connected with a drain electrode of the second PMOS (M2), a grid electrode of the second PMOS (M2) is connected with a drain electrode of the first PMOS (M1), a drain electrode of the first PMOS (M1) is connected with a grid electrode of the tenth PMOS (M10), and a drain electrode of the second PMOS (M2) is connected with a grid electrode of the ninth PMOS (M9); the drain electrode of the first PMOS tube (M1) is simultaneously connected with the gate electrode of the tenth PMOS tube (M10);

the drain electrode of the first protection tube and the drain electrode of the first PMOS tube (M1) are connected with the grid electrode of the tenth PMOS tube (M10) in parallel and then are connected with the positive plate of the first capacitor (C1), and the negative plate of the first capacitor (C1) is connected with the drain electrode of the eleventh PMOS tube (M11), the drain electrode of the first NMOS tube (M12), the grid electrode of the thirteenth PMOS tube (M13) and the grid electrode of the second NMOS tube (M14);

the drain electrode of the second protection tube, the drain electrode of the second PMOS tube (M2) and the grid electrode of the ninth PMOS tube (M9) are connected in parallel and then are connected with the positive plate of a second capacitor (C2), and the negative plate of the second capacitor (C2) is connected with the drain electrode of the thirteenth PMOS tube (M13) and the drain electrode of the second NMOS tube (M14);

a source electrode of an eleventh PMOS (M11) and a source electrode of a thirteenth PMOS (M13) are connected to VDD (3) in parallel, a grid electrode of the eleventh PMOS (M11) is connected with a grid electrode of a first NMOS (M12) and is also connected with a digital control input end (A), a drain electrode of the eleventh PMOS (M11) is connected with a drain electrode of a first NMOS (M12) and is also connected with a grid electrode of the thirteenth PMOS (M13) and a grid electrode of a second NMOS (M14); the drain of the thirteenth PMOS tube (M13) is connected with the drain of the second NMOS tube (M14); the source electrode of the first NMOS tube (M12) and the source electrode of the second NMOS tube (M14) are connected to the ground in parallel;

the drain electrode of the ninth PMOS tube (M9) is connected with one end of the first resistor (R1) and one end of the second resistor (R2) after being connected, the other end of the first resistor (R1) is connected with the source electrode (VS) of the H-bridge (2) power tube and the emitter electrode of the triode (Q1), the other end of the second resistor (R2) is connected with the base electrode of the triode (Q1), and the collector electrode of the triode (Q1) is connected with the grid electrode (VG) of the H-bridge (2) power tube.

2. The high performance level shift circuit of claim 1, wherein: the first protection tube comprises a third PMOS tube (M3), a fourth PMOS tube (M4) and a fifth PMOS tube (M5), the source electrode of the third PMOS tube (M3) is connected with VCP (1), the grid electrode of the third PMOS tube (M3) is connected with the drain electrode of the third PMOS tube (M3) and the source electrode of the fourth PMOS tube (M4), the grid electrode of the fourth PMOS tube (M4) is connected with the drain electrode of the fourth PMOS tube (M4) and the source electrode of the fifth PMOS tube (M5), the grid electrode of the fifth PMOS tube (M5) is connected with the drain electrode of the fifth PMOS tube (M5), the drain electrode of the first PMOS tube (M1) and the grid electrode of the tenth PMOS tube (M10), and the grid electrode of the fifth PMOS tube (M5) and the drain electrode of the fifth PMOS tube (M5) are connected with the positive plate of the first capacitor (C1).

3. The high performance level shift circuit of claim 1, wherein: the second protection tube comprises a sixth PMOS tube (M6), a seventh PMOS tube (M7) and an eighth PMOS tube (M8), the source electrode of the sixth PMOS tube (M6) is connected with VCP (1), the grid electrode of the sixth PMOS tube (M6) is connected with the drain electrode of the sixth PMOS tube (M6) and the source electrode of the seventh PMOS tube (M7), the grid electrode of the seventh PMOS tube (M7) is connected with the drain electrode of the seventh PMOS tube (M7) and the source electrode of the eighth PMOS tube (M8), the grid electrode of the eighth PMOS tube (M8) is connected with the drain electrode of the eighth PMOS tube (M8), the drain electrode of the second PMOS tube (M2) and the grid electrode of the ninth PMOS tube (M9), the drain electrode of the second PMOS tube (M2), the grid electrode of the eighth PMOS tube (M8) and the grid electrode of the ninth PMOS tube (M9) are connected with the positive plate of the second capacitor (C2).

4. The high performance level shift circuit of claim 1, wherein: a power supply (VM) of an internal circuit of the H bridge (2) is connected with the drain electrode of a third NMOS tube (HP 1) and the drain electrode of a fourth NMOS tube (HP 2) in parallel, and the source electrode of the third NMOS tube (HP 1) is connected with the drain electrode of a fifth NMOS tube (LP 1) and is also connected with one end of an inductor (L1); the source electrode of the fourth NMOS tube (HP 2) is connected with the drain electrode of the sixth NMOS tube (LP 2), and the other end of the inductor (L1) is connected; the sources of the fifth NMOS transistor (LP 1) and the sixth NMOS transistor (LP 2) are connected in parallel and are grounded together.

5. The high performance level shifter circuit of claim 4, wherein: the power supply voltage in the internal circuit of the H bridge (2) is 40V, and the inductor (L1) is an adjustable inductor.

6. The high performance level shift circuit of claim 1, wherein: VDD (3) is 5V.