CN215010200U

CN215010200U - Driver control circuit and driver capable of forming dead time

Info

Publication number: CN215010200U
Application number: CN202120381240.6U
Authority: CN
Inventors: 邵滨
Original assignee: Shanghai Sillumin Semiconductor Co ltd
Current assignee: Shanghai Sillumin Semiconductor Co ltd
Priority date: 2021-02-20
Filing date: 2021-02-20
Publication date: 2021-12-03
Anticipated expiration: 2031-02-20

Abstract

The utility model provides a can form dead time's driver control circuit and driver, wherein driver control circuit includes: the circuit comprises a reference voltage operational amplifier, a transistor module, a charging module, a comparison module and a capacitor; a first input end of the reference voltage operational amplifier is connected with an original reference voltage, an output end of the reference voltage operational amplifier is connected with a control end of the transistor module, a first end of the transistor module is connected with a first power supply, and a second end of the transistor module is connected with a second input end of the reference voltage operational amplifier; the output end of the reference voltage operational amplifier is connected with the charging module and the comparison module, the charging module is connected with the first power supply, the charging module is connected with a conducting state signal of a current turn-off switch, the charging module is connected with a first end of the capacitor, the first end of the capacitor is connected with the comparison module, and a second end of the capacitor is grounded; and the output end of the comparison module is directly or indirectly connected with the current switch to be conducted.

Description

Driver control circuit and driver capable of forming dead time

Technical Field

The utility model relates to the field of electronic technology, especially, relate to a driver control circuit and driver that can form dead time.

Background

The push-pull connected transistor switches are alternately turned on and off to change the direction of current in the coil. In order to avoid unwanted current surges caused by the simultaneous conduction of the two transistors, the control circuit introduces dead time (dead time) characteristics in the switching action. During the dead time, the control circuit remains in the off drive state even if the front-end system signals that another transistor is to be turned on.

In the prior art, in the dead time generation circuit, in order to improve the noise immunity of the circuit, a capacitor needs to be connected in parallel beside an external resistor, the size of the capacitor can influence the stability of an amplifier feedback network in the dead time generation circuit, and further influence the dead time, and the dead time generation circuit has a small application range.

SUMMERY OF THE UTILITY MODEL

The utility model provides a can form dead time's driver control circuit and driver to solve the problem that the circuit is unstable, accommodation is little.

According to a first aspect of the present invention, there is provided a driver control circuit capable of forming a dead time, comprising: the circuit comprises a reference voltage operational amplifier, a transistor module, a charging module, a comparison module and a capacitor;

a first input end of the reference voltage operational amplifier is connected with an original reference voltage, an output end of the reference voltage operational amplifier is connected with a control end of the transistor module, a first end of the transistor module is connected with a first power supply, and a second end of the transistor module is connected with a second input end of the reference voltage operational amplifier;

the output end of the reference voltage operational amplifier is further connected with the first input end of the charging module and the first input end of the comparison module, and the reference voltage operational amplifier is used for: generating a target reference voltage according to the original reference voltage, and feeding the target reference voltage back to the comparison module and the charging module; the voltage values of the target reference voltage and the original reference voltage are different;

a second input end of the charging module is connected with the first power supply, a third input end of the charging module is connected with a conducting state signal of a current turn-off switch, the conducting state signal represents the conducting state of a corresponding switch, and the current turn-off switch is a switch which is currently turned off in two switches connected in series in the driver;

the charging module is connected with the first end of the capacitor, and the charging module is used for: charging the capacitor according to the target reference voltage and the conducting state signal;

the first end of the capacitor is connected with the second input end of the comparison module, and the second end of the capacitor is grounded;

the output end of the comparison module is directly or indirectly connected with a switch to be conducted currently, the comparison module is used for directly or indirectly controlling the switch to be conducted currently to be conducted to form the dead time when the voltage of the capacitor is higher than the target reference voltage, the dead time is smaller than the time period before the switch to be conducted is conducted currently after the current turn-off switch is turned off, and the switch to be conducted currently is a switch to be conducted currently in two switches which are connected in series in the driver.

Optionally, the charging module includes a first charging unit and a second charging unit; the first charging unit is connected to the first power supply through the second charging unit, the first charging unit is further connected to the conducting signal, the second charging unit is further connected to the target reference voltage, and the first end of the capacitor is connected with the first charging unit and the second charging unit;

the first charging unit is configured to: when the current turn-off switch is in a turn-on state, charging the capacitor so that the voltage of the capacitor is at a basic voltage, and when the current turn-off switch is in a turn-off state, stopping charging the capacitor;

the second charging unit is configured to: when the first charging unit stops charging the capacitor, charging the capacitor so that the voltage of the capacitor reaches a saturation voltage; the base voltage is lower than the target reference voltage, and the saturation voltage is higher than the target reference voltage.

Optionally, the capacitor is a gate oxide capacitor, and the base voltage is matched with a threshold voltage of the gate oxide capacitor.

Optionally, the first charging unit includes a first charging transistor and a second charging transistor;

a control electrode of the first charging transistor is connected to the conducting state signal, a first electrode of the first charging transistor is connected to a second electrode of the second charging transistor, and the second electrode of the second charging transistor is connected to the ground;

and the control electrode and the first electrode of the second charging transistor are connected with the first end of the capacitor.

Optionally, the first charging unit further includes a first specific transistor, and a lowest withstand voltage between a first pole and a second pole of the first specific transistor is higher than a highest withstand voltage between the first pole and the second pole of any one of the charging transistors;

the control electrode of the first appointed transistor is connected with the first end of the capacitor, the first electrode of the first appointed transistor is connected with the first electrode of the first charging transistor, and the second electrode of the first appointed transistor is connected with the second electrode of the second charging transistor.

Optionally, the second charging unit includes a third charging transistor, a fourth charging transistor and a fifth charging transistor,

a control electrode of the third charging transistor is connected with an output end of the reference voltage operational amplifier, a first electrode of the third charging transistor is connected with a control electrode of the fourth charging transistor and a first electrode of the fourth charging transistor, and a second electrode of the third charging transistor is connected with an external resistor;

a second pole of the fourth charging transistor is connected with the first power supply, and a control pole of the fourth charging transistor is connected with a control pole of the fifth charging transistor;

and a first pole of the fifth charging transistor is connected with the first end of the capacitor, and a second pole of the fifth charging transistor is connected with the first power supply.

Optionally, the second charging unit further includes a sixth charging transistor;

and the control electrode of the sixth charging transistor is connected with the control electrode of the fourth charging transistor, and the first electrode of the sixth charging transistor is connected with the first power supply.

Optionally, the second charging unit further includes a second designated transistor, and a lowest withstand voltage between a first pole and a second pole of the second designated transistor is higher than a highest withstand voltage between the first pole and the second pole of any one of the charging transistors;

and the control electrode of the second designated transistor is connected with the control electrode of the third charging transistor, the first electrode of the second designated transistor is connected with the external resistor, and the second electrode of the second designated transistor is connected with the second electrode of the third charging transistor.

Optionally, the driver control circuit further comprises a first current source,

the first end of the first current source is connected with the second input end of the reference voltage operational amplifier, and the second end of the first current source is connected with the ground.

Optionally, the transistor module includes a seventh transistor and a third specified transistor, and a lowest withstand voltage between the first pole and the second pole of the third specified transistor is higher than a highest withstand voltage between the first pole and the second pole of any one of the charging transistors;

a control electrode of the seventh transistor is connected with an output end of the reference voltage operational amplifier, a first electrode of the seventh transistor is connected with the first power supply, and a second electrode of the seventh transistor is connected with a second electrode of the third appointed transistor;

and the control electrode of the third appointed transistor is connected with the output end of the reference voltage operational amplifier, and the first electrode of the third appointed transistor is connected with the second input end of the reference voltage operational amplifier.

Optionally, the comparison module includes a comparator, a first input end of the comparator is connected to the output end of the reference voltage operational amplifier, a second input end of the voltage comparator is connected to the charging module, and an output end of the comparator is directly or indirectly connected to the current switch to be turned on.

Optionally, the driver control circuit further includes a bias module, and a first end of the bias module is connected to the charging module and a second end of the bias module is connected to the comparing module;

the bias module is used for adjusting the delay time of the comparison module according to the charging speed of the charging module for charging the capacitor.

Optionally, the bias module includes a first bias transistor, a second bias transistor, and a second current source;

the first pole and the control pole of the first bias transistor are connected with the charging module, the control pole of the first bias transistor is connected with the control pole of the second bias transistor, and the second pole of the first bias transistor is connected with the ground;

the first pole of the second bias transistor is connected with the comparison module, and the second pole of the second bias transistor is connected with the ground;

and two ends of the second current source are respectively connected with the third input end of the comparison module and the ground.

According to a second aspect of the present invention, there is provided a driver, comprising a first driver control circuit, a second driver control circuit, a first switch and a second switch, wherein the first driver control circuit and the second driver control circuit are both the driver control circuit capable of forming dead time related to the first aspect of the present invention and its optional scheme;

a third input end of a charging module in the first driver control circuit is connected to the conducting state signal of the first switch;

the output end of a comparison module in the first driver control circuit is directly or indirectly connected with the control electrode of the second switch so as to directly or indirectly control the second switch to be conducted according to the conducting state signal of the first switch and output a first control signal for controlling the second switch to be conducted;

a third input end of a charging module in the second driver control circuit is connected with a conducting state signal of a second switch;

the output end of a comparison module in the second driver control circuit is directly or indirectly connected with the control electrode of the first switch so as to output a second control signal for controlling the conduction of the first switch;

after the first switch is turned off, the first switch is the current turn-off switch, and the second switch is the current switch to be turned on; after the second switch is turned off, the second switch is the current off switch, and the first switch is the current switch to be turned on;

a first pole of the second switch is connected with a second power supply, and a second pole of the second switch is connected with a first pole of the first switch; the second pole of the first switch is connected to ground.

Optionally, the driver further includes a first logic circuit and a second logic circuit;

the first input end of the first logic circuit is connected with the output end of the first driver control circuit, the second input end of the first logic circuit is connected with the conducting state signal of the second switch, and the output end of the first logic circuit is directly or indirectly connected with the second switch so as to control the second switch to be conducted according to the conducting state signal of the second switch and the first control signal;

the first input end of the second logic circuit is connected with the output end of the second driver control circuit, the second input end of the second logic circuit is connected with the conducting state signal of the first switch, and the output end of the logic circuit is directly or indirectly connected with the first switch so as to control the first switch to be conducted according to the conducting state signal of the first switch and the second control signal.

Optionally, the first logic circuit includes a first not gate and a first and gate, and the second logic circuit includes a second not gate and a second and gate;

the input end of the first not gate is connected with the output end of the comparison module of the first driver control circuit, and the output end of the first not gate is connected with the first input end of the first and gate so as to invert the first control signal and feed the first control signal back to the first input end of the first and gate;

the second input end of the first AND gate is connected with the conducting state signal of the second switch, and the output end of the first AND gate is connected with the control electrode of the second switch directly or indirectly so as to output a logic signal for controlling the conduction of the second switch;

the second not gate is connected with the output end of the comparison module of the second driver control circuit, and the output end of the second not gate is connected with the first input end of the second and gate so as to invert the second control signal and feed the second control signal back to the first input end of the second and gate;

the second input end of the second AND gate is connected with the conducting state signal of the first switch, and the output end of the second AND gate is connected with the control electrode of the first switch directly or indirectly so as to output a logic signal for controlling the conduction of the first switch.

The utility model provides a can form dead time's driver control circuit and driver, the feedback loop that reference voltage fortune was put is independent of to the module of charging wherein for the stability of the feedback loop that reference voltage fortune was put is higher, and then, and is more accurate to the control of driver.

The utility model discloses an among the alternative, adopt the grid oxygen electric capacity, reduced the technological deviation of on-chip integrated capacitor and caused, to the control deviation of two switches.

The utility model discloses an in the alternative, increase the biasing module for the delay time of comparison module and the charge time phase-match of the module of charging, for example, when the resistance of external resistance is big, the charge speed of the module of charging to electric capacity is faster, and then the biasing module can shorten the delay time of comparison module according to electric capacity charge speed.

The utility model discloses an in the alternative, adopt a plurality of high-voltage transistors, for the resistance of external resistance provides bigger scope, also can prevent the transistor reverse conduction simultaneously, produce adverse effect to the circuit.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 is a first schematic structural diagram of a driver control circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a driver control circuit according to an embodiment of the present invention;

fig. 3 is a first schematic circuit diagram of a driver control circuit according to an embodiment of the present invention;

fig. 4 is a second schematic circuit diagram of a driver control circuit according to an embodiment of the present invention;

fig. 5 is a third schematic circuit diagram of a driver control circuit according to an embodiment of the present invention;

fig. 6 is a fourth schematic circuit diagram of the driver control circuit according to an embodiment of the present invention;

fig. 7 is a fifth schematic circuit diagram of a driver control circuit according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a driver control circuit according to an embodiment of the present invention;

fig. 9 is a signal waveform diagram one of a driver control circuit according to an embodiment of the present invention;

fig. 10 is a signal waveform diagram ii of a driver control circuit according to an embodiment of the present invention;

fig. 11 is a sixth schematic circuit diagram of a driver control circuit according to an embodiment of the present invention;

fig. 12 is a first schematic structural diagram of an actuator according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The technical solution of the present invention will be described in detail with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

Referring to fig. 1, a driver control circuit 11 capable of forming a dead time includes: a reference voltage operational amplifier U1, a transistor module 111, a charging module 112, a comparison module 113 and a capacitor Cramp;

a first input end of the reference voltage operational amplifier U1 is connected with an original reference voltage Vr, an output end of the reference voltage operational amplifier U1 is connected with a control end of the transistor module 111, a first end of the transistor module 111 is connected with a first power supply Vcc, and a second end of the transistor module 111 is connected with a second input end of the reference voltage operational amplifier U1;

the output terminal of the reference voltage op-amp U1 is further connected to the first input terminal of the charging module 112 and the first input terminal of the comparing module 113, and the reference voltage op-amp U1 is configured to: generating a target reference voltage Vr _ ramp according to the original reference voltage Vr, and feeding the target reference voltage Vr _ ramp back to the comparison module 113 and the charging module 112; the target reference voltage Vr _ ramp is different from the original reference voltage Vr in voltage value;

a second input end of the charging module 112 is connected to the first power supply Vcc, a third input end of the charging module 112 is connected to an on-state signal in of a current turn-off switch, the on-state signal in represents an on state of a corresponding switch, and the current turn-off switch is a switch which is currently turned off in two switches connected in series in a driver;

the charging module 112 is connected to a first end of the capacitor Cramp, and the charging module 112 is configured to: charging the capacitor Cramp according to the target reference voltage Vr _ ramp and the on-state signal in;

the first end of the capacitor Cramp is connected to the second input end of the comparison module 113, and the second end of the capacitor Cramp is grounded;

the output end of the comparing module 113 is directly or indirectly connected to a switch to be turned on, and the comparing module 113 is configured to directly or indirectly control the switch to be turned on when the voltage of the capacitor Cramp is higher than the target reference voltage Vr _ ramp, so as to form the dead time t_DTSaid dead time t_DTAnd the current switch-on time period is less than the current time period before the current switch-on switch is switched on after the current switch-off switch is switched off, and the current switch-on switch is a current switch-on switch of two switches connected in series in the driver.

The on-state signal in represents an on-state of a switch (a first switch or a second switch) in the driver, and specifically, the on-state signal may be a logic signal for controlling the corresponding switch to be turned on or off, for example, the on-state signal may be a signal directly or indirectly sent to a control electrode of the corresponding switch by a controller, the on-state signal of the second switch K2 is the on-state signal in2, and the on-state signal of the first switch K2 is the on-state signal in 1.

In one example, the specific operation process of the charging module 112 for charging the capacitor Cramp is as follows:

when the on-state signal connected to the charging module 112 is at a high level, the charging module 112 charges the capacitor Cramp according to the on-state signal, so that the voltage of the capacitor Cramp is at the base voltage VTH;

when the on-state signal connected to the charging module 112 is at a low level, the charging module 112 charges the capacitor Cramp according to the target reference voltage Vr _ ramp, so that the voltage of the capacitor Cramp reaches the saturation voltage Vs; the base voltage VTH is lower than the target reference voltage Vr _ ramp, and the saturation voltage Vs is higher than the target reference voltage Vr _ ramp;

in the process that the charging module 112 charges the capacitor Cramp according to the target reference voltage Vr _ ramp, when the voltage of the capacitor Cramp is higher than the target reference voltage Vr _ ramp, the output result of the comparing module 113 is inverted, and the current switch to be turned on can be directly or indirectly controlled to be turned on.

The charging module is independent of a feedback loop of the reference voltage operational amplifier, so that the stability of the feedback loop of the reference voltage operational amplifier is higher, and further, the control of the driver is more accurate.

Referring to fig. 2, in one embodiment, the charging module 112 includes a first charging unit 1121 and a second charging unit 1122; the first charging unit 1121 is connected to the first power source Vcc through the second charging unit 1122, the first charging unit 1121 is further connected to the on-state signal, the second charging unit 1122 is further connected to the target reference voltage Vr _ ramp, and a first end of the capacitor Cramp is connected to the first charging unit 1121 and the second charging unit 1122;

the first charging unit 1121 is configured to: when the current turn-off switch is in a turn-on state, charging the capacitor Cramp so that the voltage of the capacitor Cramp is at a basic voltage VTH, and when the current turn-off switch is in a turn-off state, stopping charging the capacitor Cramp;

the second charging unit 1122 is configured to: when the first charging unit 1121 stops charging the capacitor Cramp, charging the capacitor Cramp so that the voltage of the capacitor Cramp reaches a saturation voltage Vs; the base voltage VTH is lower than the target reference voltage Vr _ ramp, and the saturation voltage Vs is higher than the target reference voltage Vr _ ramp.

Above can understand that, when the present switch-off is in the conducting state under the control of the conducting state signal, even if the conducting state signal of the present switch-on to be switched on changes to control the switch-on to be switched on, because of the work of the driver control circuit 11, the present switch-on to be switched on will not be switched on at once, but a delay of a period of time needs to appear, so that two switches will not be switched on simultaneously, and further the two outputs of the driver will not influence each other.

In one embodiment, the capacitor Cramp is a gate oxide capacitor, and the base voltage VTH is matched to a threshold voltage of the gate oxide capacitor.

In the above embodiment, when the voltage across the gate oxide capacitor is lower than the threshold voltage, the capacitance of the gate oxide capacitor changes with the increase of the voltage across the gate oxide capacitor, and after the voltage across the gate oxide capacitor reaches the threshold voltage, the capacitance is almost unchanged, and the voltage across the gate oxide capacitor changes linearly, so that the accuracy of the generated dead time is not affected.

In the above embodiment, the gate oxide capacitor is used instead of other capacitors, so that the control deviation of the two switches caused by the process deviation of the on-chip integrated capacitor is reduced.

Referring to fig. 3, in one embodiment, the first charging unit 1121 includes a first charging transistor M1 and a second charging transistor M2;

the control electrode of the first charging transistor M1 is connected to the conducting state signal, the first electrode of the first charging transistor M1 is connected to the second electrode of the second charging transistor M2, and the second electrode of the second charging transistor M2 is connected to the ground;

the control electrode and the first electrode of the second charging transistor M2 are connected to the first end of the capacitor Cramp.

The transistors may be NFETs, i.e., pairs of complementary N-channel MOSFETs, or PFETs, i.e., pairs of complementary P-channel MOSFETs, whether NFETs or PFETs, the control electrodes of the transistors may be understood as the gates of the field effect transistors, and the first and second electrodes of the transistors may be understood as the sources and drains of the field effect transistors.

In one embodiment, the first charging unit 1121 further includes a first designated transistor N1, and a lowest withstand voltage between a first pole and a second pole of the first designated transistor is higher than a highest withstand voltage between the first pole and the second pole of any one of the above charging transistors;

the control electrode of the first designated transistor N1 is connected to the first terminal of the capacitor Cramp, the first electrode of the first designated transistor N1 is connected to the first electrode of the first charge transistor M1, and the second electrode of the first designated transistor N1 is connected to the second electrode of the second charge transistor M2.

The first designated transistor can be, for example, a high-voltage transistor with the lowest withstand voltage between the first pole and the second pole of the transistor not lower than 5V, so that a larger voltage variation range is provided for the circuit, and meanwhile, the reverse conduction of the transistor in the circuit can be prevented, and the adverse effect on the circuit can be generated.

Referring to fig. 4, in one embodiment, the second charging unit 1122 includes a third charging transistor M3, a fourth charging transistor M4, and a fifth charging transistor M5,

a control electrode of the third charging transistor M3 is connected to an output end of the reference voltage operational amplifier U1, a first electrode of the third charging transistor M3 is connected to a control electrode of the fourth charging transistor M4 and a first electrode of the fourth charging transistor M4, and a second electrode of the third charging transistor M3 is connected to an external resistor R_DT；

A second pole of the fourth charging transistor M4 is connected to the first power source Vcc, and a control pole of the fourth charging transistor M4 is connected to the control pole of the fifth charging transistor M5;

a first pole of the fifth charging transistor M5 is connected to a first terminal of the capacitor Cramp, and a second pole of the fifth charging transistor M5 is connected to the first power Vcc.

Wherein the external resistor R_DTBy PINThe pin is connected to the second pole of the third charge transistor M3, and its resistance value can be changed.

In one example, the external resistor R_DTThe two ends of the capacitor can be connected with an external capacitor in parallel, so that the noise suppression capability of the driver control circuit can be improved, and the external capacitor and a feedback loop of the reference voltage operational amplifier are independently opened, so that a hardware basis is provided for a larger value range of the external capacitor.

In one embodiment, the second charging unit 1122 further includes a sixth charging transistor M6;

a control electrode of the sixth charging transistor M6 is connected to a control electrode of the fourth charging transistor M4, and a first electrode of the sixth charging transistor M6 is connected to the first power Vcc.

In one embodiment, the second charging unit 1122 further includes a second designated transistor N2, and the lowest withstand voltage between the first pole and the second pole of the second designated transistor N2 is higher than the highest withstand voltage between the first pole and the second pole of any of the above charging transistors;

a control electrode of the second specifying transistor N2 is connected to a control electrode of the third charging transistor M3, and a first electrode of the second specifying transistor N2 is connected to the external resistor R_DTA second pole of the second designated transistor N2 is connected to a second pole of the third charge transistor M3.

The second specified transistor may be, for example, a high-voltage transistor in which the lowest withstand voltage between the first and second electrodes of the transistor is not lower than 5V.

In one example, the current amplification of the third charging transistor M3 and the second charging transistor M2 may be the same; in another example, the current amplification factor of the third charging transistor and the second charging transistor may be different.

In one example, the current amplification of the fourth charging transistor M4 and the fifth and sixth charging transistors M5 and M6 may be the same; for another example, the current amplification factors of the fourth charging transistor M4 and the fifth and sixth charging transistors M5 and M6 may be different.

In one example, the third charge transistor M3 and the second charge transistor M2 are PFETs, and the fourth charge transistor M4, the fifth charge transistor M5, and the sixth charge transistor M6 are NFETs; in another example, the third charging transistor M3 and the second charging transistor M2 are both NFETs, and the fourth charging transistor M4, the fifth charging transistor M5 and the sixth charging transistor M6 are all PFETs; it can be seen that the third and second charging transistors M3 and M2 are of a different channel type than the fourth, fifth and sixth charging transistors M4, M5 and M6.

Referring to fig. 5, in one embodiment, the driver control circuit 11 further includes a first current source I1,

the first end of the first current source I1 is connected to the second input end of the reference voltage operational amplifier U1, and the second end of the first current source I1 is connected to ground.

Referring to fig. 6, in one embodiment, the transistor module 111 includes a seventh transistor M7 and a third designated transistor N3;

a control electrode of the seventh transistor M7 is connected to the output terminal of the reference voltage operational amplifier U1, a first electrode of the seventh transistor M7 is connected to the first power source Vcc, and a second electrode of the seventh transistor M7 is connected to a second electrode of the third designated transistor N3;

the control electrode of the third designated transistor N3 is connected to the output end of the reference voltage operational amplifier U1, and the first electrode of the third designated transistor N3 is connected to the second input end of the reference voltage operational amplifier U1.

The third designated transistor may be, for example, a high-voltage transistor in which the lowest withstand voltage between the first and second electrodes of the transistor is not lower than 5V, and the seventh transistor M7 may be, for example, a low-voltage transistor in which the highest withstand voltage between the first and second electrodes of the transistor is not higher than 5V.

In one example, the seventh transistor M7 and the third designated transistor N3 are both PFETs, and in another example, the seventh transistor M7 and the third designated transistor N3 are both NFETs.

In an example, the transistor module 111 does not include the third designated transistor N3, and the charging module 112 does not include the first designated transistor N1 and the second designated transistor N2, and it can be seen that the first designated transistor N1, the second designated transistor N2 and the third designated transistor N3 can be selectively adopted according to practical application scenarios.

Referring to fig. 7, in one embodiment, the comparing module 113 includes a comparator U2, a first input terminal of the comparator U2 is connected to the output terminal of the reference voltage operational amplifier U1, a second input terminal of the voltage comparator U2 is connected to the charging module 112, and an output terminal of the comparator U2 is directly or indirectly connected to the currently-to-be-turned-on switch.

When the magnitude relationship between the two input ends of the comparator U2 changes, the output end of the comparator U2 does not change the level immediately, but changes the level after a time delay.

In one example, the delay time of the comparator U2 can be changed by adding a bias current to the comparator U2 or changing the magnitude of the bias current.

Referring to fig. 8, in an embodiment, the driver control circuit 11 further includes a bias module 114, a first end of the bias module 114 is connected to the charging module 112, and a second end of the bias module 114 is connected to the comparing module 113;

the bias module 114 is configured to adjust the delay time of the comparing module 113 according to the charging speed of the charging module 112 for charging the capacitor Cramp.

The operation of the biasing module 114 in one embodiment is described below in conjunction with fig. 9-10:

in fig. 9 and 10, the signal waveform corresponding to in1_ dt is the signal waveform at the output terminal of the comparator U2, the value corresponding to VTH represents the base voltage value of the capacitor Cramp, the dashed line corresponding to Vs represents the voltage value of the saturation voltage of the capacitor Cramp, the dashed line corresponding to Vr _ ramp represents the voltage value of the target reference voltage, and the signal waveform corresponding to in1 is the on-state signal.

When the charging module 112 is in use, the external resistor R_DTWhen the voltage is larger, the charging speed of the charging module 112 to charge the capacitor Cramp is slower, and further, the bias module 114 provides the comparator U2 with the voltageThe bias current supplied is relatively small and the delay of comparator U2 is slightly larger;

when the charging module 112 is in use, the external resistor R_DTWhen the charging speed of the capacitor Cramp charged by the charging module 112 is relatively fast, and therefore the bias current provided by the bias module 114 to the comparator U2 is relatively large, if the extra current of the comparator U2 is still kept small, the delay of the comparator is relatively large, such as the dashed line in fig. 10, and thus the relative error introduced by the comparator is large, and if the extra current of the comparator varies with the charging current, the delay of the comparator is also reduced when the charging speed of the capacitor Cramp charged is relatively fast, such as the dashed line in fig. 10, and thus the relative error introduced by the comparator is also reduced.

Referring to fig. 11, in one embodiment, the bias module 114 includes a first bias transistor M8, a second bias transistor M9, a second current source I2;

the first pole and the control pole of the first bias transistor M8 are connected to the charging module 112, the control pole of the first bias transistor M8 is connected to the control pole of the second bias transistor M9, and the second pole of the first bias transistor M8 is connected to ground;

a first pole of the second bias transistor M9 is connected to the comparison module 113, and a second pole of the second bias transistor M9 is connected to ground;

two ends of the second current source I2 are respectively connected to the third input terminal of the comparing module 113 and ground.

In one example, the first and control electrodes of the first bias transistor M8 are connected to the second electrode of the sixth charge transistor M6.

In one example, the current amplification of the first bias transistor M8 and the second bias transistor M9 may be the same; for another example, the current amplification of the first bias transistor M8 and the second bias transistor M9 may be different.

In one example, the first biasing transistor M8 and the second biasing transistor M9 are both PFETs, and in another example, the first biasing transistor M8 and the second biasing transistor M9 are both NFETs.

Referring to fig. 12, the driver includes a first driver control circuit 11, a second driver control circuit 12, a first switch K1 and a second switch K2, wherein the first driver control circuit 11 and the second driver control circuit 12 are all the aforementioned driver control circuits capable of forming dead time;

a third input end of a charging module in the first driver control circuit 11 is connected to an on-state signal in1 of the first switch;

the output end of the comparison module in the first driver control circuit 11 is directly or indirectly connected to the control electrode of the second switch K2 to output a first control signal in1 for controlling the second switch K2 to be turned on;

a third input end of a charging module in the second driver control circuit 12 is connected to a conducting state signal in2 of a second switch;

the output end of the comparison module in the second driver control circuit 12 is directly or indirectly connected to the control electrode of the first switch K1 to output a second control signal for controlling the first switch K1 to be turned on;

after the first switch K1 is turned off, the first switch K1 is the currently turned-off switch, and the second switch K2 is the currently to-be-turned-on switch; after the second switch K2 is turned off, the second switch K2 is the currently turned-off switch, and the first switch K1 is the currently to-be-turned-on switch;

a first pole of the second switch K2 is connected to a second power source, and a second pole of the second switch K2 is connected to a first pole of the first switch K1; the second pole of the first switch K1 is connected to ground.

The first driver control circuit 11 and the second driver control circuit 12 ensure that the first switch K1 and the second switch K2 are not simultaneously turned on, and the interval time for which the switches are not simultaneously turned on is longer than the dead time.

In one embodiment, the driver further comprises a first logic circuit 13, a second logic circuit 14;

a first input terminal of the first logic circuit 13 is connected to the output terminal of the first driver control circuit 11, a second input terminal of the first logic circuit 13 is connected to a conduction state signal in2 of a second switch, and an output terminal of the first logic circuit 13 is directly or indirectly connected to the second switch K2, so as to control the second switch K2 to be turned on according to the conduction state signal in2 of the second switch and the first control signal in1_ dt;

the first input terminal of the second logic circuit 14 is connected to the output terminal of the second driver control circuit 12, the second input terminal of the second logic circuit 14 is connected to the on-state signal in1 of the first switch, and the output terminal of the logic circuit 14 is directly or indirectly connected to the first switch K1, so as to control the first switch K1 to be turned on according to the on-state signal in1 of the first switch and the second control signal in2_ dt.

In one example, the driver further includes a first amplifier U3 and a second amplifier U4, an input terminal of the first driver U3 is connected to an output terminal of the first logic circuit 13 to amplify a signal out1 output by the first logic circuit 13 to drive the second switch K2 to be turned on;

the input terminal of the second driver U4 is connected to the output terminal of the second logic circuit 14 to amplify the signal out2 output by the second logic circuit 14 to drive the first switch K1 to be turned on.

In one embodiment, the first logic circuit 13 includes a first not gate U5 and a first and gate U6, and the second logic circuits each include a second not gate U7 and a second and gate U8;

an input end of the first not gate U5 is connected to an output end of a comparison module in the first driver control circuit 11, and an output end of the first not gate U5 is connected to a first input end of the first and gate U6, so as to invert the first control signal in1_ dt output by the first driver control circuit 11 and feed back the first control signal in1_ dt to the first input end of the first and gate U6;

a second input end of the first and gate U6 is connected to a conducting state signal in2 of the second switch, and an output end of the first and gate is connected to a control electrode of the second switch directly or indirectly, so as to output a logic signal out2 for controlling the conduction of the second switch;

the second not gate U7 is connected to the output end of the comparison module in the second driver control circuit 12, and the output end of the second not gate U7 is connected to the first input end of the second and gate U8, so as to invert the second control signal in2_ dt output by the second driver control circuit 12 and feed back the inverted signal to the first input end of the second and gate U8;

a second input end of the second and gate U8 is connected to a conducting state signal in1 of the first switch, and an output end of the second and gate U8 is connected to a control electrode of the first switch K1 directly or indirectly, so as to output a logic signal out1 for controlling the conduction of the first switch.

In an embodiment of the present invention, the signal waveforms outputted from several key positions of the driver.

Wherein the signal waveform corresponding to in1 is the waveform of the on-state signal of the first switch, and the signal waveform corresponding to in2 is the waveform of the on-state signal of the second switch;

the signal waveform corresponding to in1_ dt is the waveform of the first control signal output by the comparison module of the first driver control circuit 11, and the signal waveform corresponding to in2_ dt is the waveform of the second control signal output by the comparison module of the second driver control circuit 12;

out1 is the signal waveform outputted by the first logic circuit 13, which can control the second switch K2 to be turned on; out2 is the signal waveform outputted from the second logic circuit 14, which can control the first switch K1 to be turned on.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims

1. A driver control circuit capable of forming a dead time, comprising: the circuit comprises a reference voltage operational amplifier, a transistor module, a charging module, a comparison module and a capacitor;

2. The driver control circuit capable of forming a dead time of claim 1, wherein the charging module comprises a first charging unit and a second charging unit; the first charging unit is connected to the first power supply through the second charging unit, the first charging unit is further connected to the conducting state signal, the second charging unit is further connected to the target reference voltage, and the first end of the capacitor is connected with the first charging unit and the second charging unit;

3. The driver control circuit capable of developing dead time of claim 2, wherein the capacitor is a gate oxide capacitor, and the base voltage is matched to a threshold voltage of the gate oxide capacitor.

4. The driver control circuit capable of forming a dead time according to claim 2, wherein the first charging unit includes a first charging transistor and a second charging transistor;

5. The driver control circuit capable of forming a dead time according to claim 4, wherein the first charging unit further includes a first specific transistor, a lowest withstand voltage between a first pole and a second pole of the first specific transistor is higher than a highest withstand voltage between the first pole and the second pole of any one of the charging transistors;

6. The driver control circuit capable of forming a dead time according to claim 2, wherein the second charging unit includes a third charging transistor, a fourth charging transistor, and a fifth charging transistor,

7. The driver control circuit capable of forming a dead time of claim 6, wherein the second charging unit further comprises a sixth charging transistor;

8. The driver control circuit capable of forming a dead time according to claim 6, wherein the second charging unit further includes a second specifying transistor, a lowest withstand voltage between a first pole and a second pole of the second specifying transistor is higher than a highest withstand voltage between the first pole and the second pole of any one of the charging transistors;

9. The driver control circuit capable of developing dead time of claim 1, further comprising a first current source,

10. The driver control circuit capable of forming dead time according to claim 1, wherein the transistor module includes a seventh transistor and a third specified transistor, and a lowest withstand voltage between a first pole and a second pole of the third specified transistor is higher than a highest withstand voltage between a first pole and a second pole of any one of the charge transistors;

11. The driver control circuit capable of forming dead time according to claim 1, wherein the comparison module comprises a comparator, a first input terminal of the comparator is connected to the output terminal of the reference voltage op-amp, a second input terminal of the comparator is connected to the charging module, and an output terminal of the comparator is directly or indirectly connected to the switch to be turned on.

12. The driver control circuit capable of forming dead time according to any one of claims 1 to 11, further comprising a bias module, wherein a first end of the bias module is connected to the charging module and a second end of the bias module is connected to the comparing module;

13. The driver control circuit capable of developing dead time of claim 12, wherein the bias module comprises a first bias transistor, a second current source;

14. A driver comprising a first driver control circuit, a second driver control circuit, a first switch, and a second switch, wherein the first driver control circuit and the second driver control circuit are the driver control circuit capable of forming a dead time according to any one of claims 1 to 13;

a third input end of a charging module in the first driver control circuit is connected with a conducting state signal of the first switch; the output end of a comparison module in the first driver control circuit is directly or indirectly connected with the control electrode of the second switch so as to output a first control signal for controlling the conduction of the second switch;

a third input end of a charging module in the second driver control circuit is connected to the conducting state signal of the second switch;

after the first switch is turned off, the first switch is the current turn-off switch, and the second switch is the current switch to be turned on; after the second switch is turned off, the second switch is the current turn-off switch, and the first switch is the current switch to be turned on;

15. The driver of claim 14, further comprising a first logic circuit, a second logic circuit;

the first input end of the second logic circuit is connected with the output end of the second driver control circuit, the second input end of the second logic circuit is connected with the conducting state signal of the first switch, and the output end of the logic circuit is directly or indirectly connected with the first switch so as to control the first switch to be conducted according to the conducting state signal and the second control signal of the first switch.

16. The driver of claim 15, wherein the first logic circuit comprises a first not gate and a first and gate, and the second logic circuit comprises a second not gate and a second and gate;