CN215073108U - PCB structure with PCB layer number identification mark - Google Patents

Abstract

The utility model discloses a take PCB structure of PCB number of piles discernment mark, PCB board include multilayer PCB layer, every the edge on PCB layer sets up the number of piles flag block, set up in the number of piles flag block and represent the number of piles reference numeral of PCB layer preface, the number of piles does not overlap between the flag block, the orthographic projection region of number of piles flag block sets up side by side. The utility model discloses each PCB layer on the PCB board all sets up a number of piles mark the piece, be provided with the number of piles reference numeral on this number of piles mark the piece, the number of piles reference numeral corresponds the sequence on its place layer, when carrying out the PCB lamination, staff's accessible naked eye discerns the order on each PCB layer, also can be with the number of piles reference numeral that obtains the PCB layer through visual scanning, thereby obtain the range order on each PCB layer, with the condition of avoiding laminating order to go wrong completely, and this mode does not influence original normal production flow and production process, only increase the copper foil of etching when etching the PCB layer.

Description

PCB structure with PCB layer number identification mark

Technical Field

The utility model relates to a PCB designs technical field, and more specifically says, relates to a take PCB structure of PCB number of piles discernment mark.

Background

Pcb (printed Circuit board), which is called printed Circuit board (pcb) in chinese, is a support for electronic components and is a carrier for electrical interconnection of electronic components. Among them, in order to increase an area where wiring can be performed, the PCB is provided using Multi-Layer Boards (Multi-Layer Boards) in which more single or double-sided wiring Boards are used. Printed wiring boards in which multiple PCB layers are alternated with a positioning system and an insulating adhesive material, bonded together and the conductive patterns interconnected as designed, are referred to as multilayer printed wiring boards.

With the rapid development of electronic technology and society, the applications and functions of electronic devices are increased, and the size is required to be miniaturized, so that the density of PCBs is required to be increased and electronic components are required to be increased.

Multilayer PCB adopts the pressfitting technology usually when the preparation, with PCB symmetry separately and machine-shaping back, forms PCB through the pressfitting, under this condition, need guarantee the order that the PCB layer was placed during the pressfitting, otherwise the PCB internally designed's that produces circuit structure is disorderly, unable normal use, may cause PCB's damage even.

Disclosure of Invention

In order to overcome the deficiencies of the prior art, the utility model provides a take PCB structure of PCB number of piles discernment mark.

The utility model discloses technical scheme as follows:

a PCB structure with PCB layer number identification marks is characterized in that a PCB comprises multiple PCB layers, layer number marking blocks are arranged at the edges of the PCB layers, layer number marks representing the layer number of the PCB layers are arranged in the layer number marking blocks, the layer number marking blocks are not overlapped, and orthographic projection areas of the layer number marking blocks are arranged in parallel.

In the above PCB structure with the PCB layer identification mark, the layer number marking block is rectangular.

Further, the size of the layer number indication block is 1mm × 2 mm.

Further, the size of the layer number marking block is 0.5mm × 1 mm.

In the PCB structure with the PCB layer number identification mark, the edge of the short side of the layer number marking block is flush with the edge of the PCB.

According to the PCB structure with the PCB layer number identification mark, the margin of the PCB is provided with the vacant area with the width of 0.5 mm.

In the above PCB structure with the PCB layer number identification mark, the layer number label is etched and disposed on the layer number marking block.

In the PCB structure with the PCB layer number identification mark, the layer number marking block is arranged on the PCB board through etching.

In the PCB structure with the PCB layer number identification mark, the edges of the orthographic projection areas of two adjacent layer number marking blocks are contacted with each other.

In the above PCB structure with the PCB layer number identification mark, the layer number marking blocks are arranged in an increasing or decreasing order according to the layer number label.

In the above PCB structure with the PCB layer identification mark, the layer number marking block is provided with a vacant area with a width of 0.5 mm.

According to the above scheme the utility model discloses, its beneficial effect lies in, the utility model discloses each PCB layer on the PCB board all sets up a number of piles flag block, be provided with the number of piles reference numeral on this number of piles flag block, the number of piles reference numeral corresponds the sequence on its place layer, when carrying out the PCB lamination, staff's accessible naked eye discerns the order on each PCB layer, also can be with the number of piles reference numeral that obtains the PCB layer through visual scanning, thereby obtain the range order on each PCB layer, with the condition of avoiding laminating order to go wrong completely, and this mode does not influence original normal production flow and production process, only increase the copper foil of etching when etching the PCB layer.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of the present invention.

Fig. 2 is a schematic structural diagram of an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of another embodiment of the present invention.

Wherein, in the figures, the respective reference numerals:

1, a PCB board; 2. a layer number marking block; 3. a vacant area; 4. an electronic component.

Detailed Description

In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to illustrate the present invention in further detail. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

It will be understood that when an element is referred to as being "disposed" on another element, it can be directly or indirectly disposed on the other element.

The utility model provides a take PCB structure of PCB number of piles discernment mark, as shown in fig. 2, PCB board 1 structure includes the multilayer PCB layer, and the edge on every PCB layer sets up number of piles flag 2, sets up the number of piles label in the number of piles flag 2, does not overlap between the number of piles flag 2, and the orthographic projection region of the number of piles flag 2 sets up side by side.

In the actual lamination process of the multilayer PCB 1, because the PCB layers are only produced with copper foils layer by layer, a worker can easily identify the sequence of the PCB layer represented by each copper foil through the layer number labels in the layer number marking block 2, or the control end obtains the sequence of the PCB layer where the copper foil is located through visual scanning, so that the PCB layers are not staggered when being laminated, the circuit design is correct, and the product quality is guaranteed.

In the PCB design process, after a designer finishes PCB whole board design, a layer number marking block 2 is designed in a geber file of each layer, and the layer sequence of the PCB layer is marked on the layer number marking block 2. In the present application, the shape of the layer number designation block 2 is not limited at all, but for the sake of convenience of processing and identification, it is preferable that the shape of the layer number designation block 2 is rectangular, as shown in fig. 1. In the present application, the orthographic projection areas of two adjacent layer number indicating blocks 2 are in contact with each other, that is, the orthographic projection areas of the layer number indicating blocks 2 are closely arranged side by side, which means that all the layer number indicating blocks 2 are arranged in the same area of the PCB 1 and are staggered with each other, so that the layer number indicating blocks 2 of each PCB layer can be obviously observed from the geber document, thereby checking and confirming whether the marks of the layer number indicating blocks 2 of the PCB 1 are correct or not and whether the number of the marks is missing or not. In order to better identify the layer sequence of each PCB layer, the layer number marking block 2 is arranged in an increasing or decreasing order according to the sequence of the layer number marks, so that the result is clear.

Based on the function of the layer number indicating block 2, the position of the layer number indicating block 2 does not need to be limited, but it is clear that all the layer number indicating blocks 2 on the same PCB 1 must be placed in the same area to facilitate finding and positioning, and thus, the position of the layer number indicating block 2 needs to be determined according to the actual condition of the PCB 1.

Although the number of layers indicating block 2 can be reduced as much as possible, placing all the number of layers indicating blocks 2 at the same position requires a certain space, and this effect is amplified in the multilayer PCB 1 or the high-density board, and therefore, it is necessary to limit the position and size of the number of layers indicating block 2 to some extent. As shown in fig. 1 and 2, when the short edge of the layer number marking block 2 is flush with the edge of the PCB board 1, the occupied area is relatively small, and the layer number label does not need to be rotated or reduced, which is more beneficial to identifying the layer sequence. Secondly, the width range of 0.5mm apart from its edge sets up vacant district 3 in current PCB board 1, and any line and electronic components 4 are forbidden to set up for reasons such as safety or processing in this area, and the number of piles in this application marks block 2 and can utilize this region to set up.

In one embodiment, as shown in fig. 2, the layer number designation block 2 has a rectangular shape with dimensions of 1mm × 2 mm. In another embodiment, as shown in fig. 3, the layer number designation block 2 has a rectangular shape with dimensions of 0.5mm × 1 mm. The two layer number marking blocks 2 are determined according to the size of the two layer number marking blocks 2, the PCB 1 in the prior art is provided with the empty area 3 of 0.5mm, and the requirement can be met only by needing the width range of 1.5mm, so that the space requirement is relatively easy to meet, and in the PCB 1 with higher density, the size of the layer number marking blocks 2 can be further reduced, and the size space of 0.5mm is searched for to meet the design of the PCB 1 with higher density.

Because the layer number marking block 2 and the layer number label are both made of copper, the layer number marking block and the layer number label can interfere with the wiring on the same layer of PCB, and in consideration of signal filtering and the like, a vacant area 3 needs to be arranged outside the layer number marking block 2 to reject all copper wiring and the bonding pads of the electronic components 4, so as to prevent the layer number marking block 2 from interfering with the wiring on the PCB layer and the electronic components 4.

In the actual production process, the PCB layer is the copper foil layer by layer after the production is finished, the corresponding routing is formed by etching, in order to reduce the influence of the layer number marking block 2 and the layer number mark on the production process of the PCB 1, the layer number marking block 2 and the layer number mark are arranged at the corresponding positions in an etching mode, the layer number marking block 2 and the layer number mark are completed together in the process of etching the routing on the PCB layer, the independent manufacturing and forming are not needed, and any process is not needed.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims (10)

1. The PCB structure with the PCB layer number identification mark is characterized in that a PCB comprises a plurality of PCB layers, each PCB layer is provided with a layer number marking block at the edge, layer number marks representing the sequence of the PCB layers are arranged in the layer number marking blocks, the layer number marking blocks are not overlapped, and orthographic projection areas of the layer number marking blocks are arranged in parallel.

2. The PCB structure with PCB layer number identification mark of claim 1, wherein the layer number marking block is rectangular.

3. The PCB structure with PCB floor identification mark of claim 2, wherein the size of the floor indication block is 1mm x 2 mm.

4. A PCB structure with PCB floor identification mark as claimed in claim 2, wherein the size of the floor indication block is 0.5mm x 1 mm.

5. The PCB structure with the PCB layer number identification mark of claim 1, wherein the edge of the short side of the layer number marking block is flush with the edge of the PCB.

6. The PCB structure with the PCB layer number identification mark of claim 1, wherein the edge of the PCB board is provided with a vacant area with the width of 0.5 mm.

7. The PCB structure with PCB layer number identification mark of claim 1, wherein the layer number marking blocks are arranged in an increasing or decreasing order according to the order of the layer number marks.

8. The PCB structure with PCB layer number identification mark of claim 1, wherein the layer number marking block is etched on the PCB.

9. The PCB structure with PCB layer number identification mark of claim 1, wherein the layer number marking blocks are arranged in an increasing or decreasing order according to the order of the layer number marks.

10. The PCB structure with the PCB layer number identification mark of claim 1, wherein a vacant area with a width of 0.5mm is arranged outside the layer number marking block.

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