CN112738976A - PCB and layer skewness management and control quality detection mechanism thereof - Google Patents
PCB and layer skewness management and control quality detection mechanism thereof Download PDFInfo
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- CN112738976A CN112738976A CN202011305730.4A CN202011305730A CN112738976A CN 112738976 A CN112738976 A CN 112738976A CN 202011305730 A CN202011305730 A CN 202011305730A CN 112738976 A CN112738976 A CN 112738976A
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- 238000001514 detection method Methods 0.000 title claims abstract description 61
- 230000007246 mechanism Effects 0.000 title claims abstract description 26
- 238000005259 measurement Methods 0.000 claims abstract description 48
- 239000004020 conductor Substances 0.000 claims abstract description 18
- 238000012360 testing method Methods 0.000 claims description 11
- 239000011800 void material Substances 0.000 claims description 11
- 238000013461 design Methods 0.000 abstract description 10
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 238000007689 inspection Methods 0.000 description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000003825 pressing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention discloses a layer deviation control quality detection mechanism which comprises a detection package arranged at the same position of the surface of each layer of core board, wherein the detection package comprises a grounding hole arranged on the surface of the core board and used for being connected with any electrode of PCB electrical measurement equipment, and an electrical measurement hole arranged on the surface of the core board, spaced from the grounding hole by a preset distance and used for being connected with the other electrode of the PCB electrical measurement equipment, the aperture of the grounding hole and the aperture of the electrical measurement hole are both equivalent to the aperture of a minimum through hole arranged on the PCB, an annular gap area is arranged on a conductor layer laid on the surface of each layer of core board and extends outwards from the hole wall of the electrical measurement hole, and the radial length of the annular gap area is the maximum allowable layer deviation. The layer deviation control quality detection mechanism disclosed by the invention can improve the detection operation efficiency of the PCB layer deviation control quality, improve the precision and reliability of the detection result and meet the design requirement of a high-density board. The invention also discloses a PCB, which has the beneficial effects as described above.
Description
Technical Field
The invention relates to the technical field of PCBs, in particular to a layer deviation control quality detection mechanism. The invention also relates to a PCB.
Background
Due to market demands, the design and development of PCB cards are increasingly designed with some high-density cards, but the SI/PI performance of the system for the high-density cards is not reduced. Therefore, the design potential of the high-density board card is required to be subjected to limit extrusion on the space utilization rate, the space between a hole and copper needs to be designed to be reduced, but the requirement of signal integrity needs a complete reference layer for signal routing, and the routing cannot be subjected to cross-segmentation and cannot be close to the reference layer. The processing of high density cards is a difficult problem for the PCB manufacturing industry because of the precision deviations and process tolerances necessary for industrial manufacturing.
One of the important inspection criteria in the PCB manufacturing process is layer skewness. Because the PCB is integrally formed by pressing a plurality of layers of core plates and insulating plates and then integrally drilled, and the alignment degree of each layer of core plate can not be aligned by 100% in the pressing process, the copper sheets on each layer of core plate have relative offset, so that the distance from the hole wall to the copper sheets of each layer of core plate also has relative offset in the drilling process, and the relative offset is the layer offset. The lower the layer skewness, the better the PCB processing quality. Because of the limited space of the high-density board, the deviation of the PCB design to the manufacturing process is more strict. Generally, the border of walking to the reference layer can manage and control at about 5 mils, therefore when the layer skewness surpassed 5 mils, the walking can form and stride cuts apart, and the SI performance of PCB can be much worse than the design demand.
In the prior art, there are two general quality inspection schemes for controlling the layer deviation of the PCB, wherein in the first scheme, only the sum of the process calculation tolerances of each core board of the PCB is used as the layer deviation value, and there is no effective layer deviation inspection method at all. And in the second scheme, each through hole on the PCB is sequentially subjected to an electrical test by utilizing PCB electrical test equipment, or only partial through holes are subjected to the electrical test. However, although this method can check whether the PCB layer skewness is qualified, the number of via holes is large, and if each via hole is electrically tested, it takes too long, and the checking efficiency is low; if only the partial through holes are subjected to the electrical test, the contradiction that the inspection results of the partial through holes are qualified and the inspection results of the partial through holes are unqualified due to different apertures of different through holes occurs. In a word, in the prior art, for the inspection of the PCB layer skewness control quality, the operation efficiency is low, or the inspection result precision is low, so that the design requirement of a high-density board is difficult to achieve.
Therefore, how to improve the detection operation efficiency of the PCB layer skewness control quality, improve the accuracy and reliability of the detection result, and meet the design requirements of the high-density board is a technical problem faced by the technical personnel in the field.
Disclosure of Invention
The invention aims to provide a layer deviation control quality detection mechanism which can improve the detection operation efficiency of PCB layer deviation control quality, improve the detection result precision and reliability and meet the design requirements of high-density boards. Another object of the present invention is to provide a PCB.
In order to solve the technical problem, the invention provides a layer deviation control quality detection mechanism which comprises a detection package arranged at the same position of the surface of each layer of core board, wherein the detection package comprises a grounding hole arranged on the surface of the core board and used for being connected with any electrode of PCB electrical measurement equipment, and an electrical measurement hole arranged on the surface of the core board, separated from the grounding hole by a preset distance and used for being connected with the other electrode of the PCB electrical measurement equipment, the aperture of the grounding hole and the aperture of the electrical measurement hole are both equivalent to the aperture of a minimum through hole arranged on the PCB, an annular hollow area is arranged on a conductor layer laid on the surface of each layer of core board and extends outwards from the hole wall of the electrical measurement hole, and the radial length of the annular hollow area is the maximum allowable layer deviation.
Preferably, the electrical measurement holes are formed in the surface of each layer of the core board, the annular vacancy areas are correspondingly formed in the conductor layer, and the radial lengths of the annular vacancy areas are different.
Preferably, the grounding holes and the electrical measurement holes are uniformly distributed on the surface of each layer of the core plate in a straight line.
Preferably, the distance between the centers of the grounding hole and the adjacent electricity measuring holes and the distance between the centers of the adjacent electricity measuring holes are both 40-50 mil.
Preferably, the radial length of each annular vacancy area is 5-6 mil.
Preferably, a first pad is disposed on the conductor layer outside the ground via, a second pad is disposed on the conductor layer outside the annular vacant region, and shapes of the first pad and the second pad are different.
Preferably, the first pad is rectangular and the second pad is circular.
Preferably, 4-8 detection packages are arranged on the surface of each layer of the core board, and each detection package is distributed in each corner area of each layer of the core board.
Preferably, each of the inspection packages is simultaneously distributed on the surface of each layer of the core board and the surface of the auxiliary edge corresponding to each layer of the core board.
The invention also provides a PCB, which comprises a plurality of layers of core boards and a layer deviation degree control quality detection mechanism arranged on each layer of core board, wherein the layer deviation degree control quality detection mechanism is specifically any one of the layer deviation degree control quality detection mechanisms.
The invention provides a layer deviation control quality detection mechanism which mainly comprises a detection package, a grounding hole, an electrical testing hole and an annular vacancy area. The detection packages are disposed at the same positions on the surfaces of the core boards, that is, the positions of the detection packages on the core boards correspond to each other in the stacking direction (or height direction). The detection package mainly includes a ground via and an electrical measurement via. The grounding hole is arranged on the surface of the core plate, the potential is kept grounded, and the grounding hole is mainly used for being connected with any electrode (such as a negative electrode) of PCB electrical measurement equipment for electrical measurement and inspection. The electric measuring hole is arranged on the surface of the core plate and is separated from the grounding hole by a certain distance, and the electric measuring hole is mainly used for being connected with the other electrode (such as a positive electrode) of the PCB electric measuring equipment. Importantly, the apertures of the grounding hole and the electrical measurement hole are equivalent to the aperture of the minimum via hole formed in the PCB, a conductor layer is laid on the surface of each chip, the conductor layer is located in the region of the outer edge of the electrical measurement hole, an annular vacancy area is formed by extending outwards from the hole wall of the electrical measurement hole, and the radial length of the annular vacancy area is the maximum allowable layer deviation.
Therefore, when the PCB layer skewness is inspected by the PCB electrical measurement equipment, firstly, the anode electrode of the PCB is respectively inserted into the grounding hole and the electrical measurement hole, under the condition that the layer skewness is normal, the offsets of all layers of core plates are not large and are all within the allowable maximum layer skewness, the core plates cannot be contacted with the electrodes of the PCB electrical measurement equipment in the grounding hole and the electrical measurement hole, and further the short circuit condition of the anode and the cathode in short circuit cannot occur; on the contrary, if the short circuit condition occurs in the PCB electrical measurement equipment, it indicates that the offset of at least one layer of core board is too large, so that the conductor layer is offset to exceed the radial length of the annular vacancy area, and contacts with the electrodes in the grounding hole and the electrical measurement hole, which means that the PCB layer offset control quality is not qualified.
Compared with the prior art, the aperture of the grounding hole is equal to that of the minimum via hole, if the electrical measurement inspection of the minimum via hole is qualified, the electrical measurement inspection of all the rest via holes is obviously qualified, so that the detection personnel only need to perform the electrical measurement inspection on the grounding hole and the electrical measurement hole in the detection package, namely the electrical measurement inspection of all the via holes on the PCB can be finished, the detection operation efficiency of the deflection management and control quality of the PCB layer can be improved, the detection result precision and reliability are improved, and the design requirement of the high-density board is met.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic overall structure diagram of an embodiment of the present invention.
Fig. 2 is a schematic diagram of a specific structure of the inspection package.
Wherein, in fig. 1-2:
a core board-1, a detection package-2, a first bonding pad-3 and a second bonding pad-4;
the device comprises a conductor layer-11, an annular vacancy area-12, a grounding hole-21 and an electrical testing hole-22.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic overall structure diagram of an embodiment of the present invention.
In a specific embodiment provided by the present invention, the layer deviation control quality detection mechanism mainly includes a detection package 2, a ground hole 21, an electrical measurement hole 22, and an annular void region 12.
The detection packages 2 are disposed at the same position on the surface of each core board 1, that is, the positions of the detection packages 2 on each core board 1 correspond to each other in the stacking direction (or height direction).
As shown in fig. 2, fig. 2 is a schematic diagram of a specific structure of the detection package 2.
The detection package 2 mainly comprises a ground via 21 and an electrical measurement via 22. The grounding hole 21 is opened on the surface of the core plate 1, the potential is kept grounded, and the grounding hole is mainly used for connecting with any electrode (such as a negative electrode) of PCB electrical measurement equipment for electrical measurement and inspection. The electrical measuring hole 22 is opened on the surface of the core plate 1, and is spaced from the grounding hole 21 by a certain distance, and is mainly used for connecting with another electrode (such as a positive electrode) of the PCB electrical measuring equipment. Of course, the grounding hole 21 can be connected to the positive pole of the PCB electrical measuring device, while the electrical measuring hole 22 is connected to the negative pole of the PCB electrical measuring device.
Importantly, the aperture of the grounding hole 21 and the aperture of the electrical measuring hole 22 are both equal to the aperture of the smallest via hole formed in the PCB, a conductive layer 11 (such as copper sheet) is laid on the surface of each chip, and an annular vacancy area 12 is formed in the conductive layer 11 in the area located at the outer edge of the electrical measuring hole 22 and extends outwards from the hole wall of the electrical measuring hole 22, and the radial length of the annular vacancy area 12 is the maximum allowable layer deviation.
Therefore, when the PCB layer skewness is inspected by the PCB electrical measurement equipment, firstly, the anode electrode of the PCB is respectively inserted into the grounding hole 21 and the electrical measurement hole 22, under the condition that the layer skewness is normal, the offset of each layer of core plate 1 is not large and is within the allowable maximum layer skewness, the core plates cannot contact with the electrodes of the PCB electrical measurement equipment in the grounding hole 21 and the electrical measurement hole 22, and the short circuit condition of anode and cathode short circuit cannot occur; on the contrary, if the short circuit condition occurs in the PCB electrical measurement device, it indicates that the offset of at least one layer of the core board 1 is too large, so that the conductor layer 11 is offset to exceed the radial length of the annular vacancy area 12 and contacts with the electrodes in the grounding hole 21 and the electrical measurement hole 22, and the PCB layer offset control quality is not qualified in this case.
Compared with the prior art, the aperture of the grounding hole 21 is equal to that of the electrical measuring hole 22, if the electrical measuring inspection of the minimum via hole is qualified, the electrical measuring inspection of all the rest via holes is obviously qualified, so that the detection personnel only need to perform the electrical measuring inspection on the grounding hole 21 and the electrical measuring hole 22 in the detection package 2, namely the electrical measuring inspection of all the via holes on the PCB can be finished, the detection operation efficiency of the PCB layer skewness control quality can be improved, the detection result precision and reliability are improved, and the design requirement of a high-density board is met.
It should be noted that the apertures of the grounding hole 21 and the electrical measuring hole 22 are both equivalent to the minimum via hole aperture provided on the PCB, and considering that there is an unavoidable error in the PCB production and manufacturing process, the apertures of the grounding hole 21 and the electrical measuring hole 22 can be calculated equivalent to the minimum via hole aperture only if the difference between the apertures is within 5%. Generally, considering the aperture of the mainstream via in the industry at present, the apertures of the ground hole 21 and the electrical measurement hole 22 may be specifically 6 to 12 mils, such as 6 mils, 8 mils, 10 mils, 12 mils, and the like.
Similarly, considering the requirement of D2M on the PCB manufacturing process, that is, the minimum distance from the hole wall to the copper sheet is generally 9mil, therefore, when the PCB is designed, the distance from the hole wall of the reference layer to the copper sheet is 9mil, but because of SI (Signal Integrity) performance requirement, the distance from the hole wall to the copper sheet cannot be 9mil, and because the edge of the trace to the reference layer cannot be too close, the edge of the trace to the reference layer can be controlled at about 5 mil. Thus, in the present embodiment, the radial length of the annular void region 12 is generally 5-6 mil.
In addition, in consideration of different requirements of different PCB products on the accuracy of the layer skewness, in this embodiment, a plurality of electrical measurement holes 22 are simultaneously formed on the surface of each layer of core board 1, and a plurality of annular void areas 12 are simultaneously and correspondingly formed on the conductor layer 11, and the radial lengths of the annular void areas 12 are different from each other. For example, 2 electrical measurement holes 22 may be simultaneously formed in the surface of each core board 1, and the annular void areas 12 corresponding to each other are respectively formed outside the 2 electrical measurement holes 22, and a radial length (L1) of one of the annular void areas 12 is 5 mils, and a radial length (L2) of the other annular void area 12 is 6 mils. So set up, different annular vacancy district 12 is corresponding to different layer skewness precision management and control respectively promptly, when D2M's requirement is less than 9mil, layer skewness precision requirement is higher, can launch the electric logging hole 22 that the less annular vacancy district 12 of radial length corresponds at this moment and carry out the electric logging, otherwise, when D2M's requirement is greater than 9mil, layer skewness precision requirement is slightly low, can launch the electric logging hole 22 that the great annular vacancy district 12 of radial length corresponds at this moment and carry out the electric logging.
Of course, if there are other layer skewness accuracy requirements, more electrical measurement holes 22 can be continuously formed in each layer of the core board 1, and more annular void areas 12 with different radial lengths are correspondingly formed in each layer of the conductor layer 11.
In order to facilitate the arrangement of the grounding holes 21 and the electrical testing holes 22 on each layer of the core board 1, in this embodiment, the grounding holes 21 and the electrical testing holes 22 may be uniformly distributed on the surface of each layer of the core board 1 in a straight line. For example, the ground hole 21 may be located on the left side of the area where the detection package 2 is located, one of the electrical holes 22 may be located on the right side of the area where the detection package 2 is located, and the other electrical hole 22 may be located in the middle of the area where the detection package 2 is located, and the centers of the three are collinear. Meanwhile, the distance between the centers of two adjacent electricity measuring holes 22 and the distance between the centers of the ground hole 21 and the adjacent electricity measuring hole 22 are generally 40-50 mil.
In addition, considering that the shape and size of the ground hole 21 are the same as those of each electrical testing hole 22, in order to facilitate quick recognition by the inspector, the first pad 3 is disposed on the conductor layer 11 in the region outside the ground hole 21, and the second pad 4 is disposed on the conductor layer 11 in the region outside the annular void region 12 corresponding to each electrical testing hole 22, and the first pad 3 and the second pad 4 are different in shape. For example, the first pad 3 may have a rectangular shape, and the second pad 4 may have a circular shape. Meanwhile, the radial length of the corresponding annular vacancy area 12, namely the allowable maximum layer deviation, can be marked on different second bonding pads 4 by silk screen printing.
Moreover, considering that the size of a part of the PCB is large, the layer skewness of the via holes at different positions may not be uniform, and for this reason, 4 to 8 detection packages 2 are simultaneously disposed on the surface of each layer of the core board 1 in the present embodiment. Meanwhile, in order to reduce the occupation of the space on the surface of the PCB, in this embodiment, each detection package 2 is respectively distributed in each corner area of the surface of each layer of the core board 1.
In addition, if the space in the PCB is insufficient, the detection packages 2 may be simultaneously distributed on the surface of the auxiliary edge corresponding to each layer of the core board 1, for example, 4 detection packages 2 may be disposed on the core board 1, and 4 detection packages 2 may be disposed on each auxiliary edge.
The present embodiment further provides a PCB, which mainly includes a plurality of layers of core boards 1 and a layer deviation control quality detection mechanism disposed on each layer of core board 1, wherein the specific content of the layer deviation control quality detection mechanism is the same as the related content, and is not described herein again.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A layer deviation control quality detection mechanism is characterized by comprising detection packages (2) arranged at the same position on the surface of each layer of core plate (1), the detection package (2) comprises a grounding hole (21) which is arranged on the surface of the core plate (1) and is used for being connected with any electrode of PCB electrical measurement equipment, and an electrical measurement hole (22) which is arranged on the surface of the core plate (1), is separated from the grounding hole (21) by a preset distance and is used for being connected with the other electrode of the PCB electrical measurement equipment, the aperture of the grounding hole (21) and the aperture of the electrical testing hole (22) are both equivalent to the aperture of the minimum via hole formed on the PCB, and the conductor layer (11) laid on the surface of each layer of the core board (1) extends outwards from the hole wall of the electric measuring hole (22) to form an annular vacancy area (12), and the radial length of the annular vacancy area (12) is the allowable maximum layer deviation.
2. The mechanism for detecting layer deviation degree control quality according to claim 1, wherein the electrical measurement hole (22) is provided in plural on the surface of each layer of the core board (1), the annular void region (12) is provided in plural on the conductor layer (11), and the radial length of each annular void region (12) is different.
3. The mechanism for detecting layer deviation degree control quality according to claim 2, wherein the grounding holes (21) and the electrical measuring holes (22) are uniformly distributed in a straight line on the surface of each layer of the core plate (1).
4. The mechanism for detecting layer deviation degree control quality according to claim 3, wherein the distance between the centers of the grounding hole (21) and the adjacent electrical measuring holes (22) and the distance between the centers of the adjacent electrical measuring holes (22) are both 40-50 mils.
5. The mechanism for detecting the layer deviation degree control quality is characterized in that the radial length of each annular vacancy area (12) is 5-6 mil.
6. The mechanism for detecting layer deviation degree control quality according to claim 1, wherein a first pad (3) is disposed on the conductor layer (11) outside the grounding hole (21), a second pad (4) is disposed on the conductor layer (11) outside the annular vacancy area (12), and shapes of the first pad (3) and the second pad (4) are different.
7. The mechanism for detecting layer thickness deviation control quality according to claim 6, wherein the first bonding pad (3) is rectangular and the second bonding pad (4) is circular.
8. The mechanism for detecting the layer deviation degree control quality according to any one of claims 1 to 7, wherein 4 to 8 detection packages (2) are arranged on the surface of each layer of the core board (1), and each detection package (2) is distributed in each corner area of each layer of the core board (1).
9. The mechanism for detecting layer thickness deviation control quality according to claim 8, wherein each detection package (2) is simultaneously distributed on the surface of each layer of the core board (1) and the surface of the corresponding auxiliary edge of each layer of the core board (1).
10. A PCB comprising a plurality of layers of core boards (1) and a layer deviation control quality detection mechanism disposed on each layer of core boards (1), wherein the layer deviation control quality detection mechanism is specifically the layer deviation control quality detection mechanism of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011305730.4A CN112738976A (en) | 2020-11-19 | 2020-11-19 | PCB and layer skewness management and control quality detection mechanism thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011305730.4A CN112738976A (en) | 2020-11-19 | 2020-11-19 | PCB and layer skewness management and control quality detection mechanism thereof |
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| Publication Number | Publication Date |
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| CN112738976A true CN112738976A (en) | 2021-04-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202011305730.4A Withdrawn CN112738976A (en) | 2020-11-19 | 2020-11-19 | PCB and layer skewness management and control quality detection mechanism thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114585166A (en) * | 2022-04-29 | 2022-06-03 | 苏州东山精密制造股份有限公司 | Layer deviation detection method for flexible antenna multilayer board |
| CN117320329A (en) * | 2023-09-26 | 2023-12-29 | 江门全合精密电子有限公司 | Method for testing inner layer deviation of multilayer PCB |
| CN117369017A (en) * | 2023-12-06 | 2024-01-09 | 苏州元脑智能科技有限公司 | Integrity detection method and device for copper laying of through holes in PCB and electronic equipment |
-
2020
- 2020-11-19 CN CN202011305730.4A patent/CN112738976A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114585166A (en) * | 2022-04-29 | 2022-06-03 | 苏州东山精密制造股份有限公司 | Layer deviation detection method for flexible antenna multilayer board |
| CN117320329A (en) * | 2023-09-26 | 2023-12-29 | 江门全合精密电子有限公司 | Method for testing inner layer deviation of multilayer PCB |
| CN117369017A (en) * | 2023-12-06 | 2024-01-09 | 苏州元脑智能科技有限公司 | Integrity detection method and device for copper laying of through holes in PCB and electronic equipment |
| CN117369017B (en) * | 2023-12-06 | 2024-02-23 | 苏州元脑智能科技有限公司 | Integrity detection method and device for copper laying of through holes in PCB and electronic equipment |
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Application publication date: 20210430 |