CN214314542U - Power-off protection circuit capable of preventing failure - Google Patents

Abstract

The utility model discloses a power-off protection circuit for failure prevention, which comprises a PLP circuit, a diode and an NMOS transistor, wherein the PLP circuit comprises an input end, an output end and an enabling end; the anode end and the input end of the diode are electrically connected, and the cathode end of the diode is respectively electrically connected with the enable end, the output end and the drain end of the NMOS transistor; the source of the NMOS transistor is grounded and the gate is used for being electrically connected with the SSD master. The utility model discloses an increase diode and NMOS transistor on the basis of original PLP circuit, come the effect that realizes preventing that electric current recharge, data from losing and the consumption is too high simultaneously.

Description

Power-off protection circuit capable of preventing failure

Technical Field

The utility model relates to a USB interface technical field, in particular to prevent power-off protection circuit of failure.

Background

Some SSD (Solid State Disk) with PLP (power loss protection) function appear in the market, after abnormal power failure occurs at the host (main control) end, the SSD needs to store data completely within a certain time, but after the host end is powered off, the output end current of the power failure protection circuit can be back-filled to the input end, thereby causing the loss of the electric quantity stored by the PLP circuit, causing the SSD to have insufficient power supply time to complete data transmission for the SSD main control, and further losing the data. Meanwhile, when the electronic equipment provided with the SSD enters a low power consumption mode, the PLP circuit cannot be disconnected, so that the power consumption is always larger, and the effect of reducing the power consumption cannot be achieved.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem that will solve is: the power-off protection circuit capable of preventing failure is provided, and the effects of preventing current recharge, data loss and overhigh power consumption can be achieved at the same time.

In order to solve the technical problem, the utility model discloses a technical scheme be:

a power-off protection circuit for preventing failure comprises a PLP circuit, a diode and an NMOS transistor, wherein the PLP circuit comprises an input end, an output end and an enabling end;

the anode end of the diode is electrically connected with the input end, and the cathode end of the diode is respectively electrically connected with the enable end, the output end and the drain end of the NMOS transistor;

the source electrode of the NMOS transistor is grounded, and the grid electrode of the NMOS transistor is used for being electrically connected with an SSD master control.

The diode further comprises a first resistor, a cathode end of the diode is electrically connected with the output end and a first end of the first resistor respectively, and a second end of the first resistor is electrically connected with the enable end and a drain end of the NMOS transistor respectively.

Further, the resistance value of the first resistor is [10K Ω,200K Ω ].

Further, the diode is a schottky diode.

Further, the circuit also comprises a first capacitor and a second capacitor;

and the anode end of the diode is also electrically connected with the first end of the first capacitor and the first end of the second capacitor respectively, and the second end of the first capacitor and the second end of the second capacitor are both grounded.

Further, the device also comprises a second resistor, wherein a first end of the second resistor is electrically connected with the grid electrode of the NMOS transistor, and a second end of the second resistor is used for being electrically connected with the SSD master control.

The beneficial effects of the utility model reside in that: when input is input at an input end, a diode is conducted, an enable end is pulled high, meanwhile, an SSD master control pulls a grid electrode of an NMOS transistor down, the NMOS transistor cannot be conducted, the high level state of the enable end cannot be influenced, and a PLP circuit is enabled to work normally; when the voltage input end is disconnected, the diode cannot be conducted, the enable end can still be pulled high at the moment to ensure that the PLP circuit works normally, and at the moment, the output end cannot be conducted due to reverse cut-off of the diode, so that current cannot be recharged to the host end, and the circuit is ensured to have enough electric quantity to supply the SSD for main control and data storage. When the host end enters the sleep mode, the whole SSD also enters the sleep mode, at the moment, the SSD master control pulls up the grid electrode of the NMOS transistor, so that the NMOS transistor is conducted, the enable end is at a low level to disconnect the PLP circuit, and the power consumption of the PLP circuit is reduced to the minimum. Thereby simultaneously realizing the effects of preventing current recharge, data loss and overhigh power consumption.

Drawings

Fig. 1 is a schematic circuit diagram of a fail-safe circuit breaker according to an embodiment of the present invention;

description of reference numerals:

C1-C4 and a capacitor, wherein C1 is the first capacitor; c2, a second capacitor;

d1, a diode;

GPIO, general purpose input/output end;

l1, inductance;

q1, NMOS transistor; G. a gate electrode; D. a drain electrode; s, a source electrode;

R1-R6 and a resistor, wherein R1 is the first resistor; r2, a second resistor;

TC1 and TCn, and an energy storage capacitor;

vin, an input terminal; vout, output terminal; EN, enabling end; SST, soft start end; FBS, first voltage feedback end; v _ STRG and a capacitance control end; FBC, second voltage feedback end; LX, voltage output terminal.

Detailed Description

In order to explain the technical content, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.

Referring to fig. 1, an embodiment of the present invention provides a failure-prevention power-off protection circuit, including a PLP circuit, a diode D1, and an NMOS transistor Q1, where the PLP circuit includes an input terminal Vin, an output terminal Vout, and an enable terminal EN;

an anode terminal of the diode D1 is electrically connected to the input terminal Vin, and a cathode terminal of the diode D1 is electrically connected to the enable terminal EN, the output terminal Vout, and the drain terminal D of the NMOS transistor Q1, respectively;

the source S of the NMOS transistor Q1 is grounded and the gate G is used to electrically connect with the SSD master.

From the above description, the beneficial effects of the present invention are: when the input end Vin has input, the diode D1 is conducted, the enable end EN is pulled high, meanwhile, the SSD master control pulls the gate G of the NMOS transistor Q1 low, the NMOS transistor Q1 is not conducted, the high level state of the enable end EN is not affected, and the PLP circuit is enabled to work normally; when the voltage input terminal Vin is disconnected, the diode D1 cannot be turned on, the enable terminal EN can still be pulled high at this time to ensure that the PLP circuit works normally, and at this time, the output terminal Vout cannot be turned on because the diode D1 is turned off in the reverse direction, so that no current is fed back to the host terminal, and the circuit is ensured to have enough electric quantity to supply the SSD main control to store data. When the host end enters the sleep mode, the whole SSD also enters the sleep mode, at the moment, the SSD master control pulls up the grid G of the NMOS transistor Q1, so that the NMOS transistor Q1 is conducted, the enable end EN is at a low level to disconnect the PLP circuit, and the power consumption of the PLP circuit is reduced to the minimum. Thereby simultaneously realizing the effects of preventing current recharge, data loss and overhigh power consumption.

Further, the transistor further comprises a first resistor R1, a cathode terminal of the diode D1 is electrically connected to the output terminal Vout and a first terminal of the first resistor R1, respectively, and a second terminal of the first resistor R1 is electrically connected to the enable terminal EN and a drain terminal D of the NMOS transistor Q1, respectively.

Further, the resistance value of the first resistor R1 is [10K Ω,200K Ω ].

As can be seen from the above description, the first resistor R1 is provided and has a limited resistance range to provide current limiting.

Further, the diode D1 is a schottky diode.

Further, a first capacitor C1 and a second capacitor C2 are also included;

the anode terminal of the diode D1 is also electrically connected to the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2, respectively, and the second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 are both grounded.

As can be seen from the above description, the first capacitor C1 and the second capacitor C2 are provided for filtering.

Further, the device also comprises a second resistor R2, wherein a first end of the second resistor R2 is electrically connected with the gate G of the NMOS transistor Q1, and a second end of the second resistor R2 is electrically connected with an SSD master.

As is apparent from the above description, the second resistor R2 is provided as a pull-up resistor to pull up or pull down the gate G of the NMOS transistor Q1.

The failure-prevention power-off protection circuit is mainly applied to any application scene of electronic equipment provided with an SSD (solid state drive) comprising a PLP (programmable logic device) circuit, and is described in combination with a specific application scene as follows:

according to the above, and with reference to fig. 1, the first embodiment of the present invention is:

in the present embodiment, as shown in fig. 1, a fail-safe circuit includes a PLP circuit including an input terminal Vin, an output terminal Vout, and an enable terminal EN, a diode D1, and an NMOS transistor Q1.

As shown in fig. 1, an anode terminal of the diode D1 is electrically connected to the input terminal Vin, and a cathode terminal of the diode D1 is electrically connected to the enable terminal EN, the output terminal Vout, and the drain terminal D of the NMOS transistor Q1, respectively; the source S of the NMOS transistor Q1 is grounded and the gate G is used to be electrically connected to the SSD master, i.e. the general purpose input/output terminal GPIO in fig. 1 is used to be electrically connected to the SSD master. Thus, the effects of preventing current back-flow, data loss, and excessive power consumption are simultaneously achieved by the turning on and off of the diode D1 and the turning on and off of the NMOS transistor Q1.

In the present embodiment, the diode D1 is a schottky diode.

In this embodiment, the capacitor further includes a first resistor R1, a first capacitor C1, a second capacitor C2, and a second resistor R2. The cathode terminal of the diode D1 is electrically connected to the output terminal Vout and the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is electrically connected to the enable terminal EN and the drain terminal D of the NMOS transistor Q1. The anode terminal of the diode D1 is electrically connected to the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2, respectively, and the second terminal of the first capacitor C1 and the second terminal of the second capacitor C2 are both grounded. The first end of the second resistor R2 is electrically connected to the gate G of the NMOS transistor Q1, and the second end is electrically connected to the SSD master.

In this embodiment, the resistance of the first resistor R1 is 100K Ω, the resistance of the second resistor R2 is adjustable resistor, the resistance range of the adjustable resistor is [0, 10K Ω ], and in other equivalent embodiments, the resistance of the first resistor R1 is [10K Ω,200K Ω ]. The capacitance C1 used was 22uF/10V, and the capacitance C2 used was 0.1 uF/10V.

As shown in fig. 1, for the present embodiment, the PLP circuit further includes a soft start terminal SST, a first voltage feedback terminal FBS, a capacitor control terminal V _ STRG, a second voltage feedback terminal FBC and a voltage output terminal LX. Wherein, the soft start terminal SST is connected with a capacitor C4 for controlling the start time of the PLP circuit, wherein the capacitor C4 can be selected as 22 nF/10V. The first voltage feedback terminal FBS is connected to the first terminals of the resistors R5 and R6, the second terminal of the resistor R5 is grounded, the second terminal of the resistor R6 is connected to the output terminal Vout, that is, the first voltage feedback terminal FBS receives the divided voltage of the output terminal Vout, assuming that the resistance of the resistor R6 is 200k Ω, the resistance of the resistor R5 is 33k Ω, and when the voltage value of the output terminal Vout is 4.2V, the voltage value detected by the first voltage feedback terminal FBS is 0.6V. The capacitor control end V _ STRG is electrically connected with the energy storage capacitor array, the energy storage capacitor array is composed of energy storage capacitors TC 1-TCn, meanwhile, the voltage output end LX is electrically connected with the first end of the inductor L1, and the second end of the inductor L1 is electrically connected with the output end Vout, so that when the voltage value detected by the first voltage feedback end FBS is smaller than a specified voltage value, the capacitor control end V _ STRG is indicated to discharge and output current through the voltage output end LX. The second voltage feedback terminal FBC is connected to the first terminals of the resistors R3 and R4, the second terminal of the resistor R3 is grounded, and the second terminal of the resistor R4 is connected to the capacitor control terminal V _ STRG, that is, the second voltage feedback terminal FBC is configured to instruct the capacitor control terminal V _ STRG to stop outputting power to the storage capacitor array when the voltage value of the power stored in the storage capacitor array reaches a specified voltage value.

To sum up, the utility model provides a power-off protection circuit for failure prevention, when there is input at the input end, the diode is conducted, the enable end is pulled high, and simultaneously the SSD master control pulls the gate of the NMOS transistor low, the NMOS transistor is not conducted, the high level state of the enable end is not affected, so that the PLP circuit works normally; when the voltage input end is disconnected, the diode cannot be conducted, the enable end can still be pulled high at the moment to ensure that the PLP circuit works normally, and at the moment, the output end cannot be conducted due to reverse cut-off of the diode, so that current cannot be recharged to the host end, and the circuit is ensured to have enough electric quantity to supply the SSD for main control and data storage. When the host end enters the sleep mode, the whole SSD also enters the sleep mode, at the moment, the SSD master control pulls up the grid electrode of the NMOS transistor, so that the NMOS transistor is conducted, the enable end is at a low level to disconnect the PLP circuit, and the power consumption of the PLP circuit is reduced to the minimum. Thereby simultaneously realizing the effects of preventing current recharge, data loss and overhigh power consumption.

The above mentioned is only the embodiment of the present invention, and not the limitation of the patent scope of the present invention, all the equivalent transformations made by the contents of the specification and the drawings, or the direct or indirect application in the related technical field, are included in the patent protection scope of the present invention.

Claims (6)

1. The power failure protection circuit for preventing failure is characterized by comprising a PLP circuit, a diode and an NMOS transistor, wherein the PLP circuit comprises an input end, an output end and an enabling end;

the anode end of the diode is electrically connected with the input end, and the cathode end of the diode is respectively electrically connected with the enable end, the output end and the drain end of the NMOS transistor;

the source electrode of the NMOS transistor is grounded, and the grid electrode of the NMOS transistor is used for being electrically connected with an SSD master control.

2. The fail-safe circuit breaker according to claim 1, further comprising a first resistor, wherein the cathode terminal of the diode is electrically connected to the output terminal and the first terminal of the first resistor, respectively, and the second terminal of the first resistor is electrically connected to the enable terminal and the drain terminal of the NMOS transistor, respectively.

3. The fail-safe circuit breaker of claim 2 wherein the first resistor has a resistance of [10K Ω,200K Ω ].

4. A fail-safe circuit-breaking circuit as claimed in any one of claims 1 to 3, wherein the diode is a schottky diode.

5. The fail-safe circuit breaker circuit according to any one of claims 1 to 3, further comprising a first capacitor and a second capacitor;

and the anode end of the diode is also electrically connected with the first end of the first capacitor and the first end of the second capacitor respectively, and the second end of the first capacitor and the second end of the second capacitor are both grounded.

6. The fail-safe power-off protection circuit of claim 5, further comprising a second resistor having a first end electrically connected to the gate of the NMOS transistor and a second end for electrical connection to an SSD master.

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