CN214281258U - Direct-current voltage DC12V inverter circuit based on high-power NMOS (N-channel metal oxide semiconductor) tube - Google Patents
Direct-current voltage DC12V inverter circuit based on high-power NMOS (N-channel metal oxide semiconductor) tube Download PDFInfo
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- CN214281258U CN214281258U CN202120512736.2U CN202120512736U CN214281258U CN 214281258 U CN214281258 U CN 214281258U CN 202120512736 U CN202120512736 U CN 202120512736U CN 214281258 U CN214281258 U CN 214281258U
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Abstract
The utility model provides a direct current voltage DC12V inverter circuit based on high-power NMOS pipe, when the input inserts 12V direct current voltage, the grid of NMOS pipe I and NMOS pipe II all obtains higher voltage, when NMOS pipe I switches on, the grid voltage of NMOS pipe II is drawn low, therefore NMOS pipe II ends, with the increase of the electric current that switches on of NMOS pipe I, the transformer has the effect of hindering the electric current, make I grid voltage of NMOS pipe slowly drawn low, when I grid voltage of NMOS pipe is less than source voltage, NMOS pipe II switches on. When the NMOS tube II is switched on, the grid voltage of the NMOS tube I is pulled down, so that the NMOS tube I is switched off, the transformer has a blocking effect on the current along with the increase of the switching-on current of the NMOS tube II, the grid voltage of the NMOS tube II is slowly pulled down, and when the grid voltage of the NMOS tube II is smaller than the source voltage, the NMOS tube I is switched on. Therefore, the two NMOS tubes are alternately switched on and off, so that a current signal which changes constantly is generated, and the current signal is boosted into high-voltage alternating-current voltage through the transformer. The whole circuit is safe and reliable.
Description
Technical Field
The utility model relates to an inverter technical field, concretely relates to direct current voltage DC12V inverter circuit based on high-power NMOS pipe.
Background
At present, a lot of devices for inverting the direct-current voltage DC12V into the alternating-current voltage exist, but most of the devices are expensive and have overlarge volume, some inverting devices are not suitable for families, and some inverters have insufficient output power, so that the load cannot work normally. Therefore, a circuit device which is low in price and large in output power and can invert the direct-current voltage DC12V into alternating-current voltage is needed, and the circuit device not only can be suitable for common families to use, but also can output large power. If a power failure occurs in a household, the direct current DC12V storage battery can be used in the household.
Disclosure of Invention
The utility model discloses a overcome not enough of above technique, provide a direct current voltage DC12V inverter circuit based on high-power NMOS pipe.
The utility model overcomes the technical scheme that its technical problem adopted is:
a high-power NMOS transistor-based DC12V inverter circuit comprises:
the source electrode of the NMOS tube I is grounded, and the drain electrode of the NMOS tube I is connected to one contact of the secondary side of the transformer;
the source electrode of the NMOS tube II is grounded, the drain electrode of the NMOS tube II is connected to the other contact of the secondary side of the transformer and the grid electrode and the source electrode of the NMOS tube I respectively, and the source electrode of the NMOS tube II is connected to the grid electrode of the NMOS tube II and the drain electrode of the NMOS tube I respectively;
the first connecting end of the three-terminal ceramic gas discharge tube is connected to the anode of the 12V storage battery, the third connecting end of the three-terminal ceramic gas discharge tube is connected to the cathode of the 12V storage battery through a piezoresistor I, and the second connecting end of the three-terminal ceramic gas discharge tube is grounded through a piezoresistor II;
one end of a TVS transient suppression diode I and one end of a TVS transient suppression diode II are connected in series with each other, then are connected with the anode of a 12V storage battery through a decoupling inductor I, the other end of the TVS transient suppression diode I and the other end of the TVS transient suppression diode II are connected with the cathode of the 12V storage battery through a decoupling inductor II, a capacitor I and a capacitor II are connected in series with each other, then are connected with the TVS transient suppression diode I and the TVS transient suppression diode II in parallel, one end of a TVS transient suppression diode III is respectively connected with the TVS transient suppression diode I and the TVS transient suppression diode II, the other end of the TVS transient suppression diode I and the other end of the TVS transient suppression diode II are respectively connected with the capacitor I, the capacitor II and the ground, one end of the capacitor I and one end of the capacitor II which are connected in series with each other are grounded, and the other end of the secondary of the transformer is connected with the secondary of the transformer;
the first connecting end of the two-end ceramic gas discharge tube is grounded, the second connecting end of the two-end ceramic gas discharge tube is respectively connected to one end of a piezoresistor IV and one end of a piezoresistor V, the other end of the piezoresistor IV is respectively connected to one primary contact of the transformer and one end of the piezoresistor III, and the other end of the piezoresistor V is respectively connected to the other primary contact of the transformer and the other end of the piezoresistor III.
Furthermore, the grid electrode of the NMOS tube II is grounded through the resistor II and is connected to the drain electrode of the NMOS tube I through the resistor IV.
Furthermore, the drain electrode of the NMOS tube II is connected to one end of a resistor III, and the other end of the resistor III is connected to the grid electrode of the NMOS tube I and the source electrode of the NMOS tube I through the resistor I.
In order to play a role of protecting a circuit, a fuse I is arranged between the primary side of the transformer and the piezoresistor IV, and a fuse II is arranged between the primary side of the transformer and the piezoresistor V.
The utility model has the advantages that: when 12V direct current voltage is connected to the input end, the grid electrodes of the NMOS tube I and the NMOS tube II are both high in voltage, when the NMOS tube I is conducted, the grid electrode voltage of the NMOS tube II is pulled down, therefore, the NMOS tube II is cut off, the transformer has a blocking effect on current along with the increase of the conducting current of the NMOS tube I, the grid electrode voltage of the NMOS tube I is slowly pulled down, and when the grid electrode voltage of the NMOS tube I is smaller than the source electrode voltage, the NMOS tube II is conducted. When the NMOS tube II is switched on, the grid voltage of the NMOS tube I is pulled down, so that the NMOS tube I is switched off, the transformer has a blocking effect on the current along with the increase of the switching-on current of the NMOS tube II, the grid voltage of the NMOS tube II is slowly pulled down, and when the grid voltage of the NMOS tube II is smaller than the source voltage, the NMOS tube I is switched on. Therefore, the two NMOS tubes are alternately switched on and off, so that a current signal which changes constantly is generated, and the current signal is boosted into high-voltage alternating-current voltage through the transformer. The whole circuit is safe and reliable.
Drawings
FIG. 1 is a circuit diagram of the present invention;
in the figure, 1, an NMOS tube I2, an NMOS tube II 3, a three-terminal ceramic gas discharge tube 4, a piezoresistor I5, a piezoresistor II 6, a decoupling inductor I7, a decoupling inductor II 8, a TVS transient suppression diode I9, a TVS transient suppression diode II 10, a TVS transient suppression diode III 11, a capacitor I12, a capacitor II 13, a resistor I14, a resistor II 15, a resistor III 16, a resistor IV 17, a transformer 18, a fuse I19, a piezoresistor III 20, a fuse II 21, a piezoresistor IV 22, a piezoresistor V23 and two-terminal ceramic gas discharge tubes.
Detailed Description
The present invention will be further explained with reference to fig. 1.
A high-power NMOS transistor-based DC12V inverter circuit comprises: the source electrode of the NMOS tube I1 is grounded, and the drain electrode of the NMOS tube I1 is connected to a contact of the secondary side of the transformer 17; the source electrode of the NMOS tube II 2 is grounded, the drain electrode of the NMOS tube II 2 is connected to the other secondary contact of the transformer 17 and the grid electrode and the source electrode of the NMOS tube I1 respectively, and the source electrode of the NMOS tube II 2 is connected to the grid electrode of the NMOS tube II 2 and the drain electrode of the NMOS tube I1 respectively; the first connecting end of the three-terminal ceramic gas discharge tube 3 is connected to the anode of the 12V storage battery, the third connecting end of the three-terminal ceramic gas discharge tube is connected to the cathode of the 12V storage battery through a piezoresistor I4, and the second connecting end of the three-terminal ceramic gas discharge tube is grounded through a piezoresistor II 5; one end of a TVS transient suppression diode I8 and one end of a TVS transient suppression diode II 9 are connected in series with each other, then, one end of the TVS transient suppression diode I8 is connected to the positive electrode of a 12V storage battery through a decoupling inductor I6, the other end of the TVS transient suppression diode I8 is connected to the negative electrode of the 12V storage battery through a decoupling inductor II 7, a capacitor I11 and a capacitor II 12 are connected in series with each other, then, the TVS transient suppression diode I8 and the TVS transient suppression diode II 9 are connected in parallel, one end of a TVS transient suppression diode III 10 is respectively connected with the TVS transient suppression diode I8 and the TVS transient suppression diode II 9, the other end of the TVS transient suppression diode III 10 is respectively connected with the capacitor I11, the capacitor II 12 and the ground, one end of the capacitor I11 and one end of the capacitor II 12 which are connected in series with each other are grounded, and the other end of the secondary of the transformer 17 is connected with the secondary; the first connection end of the two-end ceramic gas discharge tube 23 is grounded, the second connection end of the two-end ceramic gas discharge tube is respectively connected to one end of the piezoresistor IV 21 and one end of the piezoresistor V22, the other end of the piezoresistor IV 21 is respectively connected to one primary contact of the transformer 17 and one end of the piezoresistor III 19, and the other end of the piezoresistor V22 is respectively connected to the other primary contact of the transformer 17 and the other end of the piezoresistor III 19. The NMOS tube has the advantages of high input impedance, good thermal stability, high voltage resistance, improved frequency characteristics, low noise, low power consumption, no secondary breakdown phenomenon and the like. When 12V direct current voltage is connected to the input end, the grids of the NMOS tube I1 and the NMOS tube II 2 both obtain higher voltage, when the NMOS tube I1 is conducted, the grid voltage of the NMOS tube II 2 is pulled down, therefore, the NMOS tube II 2 is cut off, along with the increase of the conducting current of the NMOS tube I1, the transformer 17 has a blocking effect on the current, the grid voltage of the NMOS tube I1 is slowly pulled down, and when the grid voltage of the NMOS tube I1 is smaller than the source voltage, the NMOS tube II 2 is conducted. When the NMOS pipe II 2 is switched on, the grid voltage of the NMOS pipe I1 is pulled down, so that the NMOS pipe I1 is switched off, and along with the increase of the switching-on current of the NMOS pipe II 2, the transformer 17 has a blocking effect on the current, so that the grid voltage of the NMOS pipe II 2 is slowly pulled down, and when the grid voltage of the NMOS pipe II 2 is smaller than the source voltage, the NMOS pipe I1 is switched on. Therefore, the two NMOS transistors are alternately turned on and off to generate a current signal that varies continuously, and the current signal is boosted to a high-voltage ac voltage by the transformer 17. When the inter-electrode electric field strength exceeds the breakdown strength of the gas, the two-terminal ceramic gas discharge tube 23 and the three-terminal ceramic gas discharge tube 3 cause a gap discharge as short-circuit protection devices, thereby limiting the inter-electrode voltage and protecting the entire anti-reverse connection circuit. The decoupling inductor I6 and the decoupling inductor II 7 mainly have the functions of preventing the current flowing through the inductors from jumping and preventing the current from passing quickly. The TVS transient suppression diode I8, the TVS transient suppression diode II 9 and the TVS transient suppression diode III 10 are voltage limiting protection devices, have similar functions to piezoresistors, and also clamp overvoltage to a lower voltage value by utilizing the nonlinear characteristics of the devices to realize the protection of a rear-stage circuit. The piezoresistor I4, the piezoresistor II 5, the piezoresistor IV 21 and the piezoresistor V22 play a role in circuit protection.
Furthermore, the grid electrode of the NMOS tube II 2 is grounded through a resistor II 14 and is connected to the drain electrode of the NMOS tube I1 through a resistor IV 16. Resistor IV 16 may function to limit current.
Furthermore, the drain electrode of the NMOS tube II 2 is connected to one end of a resistor III 15, and the other end of the resistor III 15 is respectively connected to the grid electrode of the NMOS tube I1 and the source electrode of the NMOS tube I1 through a resistor I13. Resistor III 15 plays the role of current limiting.
Preferably, a fuse I18 is arranged between the primary side of the transformer 17 and the piezoresistor IV 21, and a fuse II 20 is arranged between the primary side of the transformer 17 and the piezoresistor V22. The fuse I18 and the fuse II 20 can play a role of protecting a circuit when the current is too large.
Claims (4)
1. A direct-current voltage DC12V inverter circuit based on a high-power NMOS transistor is characterized by comprising:
the source electrode of the NMOS tube I (1) is grounded, and the drain electrode of the NMOS tube I is connected to one contact of the secondary side of the transformer (17);
the source electrode of the NMOS tube II (2) is grounded, the drain electrode of the NMOS tube II is connected to the other contact of the secondary side of the transformer (17) and the grid electrode and the source electrode of the NMOS tube I (1) respectively, and the source electrode of the NMOS tube II (2) is connected to the grid electrode of the NMOS tube II (2) and the drain electrode of the NMOS tube I (1) respectively;
the three-terminal ceramic gas discharge tube (3) is connected with the anode of the 12V storage battery through a first connecting end, connected with the cathode of the 12V storage battery through a piezoresistor I (4) through a third connecting end, and grounded through a piezoresistor II (5) through a second connecting end;
one end of a TVS transient suppression diode I (8) and the other end of the TVS transient suppression diode II (9) are connected in series with each other, then one end of the TVS transient suppression diode I (8) is connected to the anode of a 12V storage battery through a decoupling inductor I (6), the other end of the TVS transient suppression diode I (7) is connected to the cathode of the 12V storage battery through a decoupling inductor II (7), a capacitor I (11) and a capacitor II (12) are connected in series with each other, then the TVS transient suppression diode I (8) and the TVS transient suppression diode II (9) which are connected in series with each other are connected in parallel, one end of a TVS transient suppression diode III (10) is respectively connected with the TVS transient suppression diode I (8) and the TVS transient suppression diode II (9), the other end of the TVS transient suppression diode III is respectively connected with the capacitor I (11), the capacitor II (12) and the ground, one end of the capacitor I (11) and the capacitor II (12) which are connected in series with each other is connected with the secondary of a transformer (17);
and a first connection end of the two-end ceramic gas discharge tube (23) is grounded, a second connection end of the two-end ceramic gas discharge tube is respectively connected to one end of a piezoresistor IV (21) and one end of a piezoresistor V (22), the other end of the piezoresistor IV (21) is respectively connected to one primary contact of the transformer (17) and one end of a piezoresistor III (19), and the other end of the piezoresistor V (22) is respectively connected to the other primary contact of the transformer (17) and the other end of the piezoresistor III (19).
2. The high-power NMOS transistor-based DC12V inverter circuit of claim 1, wherein: the grid electrode of the NMOS tube II (2) is grounded through a resistor II (14) and is connected to the drain electrode of the NMOS tube I (1) through a resistor IV (16).
3. The high-power NMOS transistor-based DC12V inverter circuit of claim 1, wherein: the drain electrode of the NMOS tube II (2) is connected to one end of a resistor III (15), and the other end of the resistor III (15) is respectively connected to the grid electrode of the NMOS tube I (1) and the source electrode of the NMOS tube I (1) through a resistor I (13).
4. The high-power NMOS transistor-based DC12V inverter circuit of claim 1, wherein: a fuse I (18) is arranged between the primary side of the transformer (17) and the piezoresistor IV (21), and a fuse II (20) is arranged between the primary side of the transformer (17) and the piezoresistor V (22).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120512736.2U CN214281258U (en) | 2021-03-11 | 2021-03-11 | Direct-current voltage DC12V inverter circuit based on high-power NMOS (N-channel metal oxide semiconductor) tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120512736.2U CN214281258U (en) | 2021-03-11 | 2021-03-11 | Direct-current voltage DC12V inverter circuit based on high-power NMOS (N-channel metal oxide semiconductor) tube |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214281258U true CN214281258U (en) | 2021-09-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120512736.2U Active CN214281258U (en) | 2021-03-11 | 2021-03-11 | Direct-current voltage DC12V inverter circuit based on high-power NMOS (N-channel metal oxide semiconductor) tube |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214281258U (en) |
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2021
- 2021-03-11 CN CN202120512736.2U patent/CN214281258U/en active Active
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