CN212693960U - Quantum chip testing arrangement - Google Patents
Quantum chip testing arrangement Download PDFInfo
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- CN212693960U CN212693960U CN202021259288.1U CN202021259288U CN212693960U CN 212693960 U CN212693960 U CN 212693960U CN 202021259288 U CN202021259288 U CN 202021259288U CN 212693960 U CN212693960 U CN 212693960U
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Abstract
The utility model belongs to quantum chip test field discloses a quantum chip testing arrangement, and the last distribution of quantum chip has the element that awaits measuring, and testing arrangement includes: the leading-out device is provided with a first grounding area and at least one signal leading-out area, the first grounding area is used for being electrically connected with one grounding end of the element to be tested, and the signal leading-out area is used for being electrically connected with the other end of the element to be tested; and the test motherboard is provided with a second grounding area and signal transmission lines which correspond to the signal leading-out areas one to one, one ends of the signal transmission lines are electrically connected with the corresponding signal leading-out areas, and the other ends of the signal transmission lines are electrically connected with the signal acquisition ends of the measuring device. This kind of quantum chip testing arrangement has effectively avoided connecting many times and has dismantled and cause the inconvenience to the component test that awaits measuring, and draws forth the component signal that awaits measuring and test, compares in measuring device lug connection on the component that awaits measuring, and this scheme measuring device connects more stably, improves the degree of accuracy of test result.
Description
Technical Field
The utility model belongs to the technical field of quantum chip test and specifically relates to a quantum chip testing arrangement is related to.
Background
The quantum chip is a core device for realizing quantum computation, and is provided with various elements, the structure of each element is fragile and is easily influenced by factors such as environment and the like, such as the resistance of a superconducting Josephson junction and the quantum chip, and the performance of the elements directly influences the performance of the superconducting quantum chip, so that the elements need to be tested to determine whether the performance parameters of the elements are qualified.
In the current device for testing the element of the superconducting quantum chip, the element to be tested is directly connected with a measuring device (such as a measuring instrument comprising a lock-in amplifier) for testing, if a test object needs to be replaced, the connection with the prior element to be tested needs to be removed, the structure of the element to be tested is fragile, and the element to be tested cannot be conveniently and quickly tested in the process of connecting and disassembling for many times. In addition, the size of the device to be tested is small, and the direct connection of the measuring device to the device to be tested is easy to be unstable, so that the accuracy of the test result is influenced.
SUMMERY OF THE UTILITY MODEL
To prior art's defect and not enough, the utility model provides a quantum chip testing arrangement.
An embodiment of the utility model provides a quantum chip testing arrangement, it has the element that awaits measuring to distribute on the quantum chip, testing arrangement includes:
the device comprises a leading-out device, a first grounding area and at least one signal leading-out area, wherein the leading-out device is provided with the first grounding area and the at least one signal leading-out area, the first grounding area is used for being electrically connected with one grounding end of the element to be tested, and the signal leading-out area is used for being electrically connected with the other end of the element to be tested;
and the test motherboard is provided with a second grounding area and signal transmission lines which are in one-to-one correspondence with the signal leading-out areas, one ends of the signal transmission lines are electrically connected with the corresponding signal leading-out areas, and the other ends of the signal transmission lines are electrically connected with the signal acquisition ends of the measuring devices.
The quantum chip testing device as described above, the extracting device comprising:
the test sub-board is provided with the first grounding area, the signal leading-out area and the signal terminals, and the signal leading-out areas correspond to the signal terminals one by one and are electrically connected with the signal terminals;
the locking seat is provided with a plurality of clamping grooves, and signal connecting sheets electrically connected with one end of the signal transmission line are arranged in the clamping grooves;
the signal connecting sheet is used for being correspondingly and electrically connected with the signal terminal.
According to the quantum chip testing device, the through holes which are in one-to-one correspondence with the signal leading-out areas are distributed on the testing daughter board;
each signal terminal is fixedly arranged in the corresponding through hole.
The quantum chip testing device comprises a signal connecting sheet and a signal connecting sheet,
the locking seat further comprises a locking driving rod, and the locking driving rod is used for driving the locking sheet so that the locking sheet moves to the positioning sheet to be in a locking state.
According to the quantum chip testing device, the locking driving rod drives the locking sheet through the eccentric wheel.
In the quantum chip testing device, the lead-out device is fixedly arranged on the testing motherboard.
The quantum chip testing device is characterized in that the leading-out device is fixedly arranged at the center of the testing motherboard,
one end of the signal transmission line is close to the center of the test motherboard, and the other end of the signal transmission line extends towards the periphery of the test motherboard.
As described above, the plurality of signal transmission lines are distributed around the center of the test motherboard.
The quantum chip testing device as described above, further comprising a header disposed on the test motherboard,
the connector comprises a central contact pin electrically connected with the other end of the signal transmission line and a shell connected with the second grounding area;
the central contact pin is used for being electrically connected with the signal acquisition end of the testing device, and the shell is electrically connected with the grounding end of the testing device.
The quantum chip testing device as described above, wherein the connector is a BNC connector.
Compared with the prior art, the quantum chip testing device provided by the utility model comprises a leading-out device and a testing mother board; be equipped with first ground connection region and at least one signal extraction region on the extraction device, first ground connection region with the ground connection one end electricity of the component that awaits measuring is connected, the signal extraction region with the other end electricity of the component that awaits measuring is connected, and the mode that the component that awaits measuring in comparing in prior art is directly connected with measuring device, the utility model discloses well component that awaits measuring is connected with the first ground connection region on the extraction device and the signal extraction region electricity earlier, carries out the mode of testing again, realizes the convenient, swiftly test of the component that awaits measuring. In addition, a second grounding area and signal transmission lines in one-to-one correspondence with the signal leading-out areas are distributed on the test mother board, one end of each signal transmission line is electrically connected with the corresponding signal leading-out area, and each element to be tested is electrically connected with the first grounding area and the signal leading-out area and then forms a test loop with the measuring device, so that a plurality of elements to be tested can be tested simultaneously. In addition, the leading-out device leads out the signal of the element to be tested for testing, and compared with the prior art that the measuring device is directly connected to the element to be tested, the measuring device in the scheme is more stable in connection, so that the test result is more accurate.
Drawings
Fig. 1 is a schematic structural diagram of the quantum chip testing device of the present invention;
fig. 2 is a schematic structural diagram of the drawing device of the present invention;
FIG. 3 is a schematic structural diagram of the test daughter board of the present invention;
fig. 4 is a schematic structural view of the locking seat of the present invention;
wherein: 100. a quantum chip; 200. a joint; 201. a central pin is inserted; 202. a housing;
1. a lead-out device; 2. testing the motherboard;
11. testing the daughter board; 12. a locking seat; 21. an outer periphery; 22. a signal transmission line;
111. a first ground region; 112. a signal lead-out area; 113. a signal terminal; 114. a via hole; 121. A card slot; 122. a signal connecting sheet; 123. locking the driving rod;
1221. positioning plates; 1222. a locking tab.
Detailed Description
The embodiments described below by referring to the drawings are exemplary only for explaining the present invention, and should not be construed as limiting the present invention.
The quantum chip is a core device for realizing quantum computation, and is provided with various elements, the structure of each element is fragile and is easily influenced by factors such as environment and the like, such as the resistance of a superconducting Josephson junction and the quantum chip, and the performance of the elements directly influences the performance of the superconducting quantum chip, so that the elements need to be tested to determine whether the performance parameters of the elements are qualified. How to conveniently and quickly test a plurality of elements and avoid the direct contact of the measuring device with the element to be tested is a problem that is continuously studied by those skilled in the art.
In the device that tests is carried out to superconducting quantum chip's component at present, directly test the component to be measured and measuring device, if need to change the test object, then need get rid of earlier the being connected with the component that awaits measuring earlier, the component that awaits measuring structure itself is comparatively fragile, and the process of many times connection dismantlements can't realize conveniently, swiftly test the performance of the component that awaits measuring. In addition, the size of the device to be tested is small, and the direct connection of the measuring device to the device to be tested is easy to be unstable, so that the accuracy of the test result is influenced.
Aiming at the troubles caused by the prior art, the applicant provides a quantum chip testing device capable of solving the problems through a large amount of work and verification.
Specifically, as shown in fig. 1, an embodiment of the present application provides a quantum chip testing apparatus, which includes an extraction apparatus 1 and a test mother board 2.
Wherein, elements to be tested are distributed on the quantum chip 100; the leading-out device 1 is provided with a first grounding area 111 and at least one signal leading-out area 112, when the leading-out device is specifically arranged, one or more signal leading-out areas 112 can be arranged, the signal leading-out areas are arranged according to the requirement of the element to be tested, the first grounding area 111 is used for being electrically connected with one grounding end of the element to be tested, and the signal leading-out area 112 is used for being electrically connected with the other grounding end of the element to be tested; second grounding areas and signal transmission lines 22 corresponding to the signal lead-out areas 112 one by one are distributed on the test motherboard 2, and one end of each signal transmission line 22 is electrically connected with the corresponding signal lead-out area 112.
The utility model discloses in the element that awaits measuring earlier with on the eduction gear 1 first ground connection region 111 with signal extraction region 112 electricity is connected, compares in prior art in measuring device lug connection be in on the element that awaits measuring, when needing to change the test object, can avoid connecting the process of dismantlement many times, realize testing the element that awaits measuring convenient, swiftly. When a plurality of components to be tested need to be tested, each component to be tested is electrically connected with the corresponding first grounding area 111 and the corresponding signal leading-out area 112, so that simultaneous testing can be realized, and the accuracy of a test result is ensured. The second grounding areas and the signal transmission lines 22 corresponding to the signal leading-out areas 112 one by one are distributed on the test motherboard 2, one end of each signal transmission line 22 is electrically connected with the corresponding signal leading-out area 112, and each element to be tested is electrically connected with the first grounding area 111 and the signal leading-out area 112 and then forms a test loop with the measuring device, so that a plurality of elements to be tested can be tested simultaneously. In addition, in this scheme extraction device 1 draws out the component signal that awaits measuring and tests, the size of the component that awaits measuring itself is less, and measuring device's measurement pin is great relatively, compare in prior art measuring device lug connection in the component that awaits measuring, thereby easily lead to the unstability of connecting to lead to the inaccuracy of test result, in this scheme measuring device's connection is more stable to guarantee the degree of accuracy of test result.
Referring to fig. 2, the lead-out apparatus 1 includes a test daughter board 11 and a locking socket 12. Referring to fig. 3, the test daughter board 11 is provided with the first ground region 111, the signal lead-out regions 112 and signal terminals 113, the signal lead-out regions 112 are in one-to-one correspondence with and electrically connected to the signal terminals 113, specifically, the signal lead-out regions 112 are in the same number and in the corresponding positions as the signal terminals 113, the signal lead-out regions 112 are electrically connected to the signal terminals 113 through signal lines (not shown), one end of each signal line is connected to the signal lead-out region 112, and the other end of each signal line is connected to the signal terminals 113. A plurality of clamping grooves 121 are formed in the locking seat 12, and signal connecting sheets 122 electrically connected with one ends of the signal transmission lines 22 are arranged in the clamping grooves 121; the signal connecting sheet 122 is used for being correspondingly and electrically connected with the signal terminals 113, the signal terminals 113 are correspondingly inserted into the card slots 122 and are electrically connected with the signal connecting sheet 122, and more preferably, the number of the card slots 121 is the same as that of the signal terminals 113 and the signal connecting sheet 122, so that the signal terminals 113 are just correspondingly arranged in the card slots 121 one by one and are electrically connected with the signal connecting sheet 122.
In the specific setting, with reference to fig. 3, the test daughter board 11 is distributed with via holes 114 corresponding to the signal leading-out regions 112 one to one; each of the signal terminals 113 is fixedly disposed in the corresponding via hole 114, and more preferably, the number of the via holes 114 is equal to the number of the signal terminals 113.
In a specific arrangement, referring to fig. 4, the signal connecting piece 122 includes a positioning piece 1221 and a locking piece 1222, the locking seat 12 further includes a locking driving rod 123, and the locking driving rod 123 is configured to drive the locking piece 1222, so that the locking piece 1222 moves to the positioning piece 1221 to a locking state.
The locking driving rod 123 drives the locking plate 1222 through an eccentric wheel (not shown in the figure), and one end of the signal terminal 113 is correspondingly connected in the slot 121 and electrically connected with the signal connecting plate 122 in the slot 121, so as to electrically connect the test daughter board 11 with the locking seat 12, and to implement signal transmission. Therefore, signals are led out through the test daughter board 11 and the locking seat 12, the measuring device is not directly connected to the element to be measured, so as to ensure stable use performance of the element to be measured, and due to the small structure of the element to be measured, compared with the prior art in which the measuring device is directly connected to the element to be measured, the connection of the measuring device in the scheme is more stable, so as to ensure stable signal transmission; and if a plurality of the elements to be tested are tested, a plurality of loops can be formed. Compared with the prior art that the use performance of the element to be detected can be influenced by the measuring device through repeated disassembly relative to the element to be detected, the scheme does not need repeated disassembly, and ensures that the element to be detected is stable in structure so as to enable signals to be stably transmitted. Further, as the number of the elements to be tested increases, for example: and by means of the superconductive Josephson junction, the extension of the leading-out device 1 can be realized by synchronously extending the clamping groove 121, so that more elements to be tested can be tested.
In a preferred embodiment, the locking driving rod 123 is rotatably connected to the locking plate 1222 via an eccentric (not shown in the figure), the locking driving rod 123 is clamped in the curvature of the eccentric, and when the locking driving rod 123 moves, the locking driving rod 123 gradually approaches the center of the bottom of the eccentric along the curvature due to the action of the eccentric, so as to tighten the distance between the locking plate 1222 and the positioning plate 1221, thereby fastening the connection. The locking tab 1222 is moved relative to the positioning tab 1221 to lock the signal terminal 113 by the locking tab 1222, and specifically, the locking driving rod 123 rotates clockwise around the connection point with the locking tab 1222 to drive the locking tab 1222 to move close to the positioning tab 1221 to a locking state, so as to prevent the signal terminal 113 from shaking and affecting stable signal transmission; the locking driving rod 123 rotates counterclockwise around the connection point with the locking tab 1222, so as to drive the locking tab 1222 to move away from the positioning tab 1221 to the release state, thereby locking and releasing the signal terminal 113 for installation and taking.
As an implementation of this embodiment, the lead-out device 1 is fixedly disposed on the test motherboard 2. In a more preferable embodiment, the lead-out device 1 is fixedly arranged at the center of the test motherboard 2, so that stable signal transmission is facilitated, and a test result is more accurate. Wherein the center of the test motherboard 2 refers to a geometric center of the test motherboard 2.
When specifically setting up, the one end of signal transmission line 22 is close to the center of test motherboard 2, the other end to the periphery 21 of test motherboard 2 extends, signal transmission line 22 is used for drawing forth the signal of the element that awaits measuring, so that measuring device is right the test signal of the element that awaits measuring tests. Further, a plurality of signal transmission lines 22 are distributed around the center of the test motherboard 2, so that a multi-layer distribution around the center of the test motherboard 2 is realized, and the expansion is facilitated.
The element to be measured may be a superconducting josephson junction or a resistor, and it is understood that the superconducting josephson junction is a three-layer SIS (superconducting-insulation-superconducting) structure, and the structure has a superconducting tunneling effect, and whether the superconducting tunneling effect is present or not is related to an applied voltage, so that measurement of the three-layer structure may select a dynamic parameter for measurement, such as a voltage-current relationship curve of the superconducting josephson junction, or may measure the resistance of the superconducting josephson junction with a fixed parameter. Those skilled in the art can set the setting according to their own needs, and the embodiment is not limited in particular.
Referring again to fig. 1, the test apparatus further includes a connector 200 disposed on the test motherboard, where the connector 200 includes a central pin 201 electrically connected to the other end of the signal transmission line 22, and a housing 202 connected to the second ground region; the central pin 201 is used for being electrically connected with a signal output end of the testing device, and the shell 202 is electrically connected with a signal input end of the testing device.
One end of the signal transmission line 22 is electrically connected to the corresponding signal leading-out region 112, the other end is electrically connected to the central pin 201, the measuring device is electrically connected to the central pin 201, the shell 202 is grounded, so that a test signal of the element to be tested is led out, the test signal is a voltage signal and a current signal, and a required performance parameter is a voltage-current relation curve, and then the curve is directly drawn. Or, the test signal is a voltage signal and a current signal, and the required performance parameter is a resistance, the signal processing is performed according to the relationship of voltage, current and resistance, and the device to be tested can be tested without directly connecting the measuring device to the device to be tested with a smaller structural size, so as to obtain the performance parameter of the quantum chip 100. And the element to be tested can be tested simultaneously without repeated disassembly, so that the structure and the service performance of the element to be tested are prevented from being influenced, in addition, the same testing environment is ensured, and the accuracy and the reliability of a testing result are ensured.
In this embodiment, the connector is a BNC connector, or other types of coaxial cables are selected according to the requirement, and is not limited herein.
Based on the characteristic that the performance parameter value of the device under test is usually small and easily buried in a noise signal, in this embodiment, the measuring device may be an instrument including a lock-in amplifier.
The utility model provides a quantum chip testing arrangement, the element that awaits measuring earlier with on the extraction device 1 first ground connection region 111 with signal extraction region 112 electricity is connected, has avoided connecting many times and has dismantled and cause thereby the damage of the element that awaits measuring influences quantum chip 100's performance. Each the element to be tested with first ground region 111 with signal extraction region 112 electricity is connected, signal extraction region 112 again by signal transmission line 22 draws forth the signal, and then tests, realizes simultaneously to a plurality of the element to be tested tests, and compare in prior art need be to a plurality of the element to be tested tests alone one by one, and is more convenient, swift in this scheme, and guarantees that all the test environment of the element to be tested keeps the unanimity, improves test accuracy greatly.
In addition, the leading-out device 1 leads out the signal of the element to be tested for testing, and compared with the prior art that the measuring device is directly connected to the element to be tested, the connection of the measuring device in the scheme is more stable, so that the accuracy of the test result is improved.
The structure, features and effects of the present invention have been described in detail above according to the embodiment shown in the drawings, and the above description is only the preferred embodiment of the present invention, but the present invention is not limited to the implementation scope shown in the drawings, and all changes made according to the idea of the present invention or equivalent embodiments modified to the same changes should be considered within the protection scope of the present invention when not exceeding the spirit covered by the description and drawings.
Claims (10)
1. A quantum chip testing device, elements to be tested are distributed on the quantum chip,
characterized in that, the testing device includes:
the device comprises a leading-out device, a first grounding area and at least one signal leading-out area, wherein the leading-out device is provided with the first grounding area and the at least one signal leading-out area;
and the test motherboard is provided with a second grounding area and signal transmission lines which are in one-to-one correspondence with the signal leading-out areas, one ends of the signal transmission lines are electrically connected with the corresponding signal leading-out areas, and the other ends of the signal transmission lines are electrically connected with the signal acquisition ends of the measuring devices.
2. The quantum chip testing device of claim 1, wherein the extraction device comprises:
the test sub-board is provided with the first grounding area, the signal leading-out area and the signal terminals, and the signal leading-out areas correspond to the signal terminals one by one and are electrically connected with the signal terminals;
the locking seat is provided with a plurality of clamping grooves, signal connecting pieces electrically connected with one end of the signal transmission line are arranged in the clamping grooves, and the signal connecting pieces are used for being correspondingly and electrically connected with the signal terminals.
3. The quantum chip testing device of claim 2, wherein via holes corresponding to the signal leading-out areas one to one are distributed on the test daughter board;
each signal terminal is fixedly arranged in the corresponding through hole.
4. The quantum chip testing device of claim 2, wherein the signal connection pad comprises a positioning pad and a locking pad,
the locking seat further comprises a locking driving rod, and the locking driving rod is used for driving the locking sheet so that the locking sheet moves to the positioning sheet to be in a locking state.
5. The quantum chip testing device of claim 4, wherein the locking driving rod drives the locking tab through an eccentric wheel.
6. The quantum chip testing device of claim 1, wherein the extraction device is fixedly arranged on the test motherboard.
7. The quantum chip testing device of claim 6, wherein the extraction device is fixedly arranged at the center of the test motherboard,
one end of the signal transmission line is close to the center of the test motherboard, and the other end of the signal transmission line extends towards the periphery of the test motherboard.
8. The quantum chip testing device of claim 7, wherein a plurality of the signal transmission lines are distributed around a center of the test motherboard.
9. The quantum chip testing device of claim 1, further comprising a header disposed on the test motherboard,
the connector comprises a central contact pin electrically connected with the other end of the signal transmission line and a shell connected with the second grounding area;
the central contact pin is used for being electrically connected with the signal acquisition end of the testing device, and the shell is electrically connected with the grounding end of the testing device.
10. The quantum chip testing device of claim 9, wherein the connector is a BNC connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021259288.1U CN212693960U (en) | 2020-06-30 | 2020-06-30 | Quantum chip testing arrangement |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021259288.1U CN212693960U (en) | 2020-06-30 | 2020-06-30 | Quantum chip testing arrangement |
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| CN212693960U true CN212693960U (en) | 2021-03-12 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114944380A (en) * | 2022-06-07 | 2022-08-26 | 合肥本源量子计算科技有限责任公司 | Test structure, quantum chip and manufacturing and testing methods thereof |
| CN114966364A (en) * | 2022-04-25 | 2022-08-30 | 苏州浪潮智能科技有限公司 | SPI test device and server |
-
2020
- 2020-06-30 CN CN202021259288.1U patent/CN212693960U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114966364A (en) * | 2022-04-25 | 2022-08-30 | 苏州浪潮智能科技有限公司 | SPI test device and server |
| CN114966364B (en) * | 2022-04-25 | 2024-01-16 | 苏州浪潮智能科技有限公司 | SPI test device and server |
| CN114944380A (en) * | 2022-06-07 | 2022-08-26 | 合肥本源量子计算科技有限责任公司 | Test structure, quantum chip and manufacturing and testing methods thereof |
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