CN114944380A - Test structure, quantum chip and manufacturing and testing methods thereof - Google Patents

Abstract

The application discloses a test structure, a quantum chip and manufacturing and testing methods thereof, and belongs to the field of quantum chip packaging. The test structure comprises a first conducting wire, a second conducting wire, a plurality of conducting columns and a plurality of first measuring lines. The first conducting wire and the second conducting wire are located on different surfaces and are connected through a plurality of conducting posts which are arranged at intervals to form a circuit to be tested. Each first measuring line is independently connected with the first conducting wire, so that two conducting columns are arranged between any two adjacent first measuring lines. Therefore, the connectivity of any group of conductive columns and the first conducting wires and the second conducting wires between the conductive columns can be measured by using the first measuring lines in the test structure.

Description

Test structure, quantum chip and manufacturing and testing methods thereof

Technical Field

The application belongs to the field of quantum chip packaging, and particularly relates to a test structure, a quantum chip and manufacturing and testing methods thereof.

Background

Currently, quantum chips are usually designed with a planar structure. However, as the number of qubits in a quantum chip increases, it has become increasingly difficult for planar structure designs to meet practical requirements. For example, the planar structure may result in a quantum chip having a large volume, which is not favorable for improving the integration and miniaturization of the quantum chip. Meanwhile, the internal space of a refrigerator used in the test and operation process of a superconducting quantum chip is limited, which also limits the volume of the quantum chip not to be too large.

Therefore, a solution to the problem of the excessive volume of the quantum chip is urgently required. On the basis, the three-dimensional packaging of the quantum chip is proposed, wherein the flip-chip bonding scheme is particularly prominent. However, the flip chip bonding scheme has high process requirements, and the performance parameters and design parameters of the packaged quantum chip are prone to unknown fluctuation, so that it is necessary to test the flip chip bonding quantum chip.

Disclosure of Invention

In view of the above, the present application discloses a test structure, a quantum chip, and methods for manufacturing and testing the same. The scheme can be used in the manufacturing process of the quantum chip to improve the manufacturing process. The test structure can be used for testing and screening in advance, so that the yield of the manufactured quantum chip is improved, and the manufacturing cost of the quantum chip is reduced.

The scheme exemplified in the present application is implemented as follows.

In a first aspect, the present examples provide a test structure for application to a quantum chip having first and second non-planar surfaces.

The test structure includes:

the first lead is arranged on the first surface;

the second lead is configured on the second surface;

a plurality of conductive columns arranged at intervals, wherein each conductive column is configured to be electrically connected with the first conducting wire and the second conducting wire through two ends respectively, so that the first conducting wire, the plurality of conductive columns and the second conducting wire form a circuit to be tested; and

the first measuring lines are configured on the first surface and are respectively and independently electrically connected with the first conducting wires, so that two conducting columns are arranged between any two adjacent first measuring lines.

The test structure is provided with leads (a first lead and a second lead) respectively on two different surfaces (a first surface and a second surface) in the quantum chip, and is provided with a first measuring line for testing the quantum chip. The test structure is used for testing, the on-off condition of the conductive columns, the first conducting wire and the second conducting wire can be measured, so that the quantum chips which are qualified in interconnection of the conductive columns, the first conducting wire and the second conducting wire can be identified, the unqualified quantum chips can be screened out as early as possible, the follow-up processing operation can be avoided, and unnecessary waste in the processing procedure can be reduced. Therefore, the yield of products obtained by performing subsequent processing on the quantum chips qualified in the test is also improved.

The conductive column is used for realizing the electric connection with the first conducting wire and the second conducting wire which are respectively arranged on two different surfaces. Therefore, when the conductive pillar, the first conductive line and the second conductive line are connected to form a circuit path, it indicates that the two different surfaces in the quantum chip are configured to the expected positions, and accordingly, other components (such as buses, resonant cavities, etc.) on the quantum chip located on the two different surfaces should also be configured correctly. Therefore, the plurality of connection points of the bus on two different surfaces are corresponded through the tested circuit formed by the first conducting wire, the second conducting wire and each conducting post, so that the on-off state of each connection point of the bus can be correspondingly determined according to the determination of the on-off condition of each group of conducting posts in the test structure.

Then, the scheme of the example of the application can convert the test of the whole bus into the test of each conductive pillar of the test structure, thereby simplifying the test operation and reducing the requirement on test equipment.

In short, by configuring the test structure described above, a direct test operation on the aforementioned bus can be converted into a test operation on the test structure. The test structure is used for determination, so that the test mode is simplified, and the operation of test equipment and instruments is facilitated. In addition, the test structure can also be used for accurately judging the position of the bus where the open circuit occurs, thereby being convenient for identification and processing.

According to some examples of the application, the test structure further comprises a definition of one or more of:

the test structure also comprises a second measurement line and a third measurement line which are respectively electrically connected with two ends of the circuit to be tested;

in a second definition, the test structure further comprises a plurality of surrounding pillars arranged annularly around the conductive pillars;

a third definition, each of the plurality of conductive pillars is independently a metal pillar or a superconducting pillar;

and fourthly, the projection of the first conducting wire and the second conducting wire on the preset plane is in a linear structure.

According to some examples of the present application, the plurality of conductive pillars in the test structure are each selected to be indium pillars.

In a second aspect, examples of the present application propose a quantum chip comprising:

a chip body having first and second surfaces that are non-planar; and

the test structure is disposed on the chip body.

According to some examples of the present application, the chip body has a first chip and a second chip, the first surface is disposed on the first chip, and the second surface is disposed on the second chip;

or the number of the test structures is multiple;

or the number of the test structures is multiple, all the test structures are respectively and independently located in a first area or a second area of the chip body, the first area is located at the edge of the chip body, and the second area is far away from the first area.

According to some examples of the present application, the quantum chip is a flip chip, and the first chip and the second chip are stacked in a predetermined direction.

According to some examples of the application, the projection of the second chip is located within the projection of the first chip in a projection plane perpendicular to the predetermined direction.

In a third aspect, examples of the present application propose a method of fabricating a quantum chip.

The manufacturing method comprises the following steps:

providing a chip body, wherein the chip body is provided with a first surface and a second surface which are different; and

manufacturing a test structure on the chip body;

the test structure comprises a first conducting wire, a plurality of conducting columns, a second conducting wire, a plurality of first measuring lines, and a second measuring line and a third measuring line which are optionally configured;

the first lead is arranged on the first surface, and the second lead is arranged on the second surface;

the plurality of conductive columns are arranged at intervals and are respectively configured to be electrically connected with the first conducting wire and the second conducting wire at two ends, so that a circuit to be tested is formed by the first conducting wire, the plurality of conductive columns and the second conducting wire;

the plurality of first measuring lines are arranged on the first surface and are respectively and independently electrically connected with the first conducting wires, so that two conducting columns are arranged between any two adjacent first measuring lines;

the second measuring line and the third measuring line are respectively electrically connected with two ends of a tested circuit formed by the first conducting wire, the plurality of conducting posts and the second conducting wire.

According to some examples of the application, during the process of manufacturing the test structure on the chip body, the first conducting line, the second conducting line, the plurality of first measuring lines and the second measuring line and the third measuring line which are optionally configured are manufactured in the same step.

In a fourth aspect, examples of the present application propose a method of testing a quantum chip.

The test method comprises the following steps:

providing a quantum chip with the test structure;

and performing measurement operation on the quantum chip through a plurality of first measurement lines of the test structure, and determining whether a circuit-under-test formed by the first conducting wire, the plurality of conducting posts and the second conducting wire has an open circuit point according to the measurement result of the measurement operation.

According to some examples of the application, the testing method further comprises, with the quantum chip configured with a bus: before the measurement operation is performed, the bus is tested for a short circuit to ground.

According to some examples of the present application, the measurement operation performed by the plurality of first measurement lines is performed when the following condition is satisfied: the test confirms that the bus is not shorted to ground.

According to some examples of the application, the testing method further comprises: whether a disconnection point exists in the bus is determined based on a measurement result obtained by performing a measurement operation through a plurality of first measurement lines.

According to some examples of the present application, a measurement operation performed by a plurality of first measurement lines of a test structure includes:

and taking two adjacent first measurement lines in the test structure as measurement points, and carrying out on-off test on a group of conductive columns between the two adjacent first measurement lines.

According to some examples of the present application, a method of determining whether a disconnection point exists in a bus from measurement results obtained by performing a measurement operation through a plurality of first measurement lines includes:

executing the on-off test at least once, and judging that the bus has an open circuit point when the test result of any one on-off test indicates that the open circuit exists; and/or executing the on-off test for multiple times to complete the test of all the conductive columns, and judging that the bus does not have a broken circuit point when the test result of all the on-off tests is that the bus does not have the broken circuit.

According to some examples of the application, the test method further comprises a first operation, or the first operation and a second operation performed in sequence, or the first operation, the second operation, and a third operation performed in sequence;

wherein the first operation comprises: when the fact that the bus does not have the broken point is determined according to the measuring result of the measuring operation, the quantum chip is packaged in the packaging box;

wherein the second operation comprises: under the condition that the test structure is provided with a second measurement line and a third measurement line, the impedance of the bus is determined by a four-wire method by using the second measurement line and the third measurement line;

wherein the third operation comprises: and when the impedance determined through the second operation is matched with the design value, placing the packaged quantum chip in a refrigerator to test the selected parameters.

Has the advantages that:

compared with the prior art, the test structure of the example of the application forms the circuit to be tested by manufacturing the first conducting wire on the first surface and the second conducting wire on the second surface of the two different surfaces of the quantum chip, and also configuring a plurality of conducting columns for electrically connecting the first conducting wire and the second conducting wire. On the basis, the circuit to be tested is tested by utilizing a plurality of first measuring lines for electrically connecting the first conducting wire and the second conducting wire in the test structure. The test can determine the make and break of the circuit under test and the location of the break when it exists. And furthermore, the on-off condition of the bus in the quantum chip can be inferred based on the test result, so that the inconvenience of measuring the on-off of the bus is overcome.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the prior art of the present application, the drawings used in the description of the embodiments or the prior art will be briefly described below.

Fig. 1 is a schematic structural diagram illustrating a distribution manner of first conductive lines, second conductive columns and a test structure according to an embodiment of the present disclosure;

FIG. 2 shows a schematic top view of the structure of FIG. 1;

FIG. 3 is a schematic structural diagram illustrating a connection mode of a first measurement line in a test structure according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram illustrating a connection manner of a first measurement line, a second measurement line and a third measurement line in a test structure provided by an embodiment of the present application;

fig. 5 is a schematic structural diagram illustrating a distribution manner of the conductive pillars and the surrounding pillars in the embodiment of the present application;

fig. 6 shows a schematic structure diagram of a layout of a quantum chip having two test structures in an example of the present application;

FIG. 7 shows a schematic diagram of a layout of a quantum chip with two test structures and with a resonant cavity and a qubit in an example of the application;

fig. 8 shows a flow chart of a testing method of a quantum chip based on a test structure in an example of the present application.

An icon: 101-a first surface; 102-a second surface; 21-a first wire; 22-a second wire; 23-a conductive post; 24-a first measurement line; 25-a second measurement line; 26-a third measurement line; 27-surrounding the cylinder; 30-a test structure; 40-a bus; 50-a resonant cavity; 60-qubit.

Detailed Description

Flip chip bonding is a circuit package interconnection technique by connecting the separate structures of the upper and lower layers with a conductive structure therebetween. The use of flip-chip interconnection technology can reduce the volume of the quantum chip. However, this is a relatively demanding flip-chip technique. For example, the alignment of the upper and lower layers needs to be precise, which may result in interconnect failure.

In flip-chip bonding of quantum chips, two planar chips (with various appropriately configured circuit components and circuitry) are stacked in layers. The upper chip (marked as Flip) is reversely buckled on the upper surface of the lower chip (marked as Base), and the middle of the upper chip and the lower chip are pressed through an indium column.

In addition, in order to facilitate the layout of wiring and various circuit components, the coupling structure in the quantum chip is designed correspondingly by combining the flip chip interconnection technology. For example, one of two coupled components (such as a resonant cavity, a bus, an X-ray or a Z-ray in a superconducting quantum chip) is configured on the Flip chip, and the other is configured on the Base; or one of the two elements is configured to be out-of-plane with respect to Flip and Base, respectively, while the one and the other element are coupled in the same layer in a portion where the one and the other elements are disposed in the same layer.

In practice, the inventors couple the resonator and the bus applied in the quantum chip to the same plane. And the bus is constructed into two parts and respectively configured to different surfaces of the quantum chip, and one part of the two parts of the bus is coupled with the resonant cavity in the same surface. The two parts of the bus which are constructed and distributed on different surfaces are connected through a flip chip interconnection technology.

It is necessary to test such a distributed bus after flip-chip interconnection, since the aforementioned flip-chip interconnection techniques may risk failure of a bus constructed in the manner described above.

However, in practical tests, the inventor found that it is difficult to accurately determine whether there is a disconnection in the bus. Analysis shows that at room temperature, because one bus can shuttle up and down on Base and Flip, and materials such as titanium nitride and indium are often added to Base and Flip, the on-off of the bus cannot be judged by measuring the resistance of the bus. In addition, the distance between two pads of the bus is too large to be measured by the probe station, so that the probe station cannot be used to test the on/off of the bus.

The inventors propose solutions in the present application in order to overcome the above-mentioned problems. The example schemes mentioned later will be disclosed below with reference to fig. 1 to 8.

In order to more conveniently test the bus 40 (shown in fig. 7 and described later), the inventor proposes a test structure 30 applied to a quantum chip in the example of the present application.

The quantum chip has a first surface 101 and a second surface 102, which are not coplanar. For quantum chips of different configurations, the first surface 101 and the second surface 102 may be arranged in correspondingly different ways. For example, when the quantum chip is a Flip-chip quantum chip based on the aforementioned Flip-chip interconnection technology, the aforementioned first surface 101 may be located at Base, and the second surface 102 may be located at Flip, so as to realize an out-of-plane distribution of the first surface and the second surface; and vice versa. Alternatively, in a Flip-chip bonded quantum chip, the first 101 and second 102 surfaces may both be at Base or both at Flip; alternatively, in a non-flip-chip bonded quantum chip, the first surface 101 and the second surface 102 may be formed or formed in different locations.

The test structure 30 includes a first conductive line 21, a second conductive line 22, a conductive pillar 23, and a first measurement line 24. The first conductive line 21 is disposed on the first surface 101 of the quantum chip, and the second conductive line 22 is disposed on the second surface 102 of the quantum chip. The first conductor 21 corresponds to a portion of the bus bar 40 that is coupled coplanar with the resonant cavity 50, while the second conductor 22 corresponds to another portion of the bus bar 40 that is out of plane with the portion coupled.

Since the first wire 21 and the second wire 22 are in the non-coplanar position, the first wire 21 and the second wire 22 are required to be connected for use in a quantum chip. In the present example, the first conductive line 21 and the second conductive line 22 are connected by the conductive pillar 23.

The conductive post 23 is made of a conductive material, and may be a metal material by way of example. Thus, the conductive post 23 may be a metal post. Alternatively, the conductive pillars 23 are, for example, indium pillars (which may also be used as a superconducting material), and accordingly, the conductive pillars 23 may also be superconducting pillars. Since there are a plurality of conductive pillars 23, the material for forming each conductive pillar 23 may be independently selected, but need not be the same. Further, the arrangement of the conductive posts 23 may be optimized or adjusted as appropriate.

In the structures illustrated hereinafter (e.g., fig. 2, 3 and 4), each conductive post 23 is formed by a single post. In other examples, each conductive post 23 may also be configured in a combination of multiple posts. Further, as an example of a partial solution, the test structure 30 may further include a plurality of surrounding pillars 27, and the surrounding pillars 27 are annularly arranged around the conductive pillar 23. In an alternative example, four surrounding pillars 27 are arranged around each conductive pillar 23, see fig. 5. Wherein the surrounding pillar 27 and the conductive pillar 23 are respectively configured as a cylinder, and the diameter of the bottom surface of the conductive pillar 23 is larger than (in other examples, the diameters of the bottom surfaces of the surrounding pillar 27 may be the same or smaller than) the diameter of the bottom surface of the surrounding pillar 27.

In other words, in some examples, the conductive pillars 23 may adopt an indium pillar combination structure of a five-link pattern — it is known that the vertically opposite positions of Base and Flip may both have five links; the bottom surface shape of the five-link ring, i.e. five indium columns, is circular, for example. The middle ring of the five rings is used for wiring (i.e. electrically connected to the first wire 21 and the second wire 22), and the four rings disposed at four positions on the periphery are used for supporting the upper and lower chips. The five indium columns are uniform in height, for example, on the order of 10 μm, in order to enable uniform support and routing. When Flip chip bonding is performed, the Flip chip bonding machine is used for bonding, and the total height of the indium columns of Base and Flip after bonding is 10 μm, which is more helpful for ensuring that each indium column can be bonded.

It is verified that in the example where the surrounding pillars 27 are not configured, the uniformity of the structure and size of each conductive pillar 23 helps to improve the connection quality of the Base and Flip layers in the quantum chip configured by the Flip-chip interconnection technology. That is, arranging the respective conductive posts 23 in the foregoing manner makes it easier to connect the aligned upper and lower chips with high quality. Further, when surrounding pillars 27 are present, the uniformity in the number, structure, and arrangement of surrounding pillars 27 around each conductive pillar 23 also helps to improve the quality of the flip chip bonding.

Further, it is particularly prominent when indium columns are used for the conductive columns 23 and the surrounding columns 27. After analysis, the inventors believe that this is due to:

for the condition that Base and Flip in the Flip-chip are pressed through the indium columns, because the indium columns are soft in material, in the pressing process, if the pressure provided by the Flip-chip welding machine is too small, the pressing is not tight, and the possibility of falling exists. Also, if the pressure provided by the flip-chip bonding machine is too high, the indium columns are likely to be seriously deformed, and even the indium columns may overflow, thereby possibly causing short circuit.

In addition, in a quantum chip with a large number of qubits 60, the number of indium columns between Base and Flip is also large, and can even reach tens of thousands. The indium columns occupy a certain proportion of the area of the Flip to ensure that the chip is firmly pressed and cannot fall off. If the distance between the indium columns and the bus 40, the resonant cavity 50 or the indium columns is too small, the requirement on the pressing force of the flip-chip welding machine is higher, the control difficulty is higher, and therefore stable implementation is not easy.

Therefore, by increasing the contact area of the conductive pillar 23 and the chip to some extent (for example, by properly increasing the diameter of the bottom circle of the conductive pillar, or disposing a surrounding pillar around the conductive pillar), it is helpful to avoid the problem that the contact area is small and the stable and firm contact is not easy to occur, and the tolerance for the pressing force provided by the flip-chip bonding machine is higher.

From the overall appearance of the quantum chip, when the first surface 101 and the second surface 102 are aligned with each other in a top view of the quantum chip, it may be considered to construct the conductive pillar 23 in a cylindrical shape, a straight prism shape, or a tilted prism shape. In these examples, the conductive post 23 has a substantially linear profile in the columnar direction. When the first surface 101 and the second surface 102 are offset from or not directly opposite to each other in a top view of the quantum chip, the conductive pillar 23 may be considered to be constructed in a bent pillar, an oblique pillar, or the like.

To integrate more qubits 60 in a quantum chip, some quantum chip examples are configured with multiple resonant cavities 50 coupled to qubits 60, and therefore require that bus 40 be separately coupled to these resonant cavities 50. There are multiple coupling locations for the entire bus 40. In response, test structure 30 also exists in a plurality of locations corresponding to bus 40.

Referring to fig. 1, a first surface 101 and a second surface 102 on a quantum chip are distributed in an upper-lower layer, a first conductive line 21 is located on the first surface 101, and a second conductive line 22 is located on the second surface 102. One end of the conductive column 23 is connected to the first conductive line 21, and the other end is connected to the second conductive line 22; alternatively, the conductive column 23 is connected to the first conductive line 21 and the second conductive line 22 through both ends.

The first conductive line 21 and the second conductive line 22 are connected by a conductive post 23 to form a circuit under test, such as a series circuit. As an example, the first conductive line 21 is formed by combining a plurality of segments, and similarly, the second conductive line 22 is formed by combining a plurality of segments; or the first wire 21 has a plurality of wires, and the second wire 22 also has a plurality of wires. And, correspondingly, the conductive post 23 also has a plurality; these conductive posts 23 are spaced apart from each other to avoid direct contact between the conductive posts 23 and electrical connection. Thus, the first conductive line 21, the conductive column 23, and the second conductive line 22 may constitute a serial connection structure connected end to end in sequence. It should be noted that fig. 1 discloses the configuration of the conductive wires and the conductive pillars 23 by way of example, which is not meant to be the only solution. Fig. 2 is a schematic top view of the arrangement shown in fig. 1.

In the test structure 30, as described above, the first conductive line 21 may correspond to a portion (referred to as a first portion) of the bus line 40 coupled to the resonant cavity 50, and the second conductive line 22 may correspond to a second portion of the bus line 40 that is disposed to facilitate wiring and is different from the first portion.

The test structure 30 is configured with a first measurement line 24 based on the requirement of facilitating the measurement and confirming whether the entire circuit under test is connected or not through the measurement result. As an example, a schematic structural view of the way in which the first measurement lines 24 are arranged is disclosed in fig. 3.

In fig. 3 is shown the case where all the first measurement lines 24 are located at the same surface of the quantum chip; three first measurement lines 24 are shown and are all located at the first surface 101. In such an example, the connectivity between any two adjacent first measuring lines 24, where two conductive pillars 23 (i.e., a group of conductive pillars) are connected with the first conductive line 21 and the second conductive line 22 through the upper and lower ends, can be measured. Moreover, since there are two conductive pillars 23 between any two adjacent first measurement lines 24, when an open circuit occurs during measurement, it may not be easy to determine which of the two conductive pillars 23 is not connected directly through the measurement result. However, since the measurement lines are all arranged in one plane (e.g., the first surface 101), relatively more space may be reserved for the other surface (e.g., the second surface 102, respectively) for various component arrangements.

In addition, as can be seen from fig. 3, the projection of the entire exemplary test structure 30 on the first surface 101 or the second surface 102 is a linear structure; the linear structure mainly refers to the arrangement or the routing shape of the first conductive lines 21 and the second conductive lines 22.

As in the foregoing examples of the present application, the respective first measurement lines 24 are each independently electrically connected to the first conductive line 21. Further, based on subsequent testing needs, in other examples, the test structure 30 may also be configured with a second measurement line 25 and a third measurement line 26. And the manner of connection of the second measuring line 25 and the third measuring line 26 is clarified by the following description: the first conductive line 21, the plurality of conductive pillars 23, and the second conductive line 22 form a circuit under test, and the second measurement line 25 and the third measurement line 26 are electrically connected to both ends of the circuit under test, respectively.

The application of the test structure in quantum chips will be described later.

Based on the test structure 30 in the above description, the present application also proposes a quantum chip in the example, which includes a chip body and the test structure 30. The chip body may be formed of a single chip. The single chip provides both the first surface 101 and the second surface 102. And on the basis thereof, the test structure 30 is arranged in correspondence with the first surface 101 and the second surface 102. The first conductor 21 is placed on the first surface 101 and the second conductor is placed on the second surface 102. The arrangement of the test structures 30 with respect to the first surface 101 and the second surface 102 has been explained above, and is not described herein in detail.

In other examples, the chip body may have a first chip and a second chip that are independent, the first surface 101 and the second surface 102 may be provided by both the first chip and the second chip, or the first surface 101 is located on the first chip and the second surface 102 is located on the second chip.

It is noted that the first chip and the second chip may be attached to the same surface or area of the chip body, i.e. a tiled arrangement. Or as an example of a flip-chip bonded quantum chip, the two chips are stacked in a layered structure, or stacked along a predetermined direction (thickness direction of the quantum chip); i.e., the two chips are located on different surfaces or areas of the chip body.

In addition, the first chip and the second chip may have the same planar size and shape, and therefore, in the predetermined direction, the outlines of the two chips may coincide in a top view. Of course, in other examples, the two may also exhibit different dimensions; for example, in a projection plane perpendicular to the predetermined direction, the projection of the first chip is located outside the projection of the second chip, i.e., the projection of the second chip is within the projection of the first chip, as shown in fig. 6 and 7.

As a specific and optional example, the projected outline of the first chip and the second chip is rectangular, and then the distance between the outline of the first chip and the outline of the second chip is, for example, 5mm or more. The structure mode is that when the quantum chip is packaged subsequently, the cutter head of the wire bonding machine has an upward-lifting radian. Then, when the aforementioned distance is less than 5mm, it may cause the bit to hit the Flip chip, so that there is a great risk that the pad does not line up.

Fig. 6 and 7 disclose a quantum chip with two test structures 30, respectively; other examples may have three, four, or even more test structures. In fig. 6, two test structures 30 are located at the edge of the upper side and at the edge of the lower side of the chip, with the orientation shown in the figure. In other examples, one or more test structures 30 may also be disposed between the upper and lower test structures 30. Alternatively, the chip is defined to have a first region at the edge and a second region, or inner region, away from the edge. Thus, in the case of a quantum chip having a plurality of test structures 30, some of the test structures 30 may be located in the aforementioned first region, while the remaining test structures 30 may be located in the second region. In conjunction with the foregoing definitions, in fig. 6, two test structures 30 are located in the first area, and the second area is not configured with test structures 30.

In order to facilitate the implementation of the above quantum chip by those skilled in the art, a method for fabricating a quantum chip is disclosed as follows:

a chip body having a first surface 101 and a second surface 102 with different surfaces is provided, and then the test structure 30 is fabricated on the chip body.

When the chip body is a single-chip structure, it may provide the first surface 101 and the second surface 102 at different areas of the single chip. Two regions having different heights and different surfaces in the thickness direction of the substrate are formed on the substrate by a process such as photolithography, and the first surface 101 and the second surface 102 are formed correspondingly. The wires, measuring lines are then made either synchronously or asynchronously.

When the quantum chip is fabricated by flip chip bonding, the first surface 101 and the second surface 102 are provided by different layers of chips, and then the wires in the test structure 30 are selectively fabricated on the different layers of chips respectively based on the first surface and the second surface.

The various conductive lines and measurement lines in test structure 30 may be selected to be fabricated in a different order, which is not specifically required or limited in this application. Exemplarily, the first conductor line 21, the second conductor line 22, the plurality of first measurement lines 24 and the second and third measurement lines 25, 26 are made in the same step. For example, each conducting wire and measuring wire is drawn into an electronic layout, and then the layout structure is "transferred" to be manufactured to a substrate of a chip or various functions and structure layers on the surface of the substrate by printing, evaporation, micro-nano manufacturing technology and combining with various proper existing processes and equipment in the field of integrated circuits.

Further, based on the test structure 30, the following test method for the quantum chip can be implemented, please refer to fig. 8.

The test method is implemented by a test structure 30 to test a quantum chip. Wherein the quantum chip has the aforementioned test structure 30 or the quantum chip has the structure of a quantum chip as defined by the foregoing and likewise has the test structure 30.

The test method in the example includes performing a measurement operation on the quantum chip through the plurality of first measurement lines 24 of the test structure 30, and determining whether a circuit-under-test constituted by the first conductive line 21, the plurality of conductive pillars 23, and the second conductive line 22 has a disconnection point according to a measurement result of the measurement operation.

Wherein the disconnection point can be clarified by the description: a complete and continuous wire, which has no disconnection point; if the wire is broken from an arbitrary position to form two or more pieces, it constitutes a disconnection point at the broken position. Therefore, based on the measurement lines in the test structure 30, any two adjacent measurement lines can be selected to determine whether there is communication between the two. For example, in a series circuit formed by configuring a power supply and a load (such as a light emitting diode) and connecting two ends of the series circuit with two adjacent measuring lines respectively, when the load works (lights up), the series circuit is indicated to have no open circuit point, and when the load does not work (lights out), the series circuit is indicated to have an open circuit point; alternatively, in other examples, a multimeter may be conveniently used to measure through the first measurement line.

As shown in fig. 3, two adjacent first measuring lines 24 are respectively selected, and connectivity between each group of conductive pillars 23 and the conductive lines at two ends thereof is measured in the manner described above. Thus, the measurement operations performed by the respective first measurement lines 24 of the test structure 30 include: the first measurement lines 24 at the two ends of any one group of conductive pillars 23 in the test structure 30 are taken as measurement points to perform on-off test on each group of conductive pillars 23. Such a switching test can be performed once, so that when a switching test is performed once and the result of this test is that there is an open circuit, it can be concluded that the bus is also open circuit, so that it can be considered to stop the continuation of the test. Or, according to the number of the conductive pillars, performing multiple on-off tests so as to test all the conductive pillars, and confirming that each group of conductive pillars in all the conductive pillars are a passage according to the test result, so that it can be concluded that the bus is a passage. This is because the vias of one set of conductive studs do not confirm that the other set of conductive studs are also vias, and therefore it cannot be inferred that the bus is a via. By testing all of the conductive pillars and confirming that each group of conductive pillars is a via, the bus can be confirmed to be a via. Generally, the on-off test of a group of conductive pillars may be performed at least once, and the number of times of performing the test may also be selected according to the result of the on-off test.

Exemplarily, three first measurement lines 24 in fig. 3 are respectively marked as a measurement line No. 1, a measurement line No. 2, and a measurement line No. 3 from left to right; the corresponding four conductive columns 23 are marked as column No. 1, column No. 2, column No. 3 and column No. 4 from left to right. Then a universal meter can be used to determine the connectivity of the column 1 and the column 2 through the measurement line 1 and the measurement line 2; accordingly, the connectivity of column No. 2 and column No. 4 was determined by measurement line No. 2 and measurement line No. 3, and so on. That is, an alternative example of the measurement operation performed by each first measurement line 24 in the test structure 30 may be to perform on-off test on each group of conductive pillars 23 by taking the first measurement lines 24 at both ends of any group of conductive pillars 23 in the test structure 30 as measurement points.

Or, in other examples, the measurement point is the first measurement point with the measurement line No. 1, and then the measurement points are the second measurement points with the measurement line No. 3 and the measurement line No. 2, respectively, and so on.

The connectivity between any one set of conductive pillars 23 and the first and second conductive lines 21 and 22 can be determined in the above manner, and it can be inferred whether the first and second surfaces 101 and 102 in the quantum chip are properly configured, for example, whether the positions of the two surfaces are proper. For example, in the flip chip quantum chip, the first surface 101 and the second surface 102 are configured by two layers of chips, so that through such on-off test, it can be inferred whether the two layers of chips are correctly aligned and pressed in place, and further, it is possible to be used for studying whether other structures and components in the chips are mounted in place-the bus distributed up and down is correctly matched.

Accordingly, the test method may further comprise determining whether a disconnection point of the bus 40 exists based on the measurement result obtained by performing the measurement operation through the respective first measurement lines 24. The method for determining whether a disconnection point exists on the bus 40 according to the measurement result obtained by performing the measurement operation through each first measurement line 24 includes:

when the test result of any on-off test indicates that the open circuit exists, judging that the bus 40 has an open circuit point; when the test results of all the on-off tests indicate that there is no open circuit, it is determined that there is no open circuit point in the bus 40.

That is, when any one of the conductive pillars 23 in the test structure 30 is in an open state, it can be estimated that the bus 40 also has an open point. When each set of conductive pillars 23 in test structure 30 is in a pass/no-break state, bus 40 can be assumed to be pass, i.e., there is no break point. This is because the chip may have warpage, etc., that is, the distances between the positions of the upper and lower chips may not be uniform, so that there may be conductive pillars at one position communicating with the conductive wires of the upper and lower layers, and conductive pillars at other positions not communicating with the conductive wires of the upper and lower layers. Thus, having all wires connected makes it more likely that the bus will never have a disconnection point.

In light of the foregoing, when the daughter chip is configured with the bus 40, the testing method may further include testing whether the bus 40 is shorted to ground before performing the measurement operation. In other words, when the test bus 40 is short-circuited to ground, it indicates that the configuration of the bus 40 to the quantum chip has a problem, and the quantum chip has a defect, and it can be considered that no subsequent processing is necessary. That is, in some examples, the measurement operation performed by each first measurement line 24 may be performed when the following conditions are satisfied: the test confirms that the bus 40 is not shorted to ground. Of course, in other examples, even if it is confirmed in advance that the bus 40 and the ground are short-circuited, the test using the test structure 30 may be continued, and accordingly, whether the conductive posts 23 and the conductive wires are communicated or not may be confirmed.

Further, in some examples, after determining that the bus 40 has no open point in the above manner, the quantum chip can be optionally packaged in a packaging box. The packaged quantum chip may then be subjected to other tests, such as a four wire method of measuring the impedance of the bus 40 via the second measurement line 25 and the third measurement line 26 arranged in the test structure 30. Among them, the Four-wire method, Kelvin Four-wire sensing, may also be referred to as Four-terminal sensing, Four-wire sensing or Four-point probe method. That is, two separate measurement positions are respectively disposed at both ends of the circuit under test constituted by the first conductive line 21, the respective conductive posts 23, and the second conductive line 22, thereby constituting four measurement points (two of them are contact points of the voltage measurement electrodes, and the other two are contact points of the current measurement electrodes). When the test is performed, the impedance of the bus 40 is tested by the four measurement points.

The second measuring line 25 and the third measuring line 26 of the configuration of fig. 4 are shown in double lines. In such an example, two second measurement lines 25 and two third measurement lines 26 are used independently of the first measurement line 24 to measure the impedance of the bus 40 by a four-wire method, as also shown in fig. 7.

When the impedance of the bus 40 measured by the four-wire method is consistent with the expected design value or the difference meets the expected deviation (i.e. the measured impedance is matched with the preset value or design value according to the preset mode), the quantum chip can be determined to be qualified, and can be further processed.

For example, when the quantum chip is a superconducting quantum chip based on superconducting qubit 60, the further processing may include placing the chip in a refrigerator to test parameters such as resonant cavity, coherence time, etc. The distribution of the relative positions of the resonant cavity 50 and the qubits 60, the bus 40 and the test structure 30 in the layout can be seen in fig. 7 as an example scenario.

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application are described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the claimed subject matter may be practiced without these specific details or with various changes and modifications based on the embodiments described herein. And the division of the embodiments is for convenience of description, and no limitation should be made to the specific implementation manner of the present application, and the embodiments may be mutually incorporated and referred to without contradiction.

It should be noted that the terms "first," "second," "third," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The construction, features and functions of the present application have been described in detail and illustrated in the drawings, the present application is not limited to the embodiments, but rather the invention is intended to cover all modifications, equivalents and equivalents falling within the spirit and scope of the present application.

Claims (15)

1. A test structure for a quantum chip having first and second non-planar surfaces, the test structure comprising:

a first conductive line disposed on the first surface;

the second lead is configured on the second surface;

a plurality of conductive pillars arranged at intervals from each other, each conductive pillar being configured to be electrically connected to the first conductive line and the second conductive line through both ends, respectively, so that a circuit under test is configured by the first conductive line and the plurality of conductive pillars and the second conductive line;

and a plurality of first measurement lines disposed on the first surface and electrically connected to the first conductive lines independently, so that two conductive pillars are disposed between any two adjacent first measurement lines.

2. The test structure of claim 1, further comprising a definition of one or more of:

the test structure further comprises a second measuring line and a third measuring line, wherein the second measuring line and the third measuring line are respectively electrically connected with two ends of the circuit to be tested;

second, the test structure further comprises a plurality of surrounding pillars arranged annularly around the conductive pillars;

a third definition, each of the plurality of conductive pillars is independently a metal pillar or a superconducting pillar;

and fourthly, the projection of the first conducting wire and the second conducting wire on the preset plane is in a linear structure.

3. A quantum chip, comprising:

a chip body having first and second surfaces that are out-of-plane; and

the test structure of claim 1 or 2, configured to the chip body.

4. The quantum chip of claim 3, wherein the chip body has a first chip and a second chip, the first surface being disposed on the first chip and the second surface being disposed on the second chip;

or the number of the test structures is multiple;

or the number of the test structures is multiple, all the test structures are respectively and independently located in a first area or a second area of the chip body, the first area is located at the edge of the chip body, and the second area is far away from the first area.

5. The quantum chip of claim 4, wherein the quantum chip is a flip-chip bonded quantum chip, and the first chip and the second chip are stacked in a predetermined direction;

or the quantum chip is a flip-chip bonded quantum chip, the first chip and the second chip are stacked along a preset direction, and the projection of the second chip is located in the projection of the first chip on a projection plane perpendicular to the preset direction.

6. A manufacturing method of a quantum chip is characterized by comprising the following steps:

providing a chip body, wherein the chip body is provided with a first surface and a second surface which are different in surface; and

manufacturing a test structure on the chip body;

wherein the test structure comprises a first conductive line, a plurality of conductive pillars, a second conductive line, a plurality of first measurement lines, and optionally configured second and third measurement lines;

the first wires are arranged on the first surface, and the second wires are arranged on the second surface;

the plurality of conductive columns are arranged at intervals and are respectively configured to be electrically connected with the first conducting wire and the second conducting wire at two ends, so that a circuit to be tested is formed by the first conducting wire, the plurality of conductive columns and the second conducting wire;

the plurality of first measuring lines are configured on the first surface and are respectively and independently electrically connected with the first conducting wires, so that two conducting columns are arranged between any two adjacent first measuring lines;

the second measuring line and the third measuring line are respectively electrically connected with two ends of the measured circuit.

7. The method of claim 6, wherein the first conductive line, the second conductive line, the plurality of first measurement lines, and the second measurement line and the third measurement line are formed in a same step during the fabrication of the test structure.

8. A test method of a quantum chip is characterized by comprising the following steps:

providing a quantum chip having a test structure according to claim 1 or 2;

and performing measurement operation on the quantum chip through the plurality of first measurement lines of the test structure, and determining whether the circuit to be tested has a broken point according to the measurement result of the measurement operation.

9. The method of testing a quantum chip of claim 8 wherein the measurement operations performed by the plurality of first measurement lines of the test structure comprise:

and taking two adjacent first measurement lines in the test structure as measurement points, and carrying out on-off test on a group of conductive columns between the two adjacent first measurement lines.

10. The method for testing the quantum chip of claim 8, wherein in the case where the quantum chip is configured with a bus, the method further comprises: before performing the measurement operation, testing whether the bus is short-circuited to ground.

11. The method for testing a quantum chip according to claim 10, wherein the measurement operation performed by the plurality of first measurement lines is performed when the following condition is satisfied: the test confirms that the bus is not shorted to ground.

12. The method of testing a quantum chip of claim 11, further comprising:

determining whether a trip point exists on the bus based on a measurement result obtained by performing the measurement operation through the plurality of first measurement lines.

13. The method of testing a quantum chip of claim 12, wherein the measurement operation performed by the plurality of first measurement lines of the test structure comprises:

and taking two adjacent first measurement lines in the test structure as measurement points, and carrying out on-off test on a group of conductive columns between the two adjacent first measurement lines.

14. The method for testing the quantum chip of claim 13, wherein the method for determining whether the bus has a trip point according to the measurement result obtained by performing the measurement operation through the plurality of first measurement lines comprises:

executing the on-off test at least once, and judging that the bus has a broken circuit point when the test result of any one on-off test indicates that the bus has the broken circuit; and/or executing the on-off test for multiple times to complete the test of all the conductive columns, and judging that the bus does not have a broken circuit point when the test result of all the on-off tests is that the bus does not have the broken circuit.

15. The method for testing the quantum chip according to any one of claims 12 to 14, wherein the method for testing further comprises a first operation, or a first operation and a second operation performed in sequence, or a first operation, a second operation, and a third operation performed in sequence;

wherein the first operation comprises: when the fact that the bus does not have the open circuit point is determined according to the measuring result of the measuring operation, the quantum chip is packaged in a packaging box;

wherein the second operation comprises: determining an impedance of the bus line by a four-wire method using a second measurement line and a third measurement line in a case where the test structure is provided with the second measurement line and the third measurement line;

wherein the third operation comprises: and when the impedance determined by the second operation is matched with a design value, placing the packaged quantum chip in a refrigerator to test selected parameters.

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