CN217387497U

CN217387497U - Coupling structure, quantum chip and flip-chip quantum chip

Info

Publication number: CN217387497U
Application number: CN202221410577.6U
Authority: CN
Inventors: 赵勇杰; 李业; 李松; 张静
Original assignee: Origin Quantum Computing Technology Co Ltd
Current assignee: Origin Quantum Computing Technology Co Ltd
Priority date: 2022-06-07
Filing date: 2022-06-07
Publication date: 2022-09-06
Anticipated expiration: 2032-06-07

Abstract

The application discloses coupling structure, quantum chip and flip-chip bonding quantum chip belongs to the quantum chip and makes the field. The coupling structure is used in a quantum chip having a qubit and first and second surfaces that are faceted. The coupling structure has a resonant cavity, a coupler, a bus, and a flip-chip interconnect. The resonant cavity is disposed on the first surface and coupled to the qubit. The coupler is configured on the first surface and connected with the resonant cavity. The bus is configured on the second surface. One of the two ends of the flip-chip interconnect is connected to the bus match signal and the other end is connected to the coupler match signal. The coupling structure realizes the different-surface coupling of the resonant cavity and the bus, so that the bus can be manufactured more conveniently, the risk of bus open circuit is reduced, the coupling quality between the resonant cavity and the bus can be improved, and the reading and the transmission of signals can be realized more easily.

Description

Coupling structure, quantum chip and flip-chip bonding quantum chip

Technical Field

The application belongs to the field of quantum chip manufacturing, and particularly relates to a coupling structure, a quantum chip and a flip chip.

Background

In a multi-bit quantum chip, a flip chip technology is currently used to reduce the volume of the quantum chip. The Flip-chip quantum chip is mainly composed of double-layer chips (marked as Flip layer chips and Base layer chips), and each layer of chip is correspondingly provided with respective routing lines and various structures. However, the current flip chip technology is immature, which causes the bus in the quantum chip to be easily broken, thereby causing a problem that it is difficult to normally read the qubit in the quantum chip through the bus.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present application discloses a coupling structure, a quantum chip and a flip chip. The coupling structure can effectively reduce the problem of open circuit of the bus in the flip chip, thereby improving the probability of effectively reading the status information of the quantum bit through the bus.

The scheme exemplified in the present application is implemented as follows.

In a first aspect, the present examples propose a coupling structure for a quantum chip having a qubit and first and second surfaces that are faceted.

The coupling structure includes:

a resonant cavity disposed at the first surface, the resonant cavity having a first end and a second end, wherein the first end is configured to couple with a qubit;

the coupler is configured on the first surface and is connected with the second end of the resonant cavity;

the bus is configured on the second surface; and

a flip-chip interconnect having two ends, one of the two ends connected to the bus match signal and the other end connected to the coupler match signal.

The coupling structure can be applied to flip chip bonding quantum chips, and the resonant cavity and the bus can be coupled in different planes by respectively configuring the resonant cavity and the bus to two layers of chips (a first surface and a second surface) in the flip chip bonding quantum chips, connecting the bus with the coupler matching signal through flip interconnection and then connecting the bus with the resonant cavity through the coupler. Therefore, the coupling mode of the resonant cavity and the bus can avoid the problems and defects existing in the configuration of the resonant cavity and the bus in the same-plane coupling.

For example, since the resonant cavity and the bus are coupled in different planes, the resonant cavity and the bus can be configured on different chips, and therefore, the bus does not need to be threaded back and forth between the upper chip and the lower chip, thereby reducing the complexity of the manufacturing process, and improving the manufacturing efficiency and the quality of the finished product.

Further, since the resonators and the bus bars are coupled out-of-plane, the bus bars can be coupled to multiple resonators, and each resonator can be relatively independent. That is, a failure in coupling between one of the resonators and the bus does not affect the coupling between the other resonators and the bus. In other words, the defect of coplanar coupling between the bus and the resonant cavity in the manufacturing process of the flip chip can be effectively avoided by the mode of out-of-plane coupling.

And the resonant cavity and the bus are coupled in different planes and are respectively and independently configured on an upper chip and a lower chip in the flip chip, so that the bus can be correspondingly manufactured on one chip, and the risk of wire breakage is greatly reduced.

Through the coupling structure, the advantages introduced in the flip chip bonding quantum chip can ensure that the bus is convenient to manufacture and is not easy to break, and each resonant cavity is independently coupled with the bus and is not easy to interfere with each other. These results in easier implementation of the measurement of qubits in a quantum chip via a bus and an increased effectiveness of the read operation.

According to some examples of the present application, the coupling structure further includes a stiffener bonded to the flip-chip interconnect and connected to the first surface or the second surface;

alternatively, the coupling structure further includes a first stiffener bonded to the flip-chip interconnect and connected to the first surface and a second stiffener bonded to the flip-chip interconnect and connected to the second surface.

According to some examples of the present application, the flip-chip interconnect has a side wall, the reinforcement member is a ring-shaped member having an inner bore defined by an inner surface;

the ring is seated on the flip-chip interconnect through the inner bore and the inner surface contacts the sidewalls of the flip-chip interconnect.

According to some examples of the application, the material of the ring-shaped element comprises titanium nitride.

According to some examples of the present application, the coupler includes a capacitor;

alternatively, the number of flip-chip interconnects is plural;

alternatively, the coupling structure further comprises a plurality of support posts arranged in a ring around the flip-chip interconnect.

According to some examples of the present application, the flip-chip interconnects are three in number and spaced a predetermined distance from each other; alternatively, the coupler is a capacitor having a capacitance of 5 fF.

In a second aspect, the present application proposes a quantum chip comprising a substrate having first and second surfaces that are out-of-plane, a qubit and the aforementioned coupling structure, the qubit being coupled to a resonant cavity in the coupling structure.

In a third aspect, the present application provides a flip-chip quantum chip fabricated using the aforementioned coupling structure.

This flip-chip bonding quantum chip includes:

providing a first chip with a first surface, wherein a coupler, a resonant cavity and a qubit are configured on the first surface, and the resonant cavity is respectively connected with the coupler and coupled with the qubit;

a second chip provided with a second surface, the second chip being opposed to the first chip, the second surface being provided with a bus line; and

a flip-chip interconnect between the first chip and the second chip, the flip-chip interconnect having one end connected to the bus match signal and another end connected to the coupler match signal.

According to some examples of the present application, a flip-chip interconnect includes first and second coaxial and non-contacting posts, the first post further connected with a coupler match signal and the second post further connected with a bus match signal.

According to some examples of the present application, a flip-chip interconnect includes first and second coaxial indium posts, the first indium post further connected to a coupler mating signal, the second indium post further connected to a bus mating signal, and the first indium post having a first indium oxide end face axially distal from the coupler, the second indium post having a second indium oxide end face axially distal from the bus, the first indium oxide end face and the second indium oxide end face being adjacent and having a gap.

Has the advantages that:

compared with the prior art, in the coupling structure of the application example, the bus and the resonant cavity are configured to be out-of-plane, and out-of-plane coupling with the coupler is realized. When the scheme is applied to flip chip bonding quantum chips, the bus can be independently configured on one layer of chip without passing and routing back and forth between an upper layer of chip and a lower layer of chip, so that the manufacturing difficulty of the bus is reduced, and the yield of the bus is improved. And, because the bus and the resonant cavity are coupled in different planes, a plurality of resonant cavities independent of each other can be configured, thereby allowing the other resonant cavities to be used continuously through the bus without being hindered in case of failure of one or more resonant cavities, such as reading operation of the qubit.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the prior art of the present application, the drawings used in the description of the embodiments or the prior art will be briefly described below.

Fig. 1 is a schematic diagram illustrating a coupling manner of a coupling structure according to an embodiment of the present disclosure;

fig. 2 discloses a schematic structural diagram of a first flip-chip quantum chip manufactured based on the coupling method shown in fig. 1 in an embodiment of the present application;

fig. 3 discloses a schematic layout structure diagram of a multi-bit flip chip fabricated based on the coupling method shown in fig. 1 in an embodiment of the present application;

fig. 4 discloses a schematic structural diagram of a second flip-chip quantum chip manufactured based on the coupling method shown in fig. 1 in an embodiment of the present application;

fig. 5 discloses a structural schematic diagram of a third flip-chip bonded quantum chip manufactured based on the coupling manner shown in fig. 1 in the embodiment of the present application.

Icon: 100-coupled structures; 101-a first surface; 102-a second surface; 103-a bus; 104-flip-chip interconnects; 105-a resonant cavity; 106-a coupler; 200-flip chip bonding of quantum chips; 201-a first chip; 202-a second chip; 203-a second stiffener; 204-support column; 205-a first indium column; 206-a second indium column; 207-a capacitor; 208-a first connector; 209-second connector.

Detailed Description

To the best of the inventor's knowledge, the resonant cavity and bus (referred to as the read bus) of coupling in flip-chip quantum chips currently employ a coplanar coupling scheme. I.e., the resonator and the bus are on the same side at the coupling location, e.g., the resonator and the bus are on the same layer of the chip at the coupling location.

Meanwhile, in order to arrange various lines, most areas of the resonant cavity and the bus are selected to be configured in a different surface mode. Therefore, the bus is selected to be disposed between two layers of chips in an up-and-down insertion manner. Whereby the bus is divided into a first part and a second part. Wherein the first part of the bus is wired in an upper chip in the flip chip and distributed and coupled in the same plane as the resonant cavity. Meanwhile, the second part of the bus is arranged on the lower layer chip wiring in the flip chip and is opposite to the resonant cavity. In order to connect the first part and the second part of the bus, a structure such as an indium column is required to be arranged between the first layer chip and the second layer chip, and two ends of the indium column are respectively connected with the first part and the second part of the bus in a signal mode.

Since the upper and lower chips in the flip chip need to be aligned in order to positionally match the indium columns with the bus lines on the upper and lower chip portions. Wherein the alignment can be implemented by respectively arranging alignment marks on the upper and lower layers of the flip chip. However, in the manufacturing process of the flip chip, after etching, peeling and other processes, the edge of the alignment mark may become blurred, so that the flip chip welder cannot accurately determine the edge of the alignment mark, and the upper and lower chips are aligned to generate a deviation, which causes the upper and lower chips to be misaligned, and further may cause a short circuit or an open circuit of a circuit, for example, the bus having the first portion and the second portion is open, and further affects reading status information of a qubit through the resonant cavity.

In view of the above, the inventors have made practical and research efforts to provide a solution to overcome the above-mentioned dilemma.

In general, the inventors believe that to ameliorate, or even solve, the above-mentioned problems, the buses and the resonator can be out-of-plane coupled, and in this out-of-plane coupling scheme, the buses do not need to be routed back and forth between the upper and lower chips. That is, the buses are entirely located on one layer of chips, and the resonators are entirely located on the other layer of chips.

Also, in the above-described out-of-plane coupling scheme, the resonant cavity can be coupled to the qubit by coupling the bus to the coupler with a matching signal using an appropriate connection structure (which will be referred to and described again with flip-chip interconnects later), and then coupling the coupler to the resonant cavity (which is coplanar with the resonant cavity).

Although in the above-described solution of the present application, there is also a connection structure connecting the upper and lower chips. However, since the bus does not need to be vertically inserted and wired, the bus is fabricated on one surface when the manufacturing process is performed, and thus the risk of disconnection is greatly reduced. In other words, the existing bus structure with different-surface distribution needs signal connection through indium columns, and the connection of the indium columns needs to consider factors such as alignment and pressing force, which results in relatively low yield of the bus and high manufacturing difficulty. The bus in the example of the application can be constructed in a layer of chips in a non-different-surface form, so that the bus can be directly and conveniently manufactured through mature processes in integrated circuits such as printing, deposition, photoetching and the like, and the manufacturing difficulty and yield of the bus are reduced.

In addition, since the bus is fabricated in one layer, there is a low risk of bus opens due to fabrication under typical process conditions in the current industry. And even if the manufactured bus is broken, the bus can be conveniently and quickly judged/detected/identified at room temperature. For example, the probe station is used to measure the resistance between two pads of a bus, and then the bus can be roughly determined whether the bus is open according to the resistance value. It is worth pointing out that the quantum chip with smaller resistance obtained in the operation of measuring the resistance of the bus can be preferentially selected to be used in the process of testing the manufactured quantum chip, so as to save the test time of the refrigerator and save the cost. This is because the lower the resistance of the tested bus, the lower the chance that it will open circuit.

When a plurality of quantum bits are arranged in a quantum chip and a plurality of resonant cavities are configured to read the quantum chip, the existing bus vertical insertion scheme has the condition that the connection of one bus fails, and the whole bus cannot be used or cannot transmit signals. However, the connection failure of one connection structure in the exemplary embodiment of the present application does not result in the matching signal connection of the other non-connection-failed connection structure and the resonant cavity at the corresponding position. That is, in the exemplary embodiment of the present application, a part of the connection structure is disabled, and the bus can be used continuously, i.e., the signal can be transmitted continuously.

Based on the above description, referring to fig. 1 to fig. 5, the inventor proposes a coupling structure 100, which can be applied to a quantum chip. More specifically, the quantum chip as an example may be a flip-chip superconducting quantum chip.

The quantum chip provides an out-of-plane first surface 101 and a second surface 102 corresponding to the out-of-plane coupling of the bus 103 and the resonant cavity 105. The quantum chip is also provided with quantum bits at proper positions; suitable locations therein may be the first surface 101 or the second surface 102 or other locations of the chip. The components in the coupling structure 100 may need to be suitably adapted according to the actual distribution of qubits at the first surface 101 or the second surface 102.

In general, the coupling structure 100 includes a resonant cavity 105, a coupler 106, a bus 103, and flip-chip interconnects 104, and the coupling and connection relationships between the resonant cavity, the coupler 106, and the bus are shown in fig. 1. Wherein a coupler 106, which is connected to the resonant cavity 105, is in signal communication with the bus 103 via the flip-chip interconnect 104 to effect coupling of the bus 103 and the resonant cavity 105. The flip-chip interconnect 104 is signal-mated with the bus 103 by one end and with the coupler 106 by the other end. Illustratively, a connector (a first connector 208, which can transmit electrical signals) is configured between one end of the flip-chip interconnect 104 and the bus 103 for signal connection; accordingly, another connector (a second connector 209, which can transfer an electrical signal) is disposed between the other end of the flip-chip interconnect 104 and the coupler 106 for signal connection.

That is, the bus connects the first connector 208, and the first connector 208 is also in signal communication with one end of the flip interconnect; while the other end of the flip-chip interconnect is in signal communication with the second connector 209, while the second connector 209 is also connected to one end of the coupler. Furthermore, the other end of the coupler is connected with one end of the resonant cavity, and the other end of the resonant cavity is coupled with the qubit.

Based on the different-plane coupling mode of the present exemplary embodiment, the resonant cavity 105 and the bus 103 are configured in different planes. Wherein the bus 103 is located at the second surface 102 and the cavity 105 is located at the first surface 101. Also, a coupler 106 is disposed on the first surface 101 and connected to one end of the resonant cavity 105. While the other end of the resonant cavity 105 is coupled to a qubit.

The resonant cavity 105 may be generally configured in a coplanar waveguide configuration. For example, the resonant cavity 105 is selected to be a resonant cavity in the form of a superconducting coplanar waveguide having advantages of high sensitivity, high integration, and outstanding detection efficiency. It can be selected in two forms of a quarter wavelength type and a half wavelength type as needed. The resonant cavity 105 in this form can be used for reading the quantum bit, and a plurality of resonant cavities 105 can be arranged on the bus 103 in a matching manner, so that the configuration of multiple quantum bits is facilitated, the structure of a quantum chip is simplified, and the wiring difficulty is reduced. The manufacturing method is, for example, various means in the micro-nano manufacturing technology, for example, by depositing a thin film (superconducting material, such as aluminum) on the surface of a cleaned substrate (such as high-resistance silicon), and then by fabricating a layer of a design layout through a photolithography process, etc.

The bus 103 may take the form of various transmission line types known in the art, typically selected as microstrip lines, coplanar waveguide lines, and the like. Coupler 106 may then be selected as a capacitive reactance element, such as a capacitor. The implementation of the capacitor can be interdigital capacitance, plate capacitance, etc. A specific and optional example of the coupler is a capacitor with a capacitance of 5fF (see the enlarged partial view in fig. 3 for the structure of the capacitor 207).

The flip-chip interconnects 104 may alternatively be fabricated using conductive materials, which may be used to signal couple the couplers 106 to the bus 103. In superconducting quantum chips, the flip-chip interconnects 104 may be selected to be a superconducting material, such as indium and thus the flip-chip interconnects 104 are configured as indium pillars. The specific structure and size of the indium columns are configured according to actual design parameters. Illustratively, the indium columns may be cylinders, and the height and the bottom surface diameter of the indium columns may be configured as required.

On this basis, an example can provide such a quantum chip, which includes a substrate. The substrate has a first surface 101 and a second surface 102, and the two surfaces are disposed on different areas of the substrate and are non-planar with respect to each other. The quantum chips are configured with different numbers of qubits according to their different functional and design requirements. When a plurality of qubits exist, the matching relationship between the qubits and the layout form on the substrate may be, for example, a one-dimensional chain layout, or a side-by-side multi-column layout, or an array layout. As an application example of the above-described coupling structure 100, the coupling structure 100 is provided to a substrate of the above-described quantum chip. And the resonant cavity 105 in the coupling structure 100 is coupled to the qubit therein.

As another example, the above-described coupling structure 100 is applied to a flip-chip bonded quantum chip 200 based on a flip-chip interconnection technology; an exemplary flip-chip quantum chip 200 structure is shown in fig. 2. The flip-chip quantum chip 200 includes a first chip 201 (or upper chip) and a second chip 202 (lower chip) which are oppositely disposed in a stacked manner. Various functional structures, lines, and devices are disposed on the surfaces of the first chip 201 and the second chip 202 facing each other.

Wherein the first chip 201 has a first surface 101 and the second chip 202 has a second surface 102. In the flip chip 200, the first surface 101 and the second surface 102 are arranged in a face-to-face manner. Further, the first chip 201 is configured with qubits on the first surface 101 and is coupled to the resonant cavity 105 in the coupling structure 100, and the resonant cavity 105 is connected to the coupler 106 in the coupling structure 100. Accordingly, the qubit, the resonant cavity 105 and the coupler 106 are respectively arranged to the first surface 101 of the first chip 201, and the resonant cavity 105 is coupled with the qubit and is connected with the coupler 106. The bus 103 in the coupling structure 100 is then arranged to the second surface 102 of the second chip 202.

As a support and connection structure between the first chip 201 and the second chip 202 in the flip chip 200, both ends of the flip interconnection 104 are respectively mated with the upper chip and the lower chip. And in the example, one end of the flip-chip interconnect 104 is in signal-matched connection with the bus 103 and the other end is in signal-matched connection with the coupler 106.

The number of flip-chip interconnects 104 may be selected as needed and is not particularly limited. For example, the number of flip-chip interconnects 104 may be one or two, three, or even more, i.e., the number of flip-chip interconnects 104 is at least one, at any one resonant cavity and bus coupling location. In the structure shown in fig. 2, at one coupling position, the flip-chip interconnections 104 are three in number and are arranged in sequence at intervals in a line structure. When there are multiple flip-chip interconnects 104, these flip-chip interconnects 104 follow the trace traces of the bus 103. When there are multiple resonators coupled to the bus, there are multiple coupling locations, and thus, each coupling location can be configured with a corresponding number of flip-chip interconnects as desired.

At any coupling location, the plurality of flip-chip interconnects 104 may provide more contact area, thereby helping to improve the connection effectiveness and robustness of the flip-chip interconnects 104 at the upper and lower connections, and also helping to increase the coupling area between the first chip 201 and the second chip 202. In the foregoing description, the configuration of the indium columns is matched to the resonator 105 and the bus 103. Thus, the indium columns correspond to the coupling positions of the resonators 105 and the bus lines 103. I.e., at the coupling position of the resonant cavity 105 and the bus 103, an indium column is correspondingly configured. When there are a plurality of coupling positions, there are a plurality of setting positions of the indium columns accordingly.

It is worth noting, then, that the number of indium columns is advantageously uniform at each indium column placement position. Because this can make flip-chip bonding machine when pressfitting first chip 201 and second chip 202, the pressure that produces more tends to unanimity to make the difficult warpage that takes place of upper and lower layer chip consequently, can avoid causing the problem that the conductivity of indium post can not guarantee to take place because the warpage is big.

As previously described, the number of flip-chip interconnects 104 may be matched to the number of coupling locations of the resonant cavity 105 and qubit, e.g., one-to-one correspondence. In other words, the lower upper chip is supported between the first chip 201 and the second chip 202, and the structural member connecting the bus 103 and the coupler 106 may be one or more. In some examples, the structure includes flip-chip interconnects 104 and support posts 204, and the number of flip-chip interconnects 104 and support posts 204 can be selectively configured independently. When there are multiple support posts 204 at/near each coupling location corresponding to the flip-chip interconnect 104 at that location, the support posts 204 can be configured to be disposed around the flip-chip interconnect 104. For example, when one flip-chip interconnect 104 is correspondingly disposed near any one of the coupling positions, a plurality of flip-chip interconnects 104 may surround the flip-chip interconnect 104. Meanwhile, when there are multiple (e.g., three) flip-chip interconnects 104 at the aforementioned coupling location, then the support posts 204 at that location can surround the respective flip-chip interconnects 104 at that location. For example, as shown in the enlarged view of fig. 3, three flip-chip interconnects 104 arranged in a row (spaced apart from each other by a distance that can be selectively adjusted according to the actual application; as an alternative specific example, the pitch is 30 μm), and 7 support posts 204 arranged in a circle around the three flip-chip interconnects 104.

The support posts 204 may be made of the same material as the flip-chip interconnects 104, or other materials, so as to facilitate the fabrication of the first chip 201 and the second chip 202 in the meeting. In addition, each of the flip-chip interconnects 104 and the support posts 204 may optionally have an adhesive disposed on its surface to reinforce the connection, as described below.

In other examples of the present application, it may be selected to provide a structural entity in the coupling structure 100 that provides enhanced connection to the indium stud, based on considerations of improved robustness of connection between the two ends of the indium stud and the bus 103 and coupler 106. For example, coupling structure 100 includes a stiffener. The stiffener is bonded to the flip-chip interconnect 104 and is connected to either the first surface 101 or the second surface 102. In other words, the stiffener may be a component to improve the connection robustness at the connection location of either end of the flip-chip interconnect 104 to the chip.

It will be appreciated that in some examples, it may be advantageous to choose an increase in the degree of connection security for both ends of the flip-chip interconnect 104. Thus, in some such examples, the coupling structure 100 includes a first stiffener (not shown in fig. 4) and a second stiffener 203, see fig. 4. Wherein the first stiffener is bonded to the flip-chip interconnect 104 and connected to the first surface 101 of the first chip 201, and wherein the second stiffener 203 is bonded to the flip-chip interconnect 104 and connected to the second surface 102.

Each stiffener may be configured by coating or pouring an adhesive material (such as resin used in chip packaging) between the first chip 201 and the second chip 202; in some examples, the stiffener may be selected from titanium nitride.

In other examples, the reinforcement may be configured as an annular member of annular configuration, such as a titanium nitride ring. The reinforcement member is mated with flip-chip interconnects 104, etc., as follows: the disclosed flip-chip interconnect 104 has sidewalls, and the ring has an inner bore defined by an inner surface; thus, the ring is sleeved to the flip-chip interconnects 104 (in the example, the ends thereof) through the inner holes thereof, and the inner surfaces of the ring are in contact with the sidewalls of the flip-chip interconnects 104.

Further, the flip-chip interconnect 104 in the coupling structure 100 may be optionally constructed in a segmented manner in some examples based on considerations such as ease of fabrication of the flip-chip quantum chip 200.

For example, the flip-chip interconnect 104 includes a first pillar disposed on the first surface 101 of the first chip 201 and in signal-matched connection with the coupler 106 located on the surface, and a second pillar disposed on the second surface 102 of the second chip 202 and in signal-matched connection with the bus 103 located on the surface.

Thus, it can be appreciated that in flip-chip bonding of the quantum chip 200, the first and second pillars are aligned in a coaxial manner (with their axes in the same line), so that when the first and

second chips

201 and 202 are aligned and bonded by a flip-chip bonding machine, the first and second pillars can be accurately butted to form the flip-chip interconnect 104.

Further, when the flip-chip interconnects 104 are selected to use, for example, indium columns, the flip-chip interconnects 104 in the form of indium columns may also be configured in such a way that, in consideration of their oxidation characteristics and the accuracy of the bonding between the upper and lower chips: the flip-chip interconnect 104 includes coaxial first and second indium posts 205, 206, see fig. 5. Wherein the first indium posts 205 are in signal-matched connection with the couplers 106 and the second indium posts 206 are in signal-matched connection with the buses 103. Also, the first indium stud 205 has a first indium oxide end face (not labeled) axially remote from the coupler 106, while the second indium stud 206 has a second indium oxide end face axially remote from the bus bar 103. Thus, in the flip chip 200 of the above structural form, the first indium oxide end face and the second indium oxide end face are adjacent to each other with a gap (for example, on the order of micrometers).

When the flip chip 200 is fabricated, and the first indium stud 205 and the second indium stud 206 are not bonded in place, since the gap between the indium oxide end faces of the two is narrow, and a medium such as an air gap is formed between the gap layers, an unexpected introduced capacitor is formed (since the size of the gap is small, the capacitance value is large). And it is believed through analysis that this capacitance is difficult to fuse or cancel with other structures in flip chip 200, which can adversely affect the testing of qubits and thus create situations where bus 103 cannot be read through resonator 105. However, in the present exemplary embodiment, a coupler 106 in the form of a capacitor is used. Then, this problem can be well overcome based on such a capacitive coupling approach. This is because: the capacitance undesirably introduced in the exemplary embodiment of the present application and constituted by the end face of the indium column is connected in series with the capacitor (small capacitance value) as the coupler 106, so that a capacitance of a small capacitance value can be constituted. Since the capacitance value of the series formed capacitor is small, there is little effect on the coupling of the read cavity (provided by the resonant cavity 105) and the bus 103. Therefore, the different-surface capacitive coupling mode of the resonant cavity 105 and the bus 103 enables simulated data to be closer to data in test and enables parameters of the read cavity to be acquired more easily. That is, the capacitor type coupler 106 can cancel the capacitance caused by the non-pressed position, so that the resonant cavity 105 and the qubit can be more easily regulated and simulated.

Therefore, the solution of the capacitor-type coupler 106 in the present example can reduce the operation difficulty of the pressing process in the flip chip 200 manufacturing process. Or, in the case of the coupler 106 in the form of the aforementioned capacitor, and the configuration design of the coupling structure 100 is performed accordingly, when the end face of the first indium stud 205 and the end face of the second indium stud 206 form capacitance due to non-contact during the bonding of the upper and lower chips of the flip chip, the capacitor provided in the coupling structure 100 can also counteract the aforementioned capacitance that is accidentally introduced, and thus the operation of measuring the resonant cavity 105 through the bus line 103 and the like is not hindered.

The coupling structure 100 and the quantum chip based thereon in the present disclosure have been described in detail so far. And based on these descriptions, the exemplary embodiments of the present application have at least the following advantages:

(1) the bus 103 is placed on a layer of chips without interleaving up and down. Thus, where multiple resonators 105 are provided, each resonator 105 is relatively independent of the other, and the absence of a single resonator 105 does not affect the testing of the next resonator 105.

(2) The upper chip and the lower chip are connected by adopting a plurality of indium columns corresponding to the coupling parts of the buses 103 and the resonant cavity 105, and a plurality of supported indium columns are arranged around the indium columns, so that the contact area of the indium columns can be increased, and the phenomenon of non-connection is prevented.

(3) A capacitor such as 5fF is added at the coupling position of the resonant cavity 105 in the layer opposite to the bus 103, so that the capacitance caused by the defect when the upper and lower chips are laminated can be offset, and the resonant cavity 105 and the bit can be more easily regulated and simulated.

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application are described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solutions claimed in the present application can be implemented without these technical details and various changes and modifications based on the embodiments. The embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be mutually incorporated and referred to each other without contradiction.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.

Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In addition, the terms "upper", "lower", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, or orientations or positional relationships conventionally placed when products of the application are used, or orientations or positional relationships conventionally understood by those skilled in the art, which are merely for convenience of description and simplification of description, but do not indicate or imply that the devices or elements referred to must have specific orientations, be constructed in specific orientations, and be operated, and therefore, should not be construed as limiting the application.

The construction, features and functions of the present application are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present application, but the present application is not limited by the drawings, and all equivalent embodiments that can be modified or changed according to the idea of the present application are within the scope of the present application without departing from the spirit of the present application.

Claims

1. A coupling structure for a quantum chip having a qubit and first and second non-planar surfaces, the coupling structure comprising:

a resonant cavity disposed at the first surface, the resonant cavity having a first end and a second end, wherein the first end is configured to couple with the qubit;

a bus disposed on the second surface; and

a flip-chip interconnect having two ends, one of the two ends being in signal connection with the bus match and the other end being in signal connection with the coupler match.

2. The coupling structure according to claim 1,

the coupling structure further includes a stiffener bonded to the flip-chip interconnect and connected to the first surface or the second surface;

3. The coupling structure of claim 2, wherein the flip-chip interconnect has a side wall, the reinforcement is a ring having an inner bore defined by an inner surface;

the ring member is sleeved to the flip-chip interconnect through the inner hole, and the inner surface is in contact with a sidewall of the flip-chip interconnect.

4. The coupling structure of claim 3, wherein the ring-shaped member comprises titanium nitride.

5. The coupling structure according to any one of claims 1 to 4, wherein the coupler comprises a capacitor;

alternatively, the number of flip-chip interconnects is plural;

6. The coupling structure according to any one of claims 1 to 4, wherein the flip-chip interconnections are three in number and spaced from each other by a predetermined distance;

and/or the coupler comprises a capacitor with a capacitance value of 5 fF.

7. A quantum chip, comprising:

a substrate having first and second surfaces that are out-of-plane:

a coupling structure according to any one of claims 1 to 6 provided on the substrate; and

a qubit disposed on the substrate, the qubit coupled to a resonant cavity in the coupling structure.

8. A flip-chip quantum chip fabricated using the coupling structure of any one of claims 1 to 6, the flip-chip quantum chip comprising:

providing a first chip with a first surface, wherein the coupler, the resonant cavity and the qubit are configured on the first surface, and the resonant cavity is respectively connected with the coupler and coupled with the qubit;

a second chip provided with a second surface, the second chip being disposed opposite to the first chip, the bus lines being disposed on the second surface; and

the flip-chip interconnect between the first chip and the second chip having one end connected with the bus match signal and another end connected with the coupler match signal.

9. The flip-chip quantum chip of claim 8, wherein the flip-chip interconnect comprises first and second coaxial and non-contacting posts, the first post further connected with the coupler match signal and the second post further connected with the bus match signal.

10. The flip chip bonded quantum chip of claim 8 wherein the flip chip interconnect comprises first and second coaxial indium posts, the first indium post further connected to the coupler match signal and the second indium post further connected to the bus match signal, and the first indium post has a first indium oxide end face axially distal from the coupler, the second indium post has a second indium oxide end face axially distal from the bus, the first and second indium oxide end faces being adjacent and having a gap.