CN115425010A

CN115425010A - Through-silicon-via test circuit and flip chip

Info

Publication number: CN115425010A
Application number: CN202210974718.5A
Authority: CN
Inventors: 姚文洋; 李业; 李松
Original assignee: Origin Quantum Computing Technology Co Ltd
Current assignee: Origin Quantum Computing Technology Co Ltd
Priority date: 2022-08-15
Filing date: 2022-08-15
Publication date: 2022-12-02

Abstract

The application discloses through silicon via test circuit belongs to quantum chip and makes the field. The test circuit includes a first conductive line and first and second measurement lines each having separate measurement portions. The first and second measurement lines are electrically connected with the first wire through a through silicon via interconnection and a flip chip interconnection respectively. The test circuit can be used to make and break tests on both flip-chip interconnects and through-silicon-via interconnects.

Description

Through-silicon-via test circuit and flip chip

Technical Field

The application belongs to the field of quantum chip manufacturing, and particularly relates to a through silicon via test circuit and a flip chip.

Background

With the continuous iterative development of the technology in the field of quantum computing, the number of quantum bits is gradually increased. For a conventional quantum chip with a relatively small number of qubits, a flip-chip structure of a dual-layer chip may suffice. However, flip chip bonding has been elusive for quantum chips of hundreds or even more qubits. At this time, the use of a Through-Silicon-Via (TSV) process is very important.

However, the through-silicon via process currently applied to the quantum chip is not mature, so that the stability of the manufactured quantum chip is not high. Then after the quantum chip is fabricated, a corresponding test structure is needed to examine the success rate of the through-silicon-via process. In particular, in Flip chip, signals are usually transmitted from a lower layer to an upper layer (referred to as Flip layer) through Flip pads, and then transmitted to the other side of the Flip layer through silicon vias. In this process, the make and break of the flip chip solder and the through silicon via are the most critical.

The existing test operation is to independently test each layer of chips between flip chip interconnections, and the requirements of on-off test of flip chip welding points and through silicon vias after packaging are difficult to meet. A solution that can detect whether both are open after flip-chip interconnection is highly desirable.

Disclosure of Invention

In view of the above, the present application discloses a through silicon via test circuit and a flip chip, by which an interconnect structure and a through silicon via structure in the flip chip can be tested together, so that the test circuit can be used to verify the manufacturing process conditions of the interconnect structure and the through silicon via structure in the flip chip.

The scheme exemplified in the present application is implemented as follows.

A through silicon via test circuit includes:

a first wire having a first end and a second end;

a first measurement line electrically connected to the first end through a through silicon via interconnect; and a second measurement line electrically connected to the second end through a flip-chip interconnect independent of the through-silicon via interconnect;

each of which has two separate measuring sections.

In the test circuit, the flip-chip interconnection is used for realizing interconnection of lines and elements among chips of different layers in the flip chip; the through silicon via interconnection is used for interconnecting lines and elements distributed on different surfaces of a single-layer chip. Thus, the test circuit in the present example can be used to test flip-chip interconnect chips using through silicon via technology. The through-silicon-via interconnects and the flip-chip interconnects are electrically connected to the first wires, respectively, so that the interconnects can be tested through the measurement lines connected to the interconnects. Since the measuring line has a separated measuring part, the two-end measuring operation can be realized according to the selection of the measuring part, so that the on-off condition of the silicon through hole interconnection and the flip interconnection can be obtained, and the resistance condition of the silicon through hole interconnection and the flip interconnection can be obtained through the four-end measuring operation. The selected items of the through-silicon-via interconnection and the flip-chip interconnection can be tested together based on the test circuit, so that the problems of complicated test structure caused by independent test schemes for the through-silicon-via interconnection or the flip-chip interconnection and the existing independent test structure aiming at each independent chip before flip-chip interconnection can be avoided.

According to some examples of the present application, the flip-chip interconnect is a pillar structure; and/or the flip-chip interconnect is a superconducting material.

According to some examples of the present application, the flip-chip interconnect is an indium stud and has coaxial first and second stud segments, the first stud segment being connected to the second end of the first wire and the second stud segment being connected to the second measurement line.

According to some examples of the present application, the through-silicon via interconnects are hollow pillars or solid pillars.

According to some examples of the present application, the test circuit includes a plurality of second measurement lines, each connected with the wire by a separate flip-chip interconnect.

According to some examples of the application, the plurality of second measurement lines is two second measurement lines.

According to some examples of the present application, the first wire, the first measurement line, and the second measurement line together comprise a measurement assembly;

the test circuit comprises at least two measuring assemblies, wherein two adjacent measuring assemblies are electrically connected in series, and two ends of the series connection are respectively positioned on the through silicon via interconnection pieces.

According to some examples of the present application, the electrical series connection is implemented by connecting two ends of the series line to respective through-silicon via interconnects.

According to some examples of the present application, the series line includes at least one series interconnection configured by through-silicon vias, and the plurality of second conductive lines are connected in series by the at least one series interconnection.

According to some examples of the application, the two ends of the series line are arranged out of plane; and/or the serial interconnection and the through silicon via interconnection have the same structure; and/or the serial interconnection and the through silicon via interconnection are made of the same material.

In a second aspect, examples of the present application propose a flip chip. Which has first and second opposing chips and further includes through-silicon-via test circuitry. The first lead and the first measuring line are arranged on the first chip, and the second measuring line is arranged on the second chip; the through silicon via interconnection is arranged on the first chip in a penetrating way; the flip-chip interconnection is configured between the first chip and the second chip.

According to some examples of the application, the second chip has a surface facing the first chip, the surface comprising an inner region and an outer region, the outer region surrounding the inner region, an orthographic projection of the first chip on the second chip being within the inner region or an outline of the orthographic projection of the first chip on the second chip coinciding with an outline of the inner region; the measuring part of the second measuring line is arranged in the outer layer area.

According to some examples of the application, the first conductor is a superconducting wire, or the first conductor is a coplanar waveguide.

Has the advantages that:

in contrast to the prior art, the test circuit of the present example is provided to enable testing of flip chips using through silicon via technology. Specifically, in the flip chip, lines and elements on different surfaces of different layers or chips on the same layer are connected by an interconnect structure to form a test signal path. Testing based on these signal paths can be accomplished using the aforementioned test circuitry and thus measurements can be made of the connectivity of the interconnect structure or electrical properties such as resistance.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the prior art of the present application, the drawings used in the description of the embodiments or the prior art will be briefly described below.

Fig. 1 is a schematic structural diagram of a flip chip using TSVs according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another flip chip using TSVs according to an embodiment of the present disclosure;

FIG. 3 shows a schematic view of the flip chip of FIG. 2 in an axial direction;

fig. 4 is a schematic structural diagram of another flip chip applying TSVs according to an embodiment of the present disclosure;

FIG. 5 shows a schematic cross-sectional view of the flip chip of FIG. 4 in an axial direction;

FIG. 6 discloses a schematic structure diagram of a test circuit in an example of the present application;

FIG. 7 discloses a schematic diagram of another test circuit in an example of the present application;

fig. 8 is a schematic diagram of a flip chip based on the test circuit shown in fig. 7 in two viewing directions.

An icon: 101-a first chip; 102-a second chip; 103-through silicon via interconnect; 104-flip-chip interconnects; 201-a first measurement line; 202-a first conductive line; 203-a second measurement line; 204-a measuring part; 301-a measurement component; 302-a second wire; 303-series interconnection.

Detailed Description

Fig. 1 discloses a schematic structural diagram of a three-dimensional packaged flip chip. From the foregoing figures, it can be appreciated that the flip chip of this example includes two layers of chips, and the corresponding configuration of the interconnect structure. Wherein the two layers of chips, the first chip 101 and the second chip 102, are stacked. Of course, in other examples, the number of stacked chips in the flip chip may be more (e.g., three, four, five, or even more), rather than being limited to a two-layer stack of two chips. For flip chips with a greater number of chips, the chips may be configured in a layer-by-layer stack.

The chip is used for signal intercommunication of different components and circuits in different layers of chips and the same layer of chips. Through-silicon via interconnects 103 may be disposed as desired in each layer of the chip, and flip-chip interconnects 104 may be disposed between different adjacent layers. Note that in the present example, through-silicon via interconnects 103 refer to interconnects within through-chip upper and lower surface vias in a/layer chip; i.e., through-silicon via interconnects 103, are used to enable communication of components and lines within the layers. It is noted that the through-silicon via interconnection 103 is not limited in this application to having to be configured to a substrate of silicon material, but may be, for example, a sapphire substrate. The flip-chip interconnects 104 are interconnects disposed between two adjacent layers of chips, so that the facing surfaces of the two layers of chips or the components thereon are in signal communication; that is, the flip-chip interconnects 104 are used to communicate components and lines between layers.

In the flip chip shown in fig. 1, the through-silicon via interconnects 103 and the flip chip interconnects 104 of two adjacent layers are opposed to each other in the layer stacking direction (or thickness direction or Z direction) of the chip. In other examples, the through-silicon via interconnect 103 and the flip-chip interconnect 104 may also be at a distance from each other to facilitate the routing of signal lines; such as shown in fig. 2. Fig. 3 discloses a schematic structure of a local area of the flip chip of fig. 2 in an axial direction.

In the flip chip configured by the two-layer chip of fig. 1 to 3, the upper and lower layers of the chip have a substantially equivalent profile. As an alternative example, in the flip chip of the two-layer chip shown in fig. 4, the chips of the upper and lower layers have different outline sizes. For example, the first chip 101 on the upper layer has a smaller profile than the second chip 102 on the lower layer.

In other words, two regions, namely an inner region and an outer region, can be defined on the surface of the second chip 102 facing the first chip 101; and as the name implies, the outer region surrounds the inner region. Then, for the different examples of the profile sizes of the upper and lower chips, it can be stated that the orthographic projection of the first chip 101 on the second chip 102 is located within the inner layer area — the profile sizes are different; alternatively, the outline of the orthographic projection of the first chip 101 on the second chip 102 coincides with the outline of the inner layer area — the outline size is the same.

When the first chip 101 and the second chip 102 are configured in different outline sizes, the lower chip may be configured with pads of various circuits and components in the outer layer, so as to be conveniently connected to other devices by wire bonding, and a space capable of being configured sufficiently and freely is reserved for various components and circuits arranged in the inner layer area, thereby reducing the design difficulty and the manufacturing difficulty of the chips.

In the flip chip described above, the through-silicon via interconnection 103 and the flip chip interconnection 104 can be made of various suitable materials, and are not particularly limited. Generally, the fabrication materials of both can be selected to be metallic materials, such as gold, copper, etc., depending on the type of flip chip and the usage scenario. In the context of superconducting quantum chips, the flip-chip interconnects 104 and through-silicon-via interconnects 103 may be selected to be materials capable of exhibiting superconducting properties at the operating temperature of the chip, e.g., milli-kelvin (mk), such as indium, niobium, etc., and may correspond to indium or niobium pillars. Also, the flip-chip interconnects 104 and the through-silicon via interconnects 103 may be the same material or made of different materials.

In shape, the flip-chip interconnects 104 may be configured as columnar structures; or in other examples, the flip-chip interconnects 104 may be ball or bump structures. The through-silicon via interconnect 103 is typically configured as a pillar structure since it requires a single chip with a certain thickness to pass through/through (which may partially protrude out of the surface of the chip). Further, the pillar structured flip-chip interconnects 104 withstand the pressure of the upper and lower chips, and therefore, are generally configured as solid pillar structures to provide the required structural strength. The through-silicon via interconnects 103 may be selected to be solid or hollow pillars. Particularly in view of ease of fabrication and stability of connections to various circuits and components. The flip-chip interconnect 104 may optionally be fabricated in segments. For example, the flip-chip interconnect 104 is comprised of a first post segment and a second post segment that are coaxial (i.e., the axes of both are in the same line). Wherein the first pillar segment is configured to the first chip 101 and connected to a line or device at the first chip 101; the second segment is disposed to the second chip 102 and connected to a line or device at the second chip 102. And in flip-chip interconnection, the ends/free ends of the two pillar segments remote from the chip are contacted and joined to form a pillar-like flip-chip interconnection. In this manner, when the flip-chip interconnects 104 are formed by flip-chip interconnecting the first chip 101 and the second chip 102, the stability of connection between both ends of the formed flip-chip interconnects 104 and the lines or devices distributed on the respective surfaces of the two layers of chips is maintained. If the flip-chip interconnect 104 is configured to a chip before flip-chip interconnection, and then another end of the interconnect is bonded to another chip during flip-chip interconnection, there may be a problem that the other end is connected to the other chip with poor firmness of the circuit and the component.

As for the fabrication process, the flip-chip interconnects 104 can be fabricated by photolithography, etching, lift-off, etc., while the through-silicon-via interconnects 103 can be fabricated by plating. Those skilled in the art can selectively fabricate the optical film according to the existing process, which is not described in detail in this application.

Since the fabrication of the flip chip composed of multiple layers, such as two layers, may involve complicated process steps and the obtainment of various materials, in order to control the quality of the fabricated flip chip, or verify, develop a new flip chip layout structure and fabrication process, and reduce the fabrication cost, it is necessary to evaluate the fabrication quality of the flip interconnects 104 and the through silicon via interconnects 103, so as to avoid the waste of the previous-stage products (such as single-layer chips) of the flip chip in the subsequent operations, such as packaging, and the like, or to improve the performance of the fabricated flip chip.

To the best of the inventors' knowledge, current testing methods typically test the flip-chip interconnects 104 on and off and the through-silicon-via interconnects 103 on and off, respectively. In the process of manufacturing the flip chip applying the TSV technology, chips of different layers are tested respectively, and then the tested chips are subjected to flip interconnection. However, this solution only focuses on the quality of the flip-chip interconnects and the through-silicon via interconnects 103 before flip-chip interconnection, and it is difficult to achieve an effective measurement of the quality of the flip-chip interconnects 104 and the through-silicon via interconnects 103 after flip-chip interconnection. Even if the above-mentioned test method is adopted, it is necessary to configure corresponding test structures for the through-silicon via interconnection 103 and the flip-chip interconnection, respectively, which results in relatively more complicated test steps and complicated test structures. In short, the solution of testing both in combination, i.e. testing already fabricated flip chips applying TSVs, has no relevant success cases that can be relatively simply achieved.

In view of the above, in the examples of the present application, the inventors propose a through silicon via test circuit. It can be used to test the aforementioned TSV-based flip-chip to determine, for example, the on-off and resistance conditions of the through-silicon via interconnects 103 and the flip-chip interconnects 104 therein; in other examples, it is contemplated that measurements of items such as capacitance, insertion loss, quality factor, etc. may be made based on or appropriately modified from this test circuit. In the example, the test circuit has a first conductor 202, a first measurement line 201 and a second measurement line 203.

Wherein the first conductor 202 may act as a signal line, such as a transmission line in the form of a coplanar waveguide; alternatively, first conductor 202 may also function as a conductive line such as a superconducting line. The first conductor 202 is also of a suitable length for proper routing operations. And thus, the first conductive line 202 has a first end and a second end, and an extended trace path defined between the first end and the second end; the path may be of any desired form, such as a straight or broken line or a curved or circular shape, etc.

The aforementioned two ends of the first wire 202 are connected with the flip-chip interconnect 104 and the through-silicon via interconnect 103, respectively, thereby forming a test signal path; and it can also be seen that the flip-chip interconnect 104 and the through-silicon-via interconnect 103 are discrete, with a distance therebetween defined by the first conductive line 202. On this basis, for the case where the flip-chip interconnect 104 is configured by the first pillar section attached to the first chip 101 and the second pillar section attached to the second chip 102, respectively, as described above, the first pillar section is connected to the second end of the first conductive line 202, while the second pillar section is connected to the second measurement line 203.

In fig. 5, an exemplary test signal path is disclosed, a test signal may be input from the second measurement line 203, input to the first conductive line 202 through the flip-chip interconnect 104, and output from the first measurement line 201 through the through-silicon via interconnect 103; and vice versa. Further, in order to facilitate connection with the testing equipment, the measuring lines are respectively disposed with the measuring portions 204, and each of the measuring lines has two measuring portions 204 (not shown in fig. 5) separated from each other.

According to the signal path shown in fig. 5, the connectivity of the combination of the flip-chip interconnect 104 and the through-silicon via interconnect 103 in the loop can be measured by testing the loop formed by the measurement portion 204 selected by the first measurement line 201 and the second measurement line 203. That is, if the test result is that the loops are connected, it indicates that the flip-chip interconnect 104 and the through-silicon via interconnect 103 are connected, respectively. If the loop is open, one or both of the flip-chip interconnect 104 and the through-silicon via interconnect 103 are open.

Further, in order to be able to independently test the flip-chip interconnects 104 in addition to the above-mentioned test, in some examples, the test circuit may further configure more than one second measurement line 203, for example, including at least two second measurement lines 203, see fig. 6. And, the second measurement lines 203 are each connected to the first conductive lines 202 by a separate flip-chip interconnect 104. In other words, in general, a second measurement line 203 may be correspondingly configured with a flip-chip interconnection, and accordingly connected to the second end of the first conductive line 202.

In the test circuit configuration shown in fig. 6, each measurement line has two separate measurement portions 204 (which may be configured as pads, for example), and therefore, two second measurement lines 203 and one first measurement line 201 have 6 measurement portions 204 in total. In performing measurement, one of the two measurement portions 204 of any one measurement line may be configured as a voltage measurement point, and the other may be configured as a current measurement point; and two measurement portions 204 of the same measurement line are in a short-circuited state. The position of each bonding pad on the corresponding chip can be correspondingly selected and configured by measuring the length of the wire. For example, in the case that the size of the second chip 102 is larger than that of the first chip 101, the measurement portion 204 of the second measurement line 203 of the second chip 102 may be configured with an outer region thereof.

Based on the structure shown in fig. 6, measurement may be performed with two second measurement lines 203, respectively, or with the first measurement line 201 and any one of the second measurement lines 203. Exemplary selectable test items include two-terminal method for on-off measurement, and four-terminal method (or kelvin four-terminal method, four-point probe method, etc.) for resistance measurement. When performing the two-end method measurement, one of the two measurement units 204 of each of the two selected measurement lines is selected; one voltage measuring point is selected by one measuring line, and one voltage measuring point is selected by the other measuring line; or to select the current measurement points separately. In the case of four-end measurement, both the two measurement units 204 of each of the two arbitrarily selected measurement lines are used.

Due to the numerous lines and components in the chip, and the reasonable and efficient layout of these lines and components, numerous flip-chip interconnects 104 and through-silicon-via interconnects 103 are deployed in the chip. A test circuit that appropriately configures more measurement lines would be beneficial.

Based on this, it can be defined that the first conducting wire 202, the first measuring wire 201 and the second measuring wire 203 together constitute one measuring assembly 301. The test circuit may then comprise a measurement component 301, as described above. To test more interconnects, the test circuit may include at least two measurement assemblies 301. The measurement elements 301 may be electrically arranged in parallel, or electrically arranged in series, or each independently configured, i.e., without substantial electrical connection.

As an example of serial connection, for a test circuit having a plurality of measurement devices 301, two adjacent measurement devices 301 are electrically connected in series. The serial connection position may be connected through the first conductive line 202, i.e., the electrical serial connection position is at the first conductive line 202 of each measurement component 301. Alternatively, as shown in fig. 7, two ends of the electrical series are respectively located at the respective tsv interconnects 103 in two adjacent measurement devices 301. That is, electrical series connection is achieved by connecting the two ends of the series line to respective tsv interconnects 103.

The above-mentioned series circuit is an electrical component disposed between two measurement units 301, and therefore, in an example in which a plurality of measurement units 301 are electrically connected in series by a series circuit, the number of the series circuit is one less than the number of the measurement units 301.

In addition, both ends of any series line may be located on the same surface of the first chip 101, for example, both ends may be located on a surface (or a first surface) of the first chip 101 facing the second chip 102, or both ends may be located on a surface (or a second surface) of the first chip 101 facing away from the second chip 102.

Or in still other examples, the series lines are distributed on both the front side and the back side of the first chip 101. Namely on both the aforementioned first and second surfaces; from this it is known that the series line passes through the first chip 101.

Then to implement this scheme, a structure such as the through-silicon via interconnect 103 may be configured for the series line, depicted in the example as a series interconnect 303 (which may have the same material and structure and fabrication process as the through-silicon via interconnect structure). Thus, in the above example, the serial line may include the serial interconnect 303 (one or more/at least two) and the second wire 302 that is electrically connected through the serial interconnect 303.

Wherein the serial interconnection 303 penetrates through the first chip 101 and may protrude to the surface thereof; meanwhile, a part of the second conductive lines 302 in all the second conductive lines 302 are located on the first surface, and the rest part of the second conductive lines 302 are located on the second surface; that is, the plurality of second wires 302 are alternately arranged to the front surface and the back surface of the first chip 101.

As shown in fig. 7, three measuring units 301 of the area defined by the dashed line are disclosed, the scheme of concatenation being performed by two serial lines; and each of the series lines includes two second conductive lines 302 distributed in different planes, and the two second conductive lines 302 are connected by a series interconnection 303. The two measuring sections 204 of each measuring line are each indicated as follows in order to explain the measuring method in the following.

Wherein 1V-, 1I-, and 2V-, 2I-, and 3V-, and 3I-denote the types of the measuring points of the respective pads located on the first measuring line 201 of the first chip 101, V denotes a voltage measuring point, and I denotes a current measuring point. Similarly, 1V +, 1I +, 1V-, 1I-, and 2V +, 2I +, 2V-, 2I-, and 3V +, 3I +, 3V-, 3I-represent the measurement point types of the respective pads of the second measurement line 203 located in the second chip 102, V represents a voltage measurement point, and I represents a current measurement point. It should be noted that the measurement points marked in fig. 7 may also be other types of measurement points according to the requirements of other test items, that is, the present application does not limit the measurement portions to be only voltage measurement points and current measurement points.

Based on this, at least the following measurement types can be realized for the flip chip shown in fig. 8 using the respective measurement points shown in fig. 7.

Measurement mode 1:

1V + and 1I +, and 1V-and 1I-can be used to test the on-off of the indium column by the two-end method, and the indium column resistance by the four-wire method.

Measurement mode 2:

1V + and 1I +, and 1V-and 1I-can be used for testing the make-and-break of the indium columns and the TSVs by a two-end method, testing the combined resistance of the indium columns and the TSVs by a four-wire method, and combining a 1 st measurement mode: the on-off condition of the TSV can be judged.

Measurement mode 3:

the two TSV's were tested for make-and-break between 1V + and 1I +, and 2V + and 2I +. With reference to measurement mode 1: and 2, measurement mode: the on-off of the second TSV can be judged; the indium column resistance can also be tested by a four-wire method, and the measurement mode 1 is combined: and 2, measurement mode: the resistance of the second TSV can be tested.

Measurement mode 4:

the same way as the 3 rd measurement mode, the resistance and the on-off of a third TSV can be tested between 1V-and 1I-, and 2V-and 2I-; the resistance and the on-off of the fourth TSV can be tested between 2V + and 2I +, and between 3V + and 3I +; the resistance and make-and-break of the fifth TSV can be tested between 2V and 2I, and between 3V and 3I.

Measurement mode 5:

and rapidly positioning the position of the open TSV by using a bisection method. The on-off is measured between 1V + and 1I +, and NV-and NI- - (N stands for the Nth row pad/pad, only 3 are listed here). If not, the measurement is continued between 1V + and 1I +, and N/2V-and N/2I-. The TSV for which an open circuit has been detected by bisection; for multiple TSV opens, this method can also be used to detect.

Therefore, it can be seen from the above that various test modes can be implemented by the test circuit. The test structure and the test principle of the test circuit are simple; meanwhile, the test circuit does not occupy excessive space on the chip, thereby being beneficial to the operation of a user and the implementation of test work.

The embodiments described above with reference to the drawings are exemplary only for the purpose of illustrating the present application and are not to be construed as limiting the present application. In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the foregoing description explains the embodiments of the present application in detail with reference to the drawings. However, it will be appreciated by those of ordinary skill in the art that in the various embodiments of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The division of the examples is for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be mutually incorporated and referred to each other without contradiction.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be implemented in sequences other than those illustrated or described herein.

Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The construction, features and functions of the present application are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present application, but the present application is not limited by the drawings, and all equivalent embodiments that can be modified or changed according to the idea of the present application are within the scope of the present application without departing from the spirit of the present application.

Claims

1. A through silicon via test circuit applied to a flip chip, the test circuit comprising:

a through-silicon via interconnect and a flip-chip interconnect that are discrete from each other;

the first conducting wire is formed by extending from a first end to a second end;

a first measurement line electrically connected to the first end through a through-silicon via interconnect; and a second measurement line electrically connected to the second end by a flip-chip interconnect;

each of which has two separate measuring portions.

2. The through-silicon-via test circuit of claim 1, wherein the flip-chip interconnect is a columnar structure; and/or the flip-chip interconnect is of superconducting material; and/or the through silicon via interconnection is a hollow column or a solid column.

3. The through silicon via test circuit of claim 1, wherein the flip-chip interconnects are indium pillars;

and/or the flip-chip interconnect is cylindrical and has a first cylindrical section and a second cylindrical section which are coaxial, the first cylindrical section being connected to the second end of the first wire, the second cylindrical section being connected to the second measurement wire;

and/or the test circuit comprises a plurality of second measurement lines, and each of the second measurement lines is connected with the first lead through a separate flip-chip interconnection.

4. The through silicon via test circuit according to any one of claims 1 to 3, wherein the first conductive line, the first measurement line and the second measurement line together constitute a measurement component;

the test circuit comprises at least two measurement assemblies, wherein two adjacent measurement assemblies are electrically connected in series, and two ends of the electrical connection in series are respectively positioned on the through silicon via interconnection of each of the two adjacent measurement assemblies.

5. The TSV test circuit of claim 4, wherein the electrical series connection is formed by connecting the ends of the series connection to the respective TSV interconnects.

6. The through silicon via test circuit of claim 5, wherein the series line comprises at least one series interconnect configured through a through silicon via and a plurality of second wires connected in series through the at least one series interconnect.

7. The TSV test circuit of claim 6, wherein the two ends of the series line are configured to be non-planar; and/or the serial interconnection and the through silicon via interconnection have the same structure; and/or the serial interconnection piece and the through silicon via interconnection piece are made of the same material.

8. A flip chip having a first chip and a second chip opposed to each other, characterized in that the flip chip further comprises a through-silicon-via test circuit according to any one of claims 1 to 7;

the first lead and the first measuring line are configured on a first chip, and the second measuring line is configured on a second chip;

the through silicon via interconnection is arranged on the first chip in a penetrating way; the flip-chip interconnection is configured between the first chip and the second chip.

9. The flip chip of claim 8, wherein the second chip has a surface facing the first chip, the surface comprising an inner region and an outer region, the outer region surrounding the inner region, an orthographic projection of the first chip on the second chip being within the inner region or an outline of the orthographic projection of the first chip on the second chip coinciding with an outline of the inner region;

the measuring portion of the second measuring line is disposed in the outer layer region.

10. The flip chip of claim 8, wherein the first wire is a superconducting wire or the first wire is a coplanar waveguide.