CN212412061U - 半导体器件 - Google Patents

半导体器件 Download PDF

Info

Publication number
CN212412061U
CN212412061U CN202021369729.3U CN202021369729U CN212412061U CN 212412061 U CN212412061 U CN 212412061U CN 202021369729 U CN202021369729 U CN 202021369729U CN 212412061 U CN212412061 U CN 212412061U
Authority
CN
China
Prior art keywords
gate
pattern
spacer
source
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202021369729.3U
Other languages
English (en)
Inventor
申洪湜
卢炫准
朴兴植
成石铉
李道行
李元赫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of CN212412061U publication Critical patent/CN212412061U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

提供了半导体器件，其包括：跨越衬底的栅极图案，栅极图案包括依次堆叠在衬底上的栅极绝缘层、栅电极和栅极盖图案；栅极间隔物，覆盖栅极图案的侧壁；在衬底上的源极/漏极图案，源极/漏极图案邻近栅极图案的侧壁；在源极/漏极图案上的接触垫，接触垫的顶表面低于栅电极的顶表面；在接触垫上的源极/漏极接触插塞；以及在栅极间隔物与源极/漏极接触插塞之间的保护间隔物，保护间隔物具有包围源极/漏极接触插塞的环形。

Description

半导体器件
技术领域
本公开涉及半导体器件和制造半导体器件的方法。
背景技术
半导体器件由于其小尺寸、多功能和/或低成本特性而被视为电子工业中的重要元件。半导体器件被归类为用于存储数据的半导体存储器件、用于处理数据的半导体逻辑器件以及包括存储元件和逻辑元件两者的混合半导体器件。随着电子工业发展，对具有改善的特性的半导体器件的需求不断增长。例如，对具有高可靠性、高性能和/或多个功能的半导体器件的需求不断增长。为了满足此需求，增大了半导体器件的复杂性和/或集成密度。
实用新型内容
根据一实施方式，一种半导体器件可以包括：栅极图案，跨过衬底并包括依次堆叠在衬底上的栅极绝缘层、栅电极和栅极盖图案；栅极间隔物，覆盖栅极图案的侧壁；源极/漏极图案，设置在衬底上并且在栅极图案旁边；接触垫，设置在源极/漏极图案上以具有比栅电极的顶表面低的顶表面；在接触垫上的源极/漏极接触插塞；以及保护间隔物，插设在栅极间隔物与源极/漏极接触插塞之间以具有包围源极/漏极接触插塞的环形。
根据一实施方式，一种半导体器件可以包括：有源鳍，从衬底突出并且在第一方向上延伸；栅极图案，跨过有源鳍并且包括依次堆叠在衬底上的栅极绝缘层、栅电极和栅极盖图案；栅极间隔物，覆盖栅极图案的侧壁；源极/漏极图案，设置在有源鳍上并且在栅极图案旁边；接触垫，设置在源极/漏极图案上以具有比栅电极的顶表面低的顶表面；在接触垫上的源极/漏极接触插塞；以及保护间隔物，插设在栅极间隔物与源极/漏极接触插塞之间，保护间隔物具有包围源极/漏极接触插塞的环形并具有比栅极间隔物大的宽度。
根据一实施方式，一种制造半导体器件的方法可以包括：在衬底上形成栅极图案、栅极间隔物、源极/漏极图案和层间绝缘层，栅极图案跨过衬底并且彼此相邻，栅极间隔物覆盖栅极图案的侧壁，源极/漏极图案设置在栅极图案中的相邻的栅极图案之间，层间绝缘层形成为覆盖栅极图案、栅极间隔物和源极/漏极图案，栅极图案中的每个包括依次堆叠的栅极绝缘层、栅电极和栅极盖图案；对层间绝缘层执行各向异性蚀刻工艺，以形成暴露源极/漏极图案的第一孔；对层间绝缘层执行各向同性蚀刻工艺，以扩大第一孔的宽度并暴露栅极间隔物的侧壁；在第一孔中形成接触垫，接触垫与源极/漏极图案接触；在第一孔中形成保护间隔物，保护间隔物覆盖栅极间隔物中的相邻的栅极间隔物的侧壁、暴露接触垫的顶表面、并且当在俯视图中看时具有环形；蚀刻栅极图案中的至少一个的栅极盖图案，以形成暴露栅电极的第二孔；以及在第一孔中形成与接触垫接触的源极/漏极接触插塞，并且在第二孔中形成与栅电极接触的栅极接触插塞。
附图说明
通过参照附图详细描述示例性实施方式，特征对本领域技术人员将变得明显，附图中：
图1A示出了根据一实施方式的半导体器件的俯视图。
图1B示出了根据一实施方式的半导体器件的沿图1A的线A-A'、B-B'和C-C'截取的剖视图。
图1C示出了根据一实施方式的半导体器件的沿图1A的线A-A'、B-B'和C-C'截取的剖视图。
图1D示出了根据一实施方式的半导体器件的沿图1A的线A-A'、B-B'和C-C'截取的剖视图。
图2A、图3A、图4A、图5A、图6A、图7A和图8A示出了在制造具有图1A所示的平面结构的半导体器件的过程中的阶段的俯视图。
图2B、图3B、图4B、图5B、图6B、图7B和图8B分别示出了沿图2A、图3A、图4A、图5A、图6A、图7A和8A的线A-A'、B-B'和CC'截取的剖视图。
图9A示出了根据一实施方式的半导体器件的俯视图。
图9B示出了沿图9A的线A-A'、B-B'和C-C'截取的剖视图。
图10示出了制造具有图9B的剖面的半导体器件的过程的剖视图。
图11A示出了根据一实施方式的半导体器件的俯视图。
图11B示出了沿图11A的线A-A'、B-B'和C-C'截取的剖视图。
图12示出了制造具有图11B的剖面的半导体器件的过程的剖视图。
图13A示出了根据一实施方式的半导体器件的俯视图。
图13B示出了沿图13A的线A-A'、B-B'和C-C'截取的剖视图。
图14示出了制造具有图13B的剖面的半导体器件的过程的剖视图。
图15和图16示出了俯视图，每个俯视图示出了根据一实施方式的半导体器件。
具体实施方式
现在将参照其中示出了示例实施方式的附图更全面地描述示例实施方式。
图1A是示出根据一实施方式的半导体器件的俯视图。图1B是根据一实施方式的半导体器件的沿图1A的线A-A'、B-B'和C-C'截取的剖视图。图1B的半导体器件可以对应于鳍式场效应晶体管(FinFET)器件的示例。
参照图1A和图1B，有源鳍AF可以从衬底1突出。器件隔离层3可以设置在衬底1的位于有源鳍AF旁边的部分上，例如，器件隔离层3可以沿平行于衬底1的顶表面的第二方向Y与有源鳍AF相邻。有源鳍AF可以具有位于例如沿垂直于衬底1的顶表面的第三方向Z比器件隔离层3的顶表面高的高度(level)处的顶表面和上侧。衬底1可以是单晶硅晶片或绝缘体上硅(SOI)晶片。器件隔离层3可以由例如硅氧化物、硅氮化物和硅氮氧化物中的至少一种形成，或包括例如硅氧化物、硅氮化物和硅氮氧化物中的至少一种，并且可以具有单层结构或多层结构。有源鳍AF可以是在平行于衬底1的顶表面的第一方向X上伸长的条形图案或线形图案。
栅极图案GP1、GP2、GP3和GP4中的每个可以被提供为在与第一方向X交叉的第二方向Y上跨越有源鳍AF。栅极图案GP1、GP2、GP3和GP4可以在第一方向X上彼此间隔开。栅极图案GP1、GP2、GP3和GP4中的每个可以包括依次堆叠在衬底1上的栅极绝缘层GO、栅电极GE和栅极盖图案GC。
栅极绝缘层GO可以包括例如硅氧化物和其介电常数高于硅氧化物的介电常数的高k电介质材料中的至少一种。例如，高k电介质材料可以包括金属氧化物(例如铝氧化物)。栅电极GE可以由金属性材料(例如钨、铜和铝)中的至少一种形成，或包括金属性材料(例如钨、铜和铝)中的至少一种。功函数层、扩散阻挡层等可以插设在栅电极GE与栅极绝缘层GO之间。扩散阻挡层可以包括金属氮化物层(例如钛氮化物层)。栅极盖图案GC可以由例如硅氮化物形成，或包括例如硅氮化物。
栅极间隔物GS可以被提供为分别覆盖栅极图案GP1、GP2、GP3和GP4的侧壁。栅极间隔物GS可以包括例如硅氮化物层、或包含硅氮化物层和硅氧化物层的双层或三层。栅极绝缘层GO可以延伸到栅电极GE与栅极间隔物GS之间的区域中，并且可以与栅极盖图案GC接触。
凹陷区域R1可以形成在有源鳍AF中并且在栅极间隔物GS旁边，例如，凹陷区域R1可以在栅极图案GP1、GP2、GP3和GP4中的相邻的栅极图案之间形成在有源鳍AF内。源极/漏极图案SD可以提供在凹陷区域R1中以邻近栅极图案GP1、GP2、GP3和GP4中的相应栅极图案的侧壁。源极/漏极图案SD可以是由与衬底1相同的材料形成的外延层。例如，源极/漏极图案SD可以是硅外延层。或者，源极/漏极图案SD可以包括与衬底1不同的材料。例如，源极/漏极图案SD可以是硅锗外延层。源极/漏极图案SD可以掺有n型或p型杂质。例如，源极/漏极图案SD可以掺有磷或硼。栅极图案GP1、GP2、GP3和GP4、间隔物GS以及源极/漏极图案SD可以用层间绝缘层IL覆盖。层间绝缘层IL可以由例如硅氧化物、硅氮化物、硅氮氧化物和多孔绝缘材料中的至少一种形成，或包括例如硅氧化物、硅氮化物、硅氮氧化物和多孔绝缘材料中的至少一种，并且可以具有单层结构或多层结构。
第一孔H1可以形成在层间绝缘层IL中以与源极/漏极图案SD重叠，例如，暴露源极/漏极图案SD。例如，如图1A所示，第一孔H1可以定位成与有源鳍AF的在栅极图案GP1、GP2、GP3和GP4中的相邻的栅极图案之间的部分重叠。例如，如图1B的剖面A-A'所示，栅极间隔物GS的侧壁可以与第一孔H1重叠，例如，通过第一孔H1被暴露。例如，如图1B的剖面A-A'进一步所示，第一孔H1沿第一方向X的最上宽度(即，第一孔H1的在栅极图案GP1、GP2、GP3和GP4之上的部分沿第一方向X的宽度)可以大于源极/漏极图案SD沿第一方向X的宽度。
接触垫CP可以设置在第一孔Hl中，并且可以与源极/漏极图案SD接触。如图1B的剖面A-A'所示，接触垫CP的侧壁可以例如沿第一方向X与栅极间隔物GS的侧壁接触。如图1B的剖面C-C'所示，接触垫CP的侧壁可以例如沿第二方向Y与第一孔H1的内侧壁接触。例如，参照图1A-1B，接触垫CP可以直接在源极/漏极图案SD之上部分地填充第一孔H1，因此接触垫CP的沿第一方向X彼此相反的侧壁可以与相邻栅极图案的面对的栅极间隔物GS直接接触，并且接触垫CP的沿第二方向Y彼此相反的侧壁可以与同一第一孔H1的面对的内侧壁直接接触，即，与层间绝缘层IL的面对的侧壁直接接触。接触垫CP可以由金属-半导体材料(例如钴硅化物)、扩散阻挡材料(例如钛氮化物)或金属性材料(例如钨和铝)形成，或包括金属-半导体材料(例如钴硅化物)、扩散阻挡材料(例如钛氮化物)或金属性材料(例如钨和铝)。
源极/漏极图案SD的上侧SW可以以一角度倾斜，例如从源极/漏极图案SD的最上表面向下倾斜，并且接触垫CP的下部可以延伸为与源极/漏极图案SD的倾斜的上侧SW接触。例如，如图1B的剖面C-C'所示，接触垫CP的底部可以沿着源极/漏极图案SD的最上表面且至少部分地沿着源极/漏极图案SD的例如向下倾斜的上侧SW是共形的。
在接触垫CP上，第一孔Hl的内侧壁可以用保护间隔物LS覆盖，如图1B的剖面C-C'所示。例如，如图1B的剖面A-A'和C-C'所示，保护间隔物LS可以沿着第一孔H1的未被接触垫CP填充的剩余部分的例如整个内侧壁例如连续地延伸，以接触接触垫CP的顶表面。如图1B的剖面C-C'所示，保护间隔物LS的外侧壁，例如接触层间绝缘层IL的侧壁，可以与接触垫CP的接触层间绝缘层IL的侧壁对准，例如共线。例如，保护间隔物LS的在相邻栅极图案的两个面对的栅极间隔物GS之间(例如，不与栅极图案和栅极间隔物重叠)的侧壁可以与接触垫CP的在栅极图案延伸的方向上的侧壁对准。如图1B的剖面A-A'所示，保护间隔物LS可以与栅极间隔物GS的侧壁接触。
当在俯视图中看时，保护间隔物LS可以具有闭合环形状(例如，图1A中的画上阴影的灰色闭合环)。在本实施方式中，当在俯视图中看时，保护间隔物LS可以具有椭圆环形。保护间隔物LS可以与栅极间隔物GS重叠，例如，当在俯视图(图1A)中看时，单个第一孔H1中的一个椭圆环形的保护间隔物LS可以与相邻栅极图案的两个面对的栅极间隔物GS重叠。保护间隔物LS的宽度可以大于栅极间隔物GS的宽度，例如，单个第一孔H1中的一个椭圆环形的保护间隔物LS的顶部可以延伸超出相邻栅极图案的两个面对的栅极间隔物GS，以与栅极盖图案GC的顶表面的一部分接触(在图1A的俯视图中)。例如，如图1B所示，保护间隔物LS的例如在栅极图案之上沿第一方向X测量的宽度可以大于栅极间隔物GS的例如从与该保护间隔物LS相邻的栅极图案的侧壁起沿第一方向X测量的宽度。
在一实施方式中，保护间隔物LS可以由其介电常数低于栅极间隔物GS的介电常数的低k电介质材料形成，或包括所述低k电介质材料。例如，栅极间隔物GS可以由硅碳氧化物(SiOC)形成，或包括硅碳氧化物(SiOC)。保护间隔物LS可以具有突出于栅极图案GP1、GP2、GP3和GP4之上的形状，例如以与栅极盖图案GC的顶表面至少部分地重叠。保护间隔物LS的顶表面可以与层间绝缘层IL的顶表面共面。保护间隔物LS中的相邻的保护间隔物可以沿第一方向X彼此间隔开，并且层间绝缘层IL的一部分可以位于保护间隔物LS中的相邻的保护间隔物之间。
由保护间隔物LS的内侧壁限定的第二孔H2可以设置在第一孔H1中，例如，第一孔H1和第二孔H2可以是同心的。第二孔H2可以暴露接触垫CP的顶表面的未被保护间隔物LS覆盖的部分。源极/漏极接触插塞SCT可以设置在第二孔H2中，例如，源极/漏极接触插塞SCT可以完全填充第二孔H2。保护间隔物LS可以具有例如在俯视图(图1A)中的包围(例如完全围绕)源极/漏极接触插塞SCT的环形(例如椭圆环形)、以及围绕源极/漏极接触插塞SCT的例如整个侧壁的管状圆筒形(图1B)。由于保护间隔物LS，源极/漏极接触插塞SCT可以例如沿第一方向X和第二方向Y中的每个具有比接触垫CP的宽度小的宽度。
第一栅极接触插塞GCT1可以设置在保护间隔物LS中的相邻的保护间隔物之间并且在第二栅极图案GP2上。第一栅极接触插塞GCT1可以被提供为穿透第二栅极图案GP2的栅极盖图案GC并与栅电极GE接触。第一栅极接触插塞GCT1可以设置在第三孔H3中。第三孔H3的内侧壁可以由栅极盖图案GC的侧壁和层间绝缘层IL的侧壁组成。第一栅极接触插塞GCT1可以与保护间隔物LS接触。
第二栅极接触插塞GCT2可以设置在第三栅极图案GP3上。第二栅极接触插塞GCT2可以被提供为穿透第三栅极图案GP3的栅极盖图案GC并与栅电极GE接触。如图1B的剖面B-B'所示，第二栅极接触插塞GCT2可以与器件隔离层3垂直地重叠。第二栅极接触插塞GCT2可以设置在第四孔H4中。第四孔H4的内侧壁可以由栅极盖图案GC的侧壁和层间绝缘层IL的侧壁组成。第二栅极接触插塞GCT2可以与保护间隔物LS间隔开。
图1C是示出根据一实施方式的半导体器件的沿图1A的线A-A'、B-B'和C-C'截取的剖视图。图1C的半导体器件可以对应于多桥沟道场效应晶体管
Figure BDA0002581007370000071
器件的示例。
参照图1C，沟道图案CH可以设置在有源鳍AF上以与有源鳍AF间隔开。沟道图案CH可以包括堆叠在有源鳍AF上的第一至第三半导体图案CH1、CH2和CH3。第一至第三半导体图案CH1、CH2和CH3可以彼此间隔开。在一实施方式中，第一至第三半导体图案CH1、CH2和CH3可以包括例如硅。栅电极GE可以覆盖沟道图案CH的顶表面和侧表面。第二半导体图案CH2的宽度可以不同于第三半导体图案CH3的宽度。
栅电极GE可以包括被连接以形成单个物体的第一至第四栅极部分G1、G2、G3和G4。第一栅极部分G1可以位于有源鳍AF与第一半导体图案CH1之间。第二栅极部分G2可以位于第一半导体图案CH1与第二半导体图案CH2之间。第三栅极部分G3可以位于第二半导体图案CH2与第三半导体图案CH3之间。栅极绝缘层GO可以插设在栅电极GE与沟道图案CH之间以及在栅电极GE与有源鳍AF之间。源极/漏极图案SD可以延伸到栅极间隔物GS之下的区域，以与沟道图案CH的侧壁接触。源极/漏极图案SD的宽度可以大于接触垫CP的宽度。除上述特征以外，根据本实施方式的半导体器件可以被构造为具有与参照图1B描述的半导体器件的特征基本相同的特征。
图1D是示出根据一实施方式的半导体器件的沿图1A的线A-A'、B-B'和C-C'截取的剖视图。图1D的半导体器件可以对应于多桥沟道场效应晶体管
Figure BDA0002581007370000072
器件的示例。
参照图1D，根据本实施方式的半导体器件还可以包括阻挡绝缘图案BP，该阻挡绝缘图案BP插设在源极/漏极图案SD与包围第一至第三栅极部分G1、G2和G3的栅极绝缘层GO之间。阻挡绝缘图案BP可以由与栅极绝缘层GO不同的材料(例如硅氮化物)形成，或包括与栅极绝缘层GO不同的材料(例如硅氮化物)。阻挡绝缘图案BP可以防止在第一至第三栅极部分G1、G2和G3与源极/漏极图案SD之间的可能在制造图1D的半导体器件的过程中发生的桥接问题，这可以提高半导体器件的可靠性。除上述特征以外，根据本实施方式的半导体器件可以被构造为具有与参照图1C描述的半导体器件的特征基本相同的特征。
在根据图1A-1D的实施方式的半导体器件中，接触垫CP的顶表面可以例如沿图1B的第三方向Z低于栅电极GE的顶表面，因此可以增加接触垫CP与栅电极GE之间的距离以防止接触垫CP与栅电极GE之间的桥接问题。此外，由于保护间隔物LS，可以增加栅电极GE与源极/漏极接触插塞SCT之间的距离，从而防止栅电极GE与源极/漏极接触插塞SCT之间的桥接问题。另外，因为保护间隔物LS包括低k电介质材料，所以可以减小栅电极GE与源极/漏极接触插塞SCT之间的寄生电容，从而减少或最小化信号干扰问题。因此，可以提高半导体器件的可靠性。
图2A、图3A、图4A、图5A、图6A、图7A和图8A是示出制造具有图1A所示的平面结构的半导体器件的过程中的阶段的俯视图。图2B、图3B、图4B、图5B、图6B、图7B和图8B分别是沿图2A、图3A、图4A、图5A、图6A、图7A和图8A的线A-A'、B-B'和C-C'截取的剖视图。
参照图2A和图2B，衬底1可以被蚀刻以形成有源鳍AF，该有源鳍AF是衬底1的一部分。器件隔离层3可以形成在衬底1的位于有源鳍AF旁边的部分上。虚设栅极图案可以被形成以与有源鳍AF交叉，并且栅极间隔物GS可以被形成以覆盖虚设栅极图案的侧壁。凹陷区域R1可以通过蚀刻有源鳍AF的靠近栅极间隔物GS的暴露部分而形成。可以执行选择性外延生长(SEG)工艺和原位掺杂工艺以在凹陷区域R1中形成源极/漏极图案SD。如图2B的剖面C-C'所示，源极/漏极图案SD中的每个可以以例如具有倾斜的上侧SW的五边形形成。虚设栅极图案可以被去除，然后，栅极图案GP1、GP2、GP3和GP4可以分别形成在由被去除的虚设栅极图案限定的区域例如开口中。层间绝缘层IL可以被形成以覆盖栅极图案GP1、GP2、GP3和GP4以及源极/漏极图案SD。在一实施方式中，层间绝缘层IL可以由例如正硅酸四乙酯(TEOS)形成，或包括例如正硅酸四乙酯(TEOS)。
参照图3A和图3B，第一掩模图案MK1可以形成在层间绝缘层IL上。第一掩模图案MK1可以包括与源极/漏极图案SD重叠的开口。第一掩模图案MK1可以由相对于层间绝缘层IL具有蚀刻选择性的材料(例如光致抗蚀剂、多晶硅、旋涂硬掩模(SOH)、旋涂碳(SOC)和非晶碳层(ACL)材料)中的至少一种形成，或包括所述材料中的至少一种。层间绝缘层IL可以使用第一掩模图案MK1作为蚀刻掩模被各向异性地蚀刻，以形成分别暴露源极/漏极图案SD的第一孔H1。在此，源极/漏极图案SD的上部也可以被蚀刻，如图3B的剖面C-C'所示。第一孔H1中的每个可以形成为具有例如如在图3B的层间绝缘层IL的面对的侧壁之间沿图2A的第一方向X所测量的第一宽度W1。第一孔H1可以暴露栅极间隔物GS的侧壁。即使当在第一孔H1的形成期间发生不对准时，栅极图案GP1、GP2、GP3和GP4的侧壁也可以由栅极间隔物GS保护。用于形成第一孔H1的各向异性蚀刻工艺可以通过利用栅极间隔物GS的蚀刻选择性的自对准方法来执行。在某些情况下，各向异性蚀刻工艺可以导致栅极间隔物GS的上部的损坏。
参照图4A和图4B，第一掩模图案MK1可以被去除以暴露层间绝缘层IL的顶表面。可以执行选择性地蚀刻层间绝缘层IL的各向同性蚀刻工艺，以将第一孔H1的宽度扩大到例如如在图4B的被蚀刻的层间绝缘层IL的面对的侧壁之间沿图2A的第一方向X所测量的第二宽度W2，第二宽度W2大于第一宽度W1。如图4B的剖面C-C'所示，第一孔H1可以具有也沿图2A的第二方向Y扩大的宽度，因此源极/漏极图案SD的倾斜的上侧SW可以至少部分地被暴露。可以使用例如氢氟酸或氟化氢气体来执行各向同性蚀刻工艺。因为各向同性蚀刻工艺被执行以选择性地蚀刻层间绝缘层IL，所以可以防止栅极间隔物GS在该各向同性蚀刻工艺期间被损坏。
参照图5A和图5B，导电层可以形成在衬底1上并且可以通过例如回蚀刻工艺而凹入。因此，接触垫CP可以形成在第一孔H1中。在此，因为第一孔H1被扩大为具有第二宽度W2，所以可以通过第一孔H1有效地供应沉积源气体和蚀刻剂，从而更有效地执行形成导电层并使导电层凹入的工艺。在一实施方式中，接触垫CP可以在没有任何故障的情况下正常地形成。接触垫CP可以与源极/漏极图案SD的倾斜的上侧SW接触。接触垫CP的顶表面可以低于栅电极GE的顶表面。在某些情况下，栅极间隔物GS的上部可以被回蚀刻工艺损坏。
参照图5A、图5B、图6A和图6B，保护层可以形成在衬底1上，然后，可以执行对保护层的回蚀刻工艺以形成覆盖第一孔H1的内侧壁的保护间隔物LS。在某些实施方式中，保护间隔物LS的形成可以包括用保护层填充孔H1、执行化学机械抛光(CMP)工艺以在第一孔H1中形成保护图案、以及对保护图案执行各向异性蚀刻工艺。由于保护间隔物LS，第二孔H2可以被形成，以部分地暴露接触垫CP的顶表面。保护间隔物LS可以覆盖并保护栅极间隔物GS的受损的上部。
参照图6A、图6B、图7A和图7B，第二掩模图案MK2可以形成在衬底1上。第二掩模图案MK2可以包括开口，所述开口与第二栅极图案GP2的在保护间隔物LS中的相邻的保护间隔物之间的部分以及第三栅极图案GP3的与保护间隔物LS间隔开的部分重叠。第二掩模图案MK2可以由例如旋涂硬掩模(SOH)材料中的至少一种形成，或包括例如旋涂硬掩模(SOH)材料中的至少一种。第二掩模图案MK2可以填充第二孔H2。层间绝缘层IL以及第二和第三栅极图案GP2和GP3的栅极盖图案GC可以使用第二掩模图案MK2作为蚀刻掩模被蚀刻。因此，第三孔H3和第四孔H4可以被形成，以分别暴露栅电极GE。在第三孔H3和第四孔H4的形成期间，第二掩模图案MK2可以保护接触垫CP和保护间隔物LS。
参照图7A、图7B、图8A和图8B，第二掩模图案MK2可以被去除以暴露第二至第四孔H2、H3和H4。第二掩模图案MK2的去除可以通过例如其中使用氧气的灰化工艺来执行。
参照图8A、图8B、图1A和图1B，导电层可以形成在衬底1上以填充第二至第四孔H2、H3和H4。此后，可以执行CMP工艺以分别在第二至第四孔H2、H3和H4中形成源极/漏极接触插塞SCT、第一栅极接触插塞GCT1和第二栅极接触插塞GCT2。在某些实施方式中，保护间隔物LS的上部和层间绝缘层IL的上部也可以在CMP工艺期间被去除。
如果没有形成保护间隔物LS，则在导电层的形成期间，导电层可能会穿过栅极间隔物GS的受损的上部接触栅电极GE，从而有可能在源极/漏极接触插塞SCT与栅电极GE之间形成桥。随着半导体器件的集成密度增大，栅极间隔物GS的宽度减小，从而增大了形成这样的桥的可能性。
相比之下，根据一实施方式，保护间隔物LS防止形成这样的桥。此外，当保护间隔物LS形成在特定的期望区域处例如以不覆盖层间绝缘层IL的整个顶表面时，例如由于不需要改变工艺条件来确定为由层间绝缘层IL覆盖的整个顶表面负责的蚀刻停止点，因此该制造方法可以表现出减少的工艺故障和提高的产量。
图9A是示出根据一实施方式的半导体器件的俯视图。图9B是沿图9A的线A-A'、B-B'和C-C'截取的剖视图。
参照图9A和图9B，第一辅助绝缘图案PL1可以插设在第一孔H1的内侧壁与保护间隔物LS之间以及在第一孔H1的内侧壁与接触垫CP之间。第一辅助绝缘图案PL1可以由与保护间隔物LS不同的材料形成，或包括与保护间隔物LS不同的材料。第一辅助绝缘图案PL1可以由与栅极间隔物GS相同的材料(例如硅氮化物)形成，或包括与栅极间隔物GS相同的材料(例如硅氮化物)。第一辅助绝缘图案PL1可以用于加强栅极间隔物GS的受损部分。第一辅助绝缘图案PL1可以插设在保护间隔物LS与栅极间隔物GS之间以及在保护间隔物LS与层间绝缘层IL之间。当在俯视图中看时，第一辅助绝缘图案PL1可以具有包围保护间隔物LS的环形。
图10是示出制造图9A和图9B的半导体器件的过程的剖视图。
参照图10，辅助绝缘层PL可以形成在衬底1上以共形地覆盖图4B的其中第一孔H1的宽度被扩大的结构。辅助绝缘层PL可以用于加强栅极间隔物GS的可能在形成第一孔H1的工艺期间形成的受损部分。此后，如图5B所示，接触垫CP可以被形成，然后如图6B所示，保护间隔物LS可以被形成。在此，辅助绝缘层PL也可以被蚀刻以形成第一辅助绝缘图案PL1。可以以与参照图7B、图8B和图1B描述的方式相同的方式执行后续工艺。
图11A是示出根据一实施方式的半导体器件的俯视图。图11B是沿图11A的线A-A'、B-B'和C-C'截取的剖视图。
参照图11A和图11B，第二辅助绝缘图案PL2可以插设在第二孔H2的内侧壁与源极/漏极接触插塞SCT之间。第二辅助绝缘图案PL2可以由与保护间隔物LS不同的材料形成，或包括与保护间隔物LS不同的材料。例如，第二辅助绝缘图案PL2可以由硅氮化物、硅氧化物和硅氮氧化物中的至少一种形成，或包括硅氮化物、硅氧化物和硅氮氧化物中的至少一种。第二辅助绝缘图案PL2可以插设在保护间隔物LS与源极/漏极接触插塞SCT之间。当在俯视图中看时，第二辅助绝缘图案PL2可以具有包围源极/漏极接触插塞SCT的环形。
图12是示出制造图11A和图11B的半导体器件的过程的剖视图。
参照图12，在如图6B所示地形成保护间隔物LS之后，辅助绝缘层PL可以共形地形成在衬底1的整个顶表面上。此后，可以执行对辅助绝缘层PL的各向异性蚀刻工艺以形成第二辅助绝缘图案PL2。可以以与参照图7B、图8B和图1B描述的方式相同的方式执行后续工艺。
图13A是示出根据一实施方式的半导体器件的俯视图。图13B是沿图13A的线A-A'、B-B'和C-C'截取的剖视图。
参照图13A和图13B，第二辅助绝缘图案PL2可以插设在第二孔H2的内侧壁与源极/漏极接触插塞SCT之间。另外，第三辅助绝缘图案PL3可以插设在第三孔H3的内侧壁与第一栅极接触插塞GCT1之间以及在第四孔H4的内侧壁与第二栅极接触插塞GCT2之间。第三辅助绝缘图案PL3可以插设在保护间隔物LS与第一栅极接触插塞GCT1之间。第二辅助绝缘图案PL2和第三辅助绝缘图案PL3可以由与保护间隔物LS不同的材料形成，或包括与保护间隔物LS不同的材料。第二辅助绝缘图案PL2可以由与第三辅助绝缘图案PL3相同的材料形成，或包括与第三辅助绝缘图案PL3相同的材料。第二辅助绝缘图案PL2和第三辅助绝缘图案PL3可以由例如硅氮化物、硅氧化物和硅氮氧化物中的至少一种形成，或包括例如硅氮化物、硅氧化物和硅氮氧化物中的至少一种。当在俯视图中看时，第二辅助绝缘图案PL2可以具有包围源极/漏极接触插塞SCT的环形。当在俯视图中看时，第三辅助绝缘图案PL3可以具有分别包围第一栅极接触插塞GCT1和第二栅极接触插塞GCT2的环形。
图14是示出制造图13A和图13B的半导体器件的过程的剖视图。
参照图14，在如图8B所示地暴露第二至第四孔H2、H3和H4之后且在形成导电层之前，辅助绝缘层PL可以被共形地形成。此后，可以对辅助绝缘层PL执行各向异性蚀刻工艺，以形成第二辅助绝缘图案PL2和第三辅助绝缘图案PL3。接下来，可以以与参照图1A和图1B描述的方式相同或相似的方式形成导电层，并且可以对导电层执行CMP工艺。
在不矛盾的条件下，参照图9A至图14描述的实施方式可以以各种形式彼此组合。例如，在组合的实施方式中的半导体器件可以被构造为包括第一至第三辅助绝缘图案PL1、PL2和PL3的全部，或被构造为仅包括第一辅助绝缘图案PL1和第二辅助绝缘图案PL2。
图15和图16是俯视图，每个俯视图示出了根据一实施方式的半导体器件。保护间隔物LS可以具有矩形闭合环形状，如图15所示。或者，保护间隔物LS可以具有圆形闭合环形状，如图16所示。
作为总结和回顾，实施方式提供了具有提高的可靠性的半导体器件以及具有增加的产量的制造半导体器件的方法。即，根据一实施方式，半导体器件可以包括保护间隔物，该保护间隔物防止桥图案形成在彼此相邻的栅电极和源极/漏极接触插塞之间并减小它们之间的寄生电容。此外，根据一实施方式的制造半导体器件的方法可以包括形成保护间隔物，因此减少了工艺故障并增加了产量。因此，可以提高半导体器件的可靠性。
在此已经公开了示例实施方式，并且尽管采用了特定术语，但是它们仅在一般和描述性的意义上被使用和解释，而不是出于限制的目的。在一些情形下，在提交本申请时对本领域普通技术人员将明显的是，结合特定实施方式描述的特征、特性和/或元件可以单独使用或与结合其他实施方式描述的特征、特性和/或元件组合使用，除非另有明确指示。因此，本领域技术人员将理解，在不背离本实用新型的如所附权利要求中阐明的精神和范围的情况下可以进行形式和细节上的各种改变。
2019年8月23日在韩国知识产权局提交且名称为“半导体器件和制造半导体器件的方法”的韩国专利申请第10-2019-0103975号通过引用全文合并于此。

Claims (15)

1.一种半导体器件，其特征在于，包括：
跨越衬底的栅极图案，所述栅极图案包括依次堆叠在所述衬底上的栅极绝缘层、栅电极和栅极盖图案；
栅极间隔物，其覆盖所述栅极图案的侧壁；
在所述衬底上的源极/漏极图案，所述源极/漏极图案邻近所述栅极图案的所述侧壁；
在所述源极/漏极图案上的接触垫，所述接触垫的顶表面低于所述栅电极的顶表面；
在所述接触垫上的源极/漏极接触插塞；以及
保护间隔物，其在所述栅极间隔物与所述源极/漏极接触插塞之间，所述保护间隔物具有包围所述源极/漏极接触插塞的环形。
2.如权利要求1所述的半导体器件，其特征在于：
所述保护间隔物与所述栅极间隔物接触，以及
所述保护间隔物的第一宽度大于所述栅极间隔物的第二宽度，所述保护间隔物的所述第一宽度在所述栅极图案之上沿第一方向测量，所述栅极间隔物的所述第二宽度从所述栅极图案的所述侧壁起沿所述第一方向测量。
3.如权利要求1所述的半导体器件，其特征在于，所述保护间隔物具有比所述栅极间隔物的介电常数低的介电常数。
4.如权利要求1所述的半导体器件，其特征在于，所述保护间隔物的不与所述栅极图案和所述栅极间隔物重叠的侧壁与所述接触垫的在所述栅极图案延伸的方向上的侧壁对准。
5.如权利要求1所述的半导体器件，其特征在于，所述保护间隔物围绕所述源极/漏极接触插塞的整个外侧壁。
6.如权利要求1所述的半导体器件，其特征在于，所述源极/漏极接触插塞的宽度小于所述接触垫的宽度。
7.如权利要求1所述的半导体器件，其特征在于，所述源极/漏极图案具有倾斜的上侧，并且所述接触垫与所述倾斜的上侧接触。
8.如权利要求1所述的半导体器件，其特征在于，还包括：
栅极接触插塞，其穿透所述栅极盖图案、与所述栅电极接触、并且具有比所述栅极盖图案的宽度小的宽度；以及
辅助绝缘图案，其在所述栅极间隔物与所述接触垫之间、在所述栅极间隔物与所述保护间隔物之间以及在所述保护间隔物与所述栅极接触插塞之间，所述辅助绝缘图案包括与所述保护间隔物的材料不同的材料。
9.如权利要求1所述的半导体器件，其特征在于，还包括在所述保护间隔物与所述源极/漏极接触插塞之间的辅助绝缘图案，所述辅助绝缘图案包括与所述保护间隔物不同的材料。
10.如权利要求1所述的半导体器件，其特征在于，还包括：
栅极接触插塞，其穿透所述栅极盖图案、与所述栅电极接触、并且具有比所述栅极盖图案的宽度小的宽度；以及
辅助绝缘图案，其在所述保护间隔物与所述栅极接触插塞之间，所述辅助绝缘图案包括与所述保护间隔物不同的材料。
11.如权利要求1所述的半导体器件，其特征在于，还包括沟道图案，所述沟道图案包括依次堆叠在所述衬底上的第一半导体图案和第二半导体图案，
其中所述栅电极覆盖所述沟道图案的顶表面和侧表面，并且包括在所述第一半导体图案与所述第二半导体图案之间的第一栅极部分。
12.一种半导体器件，其特征在于，包括：
有源鳍，其从衬底突出并且在第一方向上延伸；
跨越所述有源鳍的栅极图案，所述栅极图案包括依次堆叠在所述衬底上的栅极绝缘层、栅电极和栅极盖图案；
栅极间隔物，其覆盖所述栅极图案的侧壁；
在所述有源鳍上的源极/漏极图案，所述源极/漏极图案邻近所述栅极图案的所述侧壁；
在所述源极/漏极图案上的接触垫；
在所述接触垫上的源极/漏极接触插塞；以及
保护间隔物，其在所述栅极间隔物与所述源极/漏极接触插塞之间，所述保护间隔物具有包围所述源极/漏极接触插塞的环形并且具有比所述栅极间隔物大的宽度。
13.如权利要求12所述的半导体器件，其特征在于，所述保护间隔物的不与所述栅极图案和所述栅极间隔物重叠的侧壁与所述接触垫的在所述栅极图案延伸的方向上的侧壁对准。
14.如权利要求12所述的半导体器件，其特征在于，所述接触垫的顶表面低于所述栅电极的顶表面。
15.如权利要求12所述的半导体器件，其特征在于，所述源极/漏极接触插塞的宽度小于所述接触垫的宽度。
CN202021369729.3U 2019-08-23 2020-07-13 半导体器件 Active CN212412061U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020190103975A KR20210024384A (ko) 2019-08-23 2019-08-23 반도체 소자 및 이의 제조 방법
KR10-2019-0103975 2019-08-23

Publications (1)

Publication Number Publication Date
CN212412061U true CN212412061U (zh) 2021-01-26

Family

ID=74405043

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202010667825.4A Pending CN112420696A (zh) 2019-08-23 2020-07-13 半导体器件和制造半导体器件的方法
CN202021369729.3U Active CN212412061U (zh) 2019-08-23 2020-07-13 半导体器件

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN202010667825.4A Pending CN112420696A (zh) 2019-08-23 2020-07-13 半导体器件和制造半导体器件的方法

Country Status (3)

Country Link
US (2) US11362196B2 (zh)
KR (1) KR20210024384A (zh)
CN (2) CN112420696A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220085857A (ko) 2020-12-15 2022-06-23 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US20230154992A1 (en) 2021-11-12 2023-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation Layers for Reducing Leakages Between Contacts

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100467023B1 (ko) * 2002-10-31 2005-01-24 삼성전자주식회사 자기 정렬 접촉 구조 및 그 형성 방법
US8436404B2 (en) * 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
US20150187945A1 (en) * 2014-01-02 2015-07-02 Globalfoundries Inc. Salicide protection during contact metallization and resulting semiconductor structures
US9312182B2 (en) 2014-06-11 2016-04-12 Globalfoundries Inc. Forming gate and source/drain contact openings by performing a common etch patterning process
US9679812B2 (en) 2014-07-24 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with self-aligned contact
US9887129B2 (en) * 2014-09-04 2018-02-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with contact plug
CN107112277B (zh) 2014-12-24 2021-03-12 英特尔公司 将过孔与密集间距金属互连层的顶和底自对准的结构和方法
KR102290538B1 (ko) * 2015-04-16 2021-08-19 삼성전자주식회사 반도체 소자 및 이의 제조 방법
KR102342079B1 (ko) * 2015-05-20 2021-12-21 삼성전자주식회사 반도체 장치 제조 방법
KR20160141034A (ko) * 2015-05-27 2016-12-08 삼성전자주식회사 반도체 소자 및 반도체 소자의 제조 방법
US9905671B2 (en) 2015-08-19 2018-02-27 International Business Machines Corporation Forming a gate contact in the active area
US9735242B2 (en) 2015-10-20 2017-08-15 Globalfoundries Inc. Semiconductor device with a gate contact positioned above the active region
US9997632B2 (en) * 2015-12-15 2018-06-12 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-type field effect transistor device and manufacturing method thereof
US9893184B2 (en) * 2015-12-15 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-type field effect transistor device and method of fabricating the same
KR102458923B1 (ko) * 2016-02-01 2022-10-25 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US10164032B2 (en) 2016-06-17 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned contact and manufacturing method thereof
US10510598B2 (en) 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned spacers and method forming same
US10164106B2 (en) * 2016-12-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US10516030B2 (en) 2017-01-09 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs and methods forming same
US10453749B2 (en) 2017-02-14 2019-10-22 Tokyo Electron Limited Method of forming a self-aligned contact using selective SiO2 deposition
KR102387465B1 (ko) 2017-03-09 2022-04-15 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102276650B1 (ko) * 2017-04-03 2021-07-15 삼성전자주식회사 반도체 소자의 제조 방법
US10115825B1 (en) * 2017-04-28 2018-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for FinFET device with asymmetric contact
US10083863B1 (en) * 2017-05-30 2018-09-25 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structure for semiconductor device
KR102283024B1 (ko) * 2017-09-01 2021-07-27 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102323733B1 (ko) * 2017-11-01 2021-11-09 삼성전자주식회사 콘택 플러그를 갖는 반도체 소자 및 그 형성 방법
US10366982B2 (en) * 2017-11-30 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure with embedded memory device and contact isolation scheme
US10943983B2 (en) * 2018-10-29 2021-03-09 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuits having protruding interconnect conductors
US11342225B2 (en) * 2019-07-31 2022-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier-free approach for forming contact plugs

Also Published As

Publication number Publication date
US20220376080A1 (en) 2022-11-24
US11362196B2 (en) 2022-06-14
US20210057538A1 (en) 2021-02-25
KR20210024384A (ko) 2021-03-05
CN112420696A (zh) 2021-02-26
US12034060B2 (en) 2024-07-09

Similar Documents

Publication Publication Date Title
US11696442B2 (en) Vertical memory devices and methods of manufacturing the same
US20230354594A1 (en) Vertical memory devices
CN110970441B (zh) 垂直存储器装置
US11705454B2 (en) Active regions via contacts having various shaped segments off-set from gate via contact
CN107919358B (zh) 半导体器件及其制造方法
CN110797345B (zh) 垂直存储器件
KR101883656B1 (ko) 활성영역과의 접촉면적이 확대된 콘택을 포함하는 반도체 소자 및 그 제조방법
CN110718502A (zh) 具有气隙的半导体器件以及用于制造其的方法
US9953985B2 (en) Method of manufacturing integrated circuit device
US10861860B2 (en) Method of manufacturing a semiconductor device
US11778826B2 (en) Vertical memory devices
US12034060B2 (en) Semiconductor device having a ring-shaped protection spacer above a contact pad and enclosing a source/drain contact plug
US20210320125A1 (en) Vertical memory devices
CN111326512A (zh) 集成电路装置
US20220102528A1 (en) Semiconductor device
US20230037646A1 (en) Semiconductor device with low k spacer and method for fabricating the same
US12068242B2 (en) Semiconductor device and method of fabricating the same
US7351625B2 (en) Recessed transistors and methods of forming the same
US20240179914A1 (en) Semiconductor device
US20230047679A1 (en) Semiconductor device and method for fabricating the semiconductor device
CN116133420A (zh) 半导体存储器件

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant