CN212324460U - Pad structure for asymmetric component of paster and printed circuit board - Google Patents
Pad structure for asymmetric component of paster and printed circuit board Download PDFInfo
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- CN212324460U CN212324460U CN202020965313.1U CN202020965313U CN212324460U CN 212324460 U CN212324460 U CN 212324460U CN 202020965313 U CN202020965313 U CN 202020965313U CN 212324460 U CN212324460 U CN 212324460U
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Abstract
The application provides a pad structure and printed circuit board for asymmetric components and parts of paster. The bonding pad structure comprises an insulating layer, a plurality of first bonding pads and a second bonding pad; the insulating layer comprises a plurality of first hollow-out areas and a plurality of second hollow-out areas which are independently arranged; the first hollow-out area and the second hollow-out area are independently arranged; the plurality of first bonding pads are respectively and correspondingly arranged in the first hollow-out areas of the insulating layer; the second bonding pad is correspondingly arranged in the second hollow-out area of the insulating layer; the first bonding pad and the second bonding pad are used for being connected with pins of the electronic component. This a pad structure for asymmetric components and parts of paster can reduce the dress and take place the probability of squint problem at electronic components on its surface.
Description
Technical Field
The utility model relates to a circuit board technical field especially relates to a pad structure and printed circuit board for asymmetric components and parts of paster.
Background
With the rapid development of the packaging technology of electronic components, the packaging of electronic components is increasingly developing towards miniaturization, but in order to solve the problem of chip heat dissipation, special heat dissipation bonding pads are designed for packaging of many electronic components.
At present, in order to achieve better heat dissipation performance, a heat dissipation pad is generally designed to be larger; however, when the electronic components are reflow-soldered, the larger heat-dissipating pad absorbs a larger amount of solder, and the electronic components mounted on the surface of the heat-dissipating pad are easily displaced.
SUMMERY OF THE UTILITY MODEL
The application provides a pad structure and printed circuit board for asymmetric components and parts of paster, this a pad structure for asymmetric components and parts of paster can reduce the dress and take place the probability of skew problem at electronic components on its surface.
In order to solve the technical problem, the application adopts a technical scheme that: a pad structure for a chip asymmetric component is provided. The bonding pad structure comprises an insulating layer, a plurality of first bonding pads and a second bonding pad; the insulating layer comprises a plurality of first hollow-out areas and a plurality of second hollow-out areas which are independently arranged; the first hollow-out area and the second hollow-out area are independently arranged; the plurality of first bonding pads are respectively and correspondingly arranged in the first hollow-out areas of the insulating layer; the second bonding pad is correspondingly arranged in the second hollow-out area of the insulating layer; the first bonding pad and the second bonding pad are used for being connected with pins of the electronic component.
The first pads are uniformly distributed at two opposite ends of the insulating layer.
The number of the first hollow-out areas is eight, each first hollow-out area is correspondingly provided with one first pad, and the shape and the size of each first pad are the same.
The first bonding pad is rectangular, square or circular.
The second hollow-out areas are positioned among the plurality of first hollow-out areas; the size of the second bonding pad is larger than that of the first bonding pad, and after the soldering tin on the second bonding pad is melted, the center of the melted soldering tin is superposed with the center of the second bonding pad.
Wherein the second pad has the same shape as the first pad.
The second bonding pad is rectangular, square or circular.
Wherein the insulating layer is a solder resist layer.
In order to solve the above technical problem, another technical solution adopted by the present application is: the printed circuit board comprises a substrate and a pad structure arranged on the substrate, wherein the pad structure is used for the surface mounted asymmetric component.
Wherein, the substrate is a core plate.
According to the pad structure for the asymmetrical chip components and the printed circuit board, the insulating layer is arranged to comprise a plurality of first hollow-out areas and a plurality of second hollow-out areas which are independently arranged through the insulating layer, the first pads are arranged at positions corresponding to the first hollow-out areas, the second pads are arranged at positions corresponding to the second hollow-out areas, the first pads and the second pads are connected with pins of the electronic components, and therefore the mounting of the electronic components is achieved, and good heat dissipation is achieved through the first pads and the second pads; meanwhile, the bonding pads connected with the pins of the electronic component in the bonding pad structure are a plurality of first bonding pads arranged independently and second bonding pads arranged independently with the first bonding pads, compared with a structure that the pins of the electronic component are directly connected with bonding pads with a large area in the prior art, the surface of each bonding pad in the bonding pad structure absorbs less soldering tin, and the soldering tin on the bonding pad at the current position is pulled by the soldering tin at other positions to move the soldering tin, so that the probability of the offset problem of the electronic component mounted on the surface of the bonding pad due to the movement of the soldering tin can be greatly reduced; in addition, each first bonding pad and each second bonding pad in the bonding pad structure are connected through the insulating layer, so that the problem of short circuit among pins of the electronic component attached to the first bonding pad and the second bonding pad can be effectively solved through the insulating layer.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a schematic structural diagram of a pad structure for a chip asymmetric component according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a pad structure for a chip asymmetric component according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. All directional indications (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are only used to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indication is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The present application will be described in detail with reference to the accompanying drawings and examples.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a pad structure for a chip asymmetric component according to an embodiment of the present application; fig. 2 is a schematic structural diagram of a pad structure for a chip asymmetric component according to another embodiment of the present application. In the present embodiment, a pad structure 10 for a chip asymmetric component is provided. The pad structure 10 includes an insulating layer 11, a plurality of first pads 12 and a second pad 13.
The insulating layer 11 comprises a plurality of independently arranged first hollow-out areas and second hollow-out areas; in a specific embodiment, the first hollow-out area and the second hollow-out area are independently arranged; the insulating layer 11 may be a solder resist layer.
Specifically, the plurality of first hollow areas are uniformly distributed at two opposite ends of the insulating layer 11; in an embodiment, the number of the first hollow-out areas is eight, four of the eight first hollow-out areas are longitudinally arranged and formed at one end of the insulating layer 11, and the other four first hollow-out areas are also longitudinally arranged and formed at the other end of the insulating layer 11.
Specifically, the second hollow-out area is positioned between the plurality of first hollow-out areas; in one embodiment, the second hollow areas are located between the first hollow areas and are offset to one side edge of the insulating layer 11.
The first pads 12 are respectively and correspondingly arranged in the first hollow areas of the insulating layer 11 and used for being connected with pins of the electronic component; in an embodiment, one first pad 12 is correspondingly disposed in each first hollow area, and the shape and the size of each first pad 12 are the same. Specifically, the shape of the first pad 12 may be rectangular, square or circular, which is not limited in this embodiment.
Specifically, a plurality of first pads 12 are uniformly distributed at two opposite ends of the insulating layer 11; in a specific embodiment, the number of the first pads 12 is eight, and four of the eight first pads 12 are disposed at one end of the insulating layer 11 in a longitudinal arrangement, and the other four first pads 12 are also disposed at the other end of the insulating layer 11 in a longitudinal arrangement.
The second pad 13 is correspondingly arranged in the second hollow-out area of the insulating layer 11 and is used for being connected with a pin of an electronic component; therefore, the mounting of the electronic component is realized through the first bonding pad 12 and the second bonding pad 13, and better heat dissipation is realized through the plurality of first bonding pads 12 and the second bonding pad 13; meanwhile, because the pads connected with the pins of the electronic component in the pad structure 10 are the first pads 12 arranged independently and the second pads 13 arranged independently from the first pads 12, compared with a structure that the pins of the electronic component are directly connected with the pads with a larger area in the prior art, the amount of solder adsorbed on the surface of each pad in the pad structure 10 is less, and the solder on the pads at other positions does not pull the solder on the pad at the current position to move the solder, so that the probability of the offset problem of the electronic component mounted on the surface of the pad structure due to the movement of the solder can be greatly reduced; in addition, since the first pads 12 and the second pads 13 in the pad structure 10 are connected through the insulating layer 11, the short circuit problem between the leads of the electronic component mounted on the first pads 12 and the second pads 13 can be effectively prevented through the insulating layer 11.
In a specific embodiment, the second pads 13 are located between the first pads 12 and are biased to one side edge of the insulating layer 11, which is distributed in a manner as shown in fig. 1 and 2. Specifically, the size of the second pad 13 is larger than that of the first pad 12, which can effectively improve the heat dissipation capability of the pad structure 10. And in one embodiment, the second pad 13 is the same shape as the first pad 12; the second pad 13 may be rectangular, square or circular.
Specifically, after the solder on the second land 13 is melted, the center of the melted solder overlaps the center of the second land 13, thereby further preventing the electronic component mounted on the land structure 10 from being displaced.
In the pad structure 10 for the asymmetric component mounted on the chip, the insulating layer 11 is arranged to include a plurality of independently arranged first hollow-out areas and a second hollow-out area, the first pads 12 are arranged at positions corresponding to the first hollow-out areas, the second pads 13 are arranged at positions corresponding to the second hollow-out areas, and the first pads 12 and the second pads 13 are connected with pins of the electronic component, so that the mounting of the electronic component is realized, and the good heat dissipation is realized through the first pads 12 and the second pads 13; meanwhile, because the pads connected with the pins of the electronic component in the pad structure 10 are the first pads 12 arranged independently and the second pads 13 arranged independently from the first pads 12, compared with a structure that the pins of the electronic component are directly connected with the pads with a larger area in the prior art, the amount of solder adsorbed on the surface of each pad in the pad structure 10 is less, and the solder on the pads at other positions does not pull the solder on the pad at the current position to move the solder, so that the probability of the offset problem of the electronic component mounted on the surface of the pad structure due to the movement of the solder can be greatly reduced; in addition, since the first pads 12 and the second pads 13 in the pad structure 10 are connected through the insulating layer 11, the short circuit problem between the leads of the electronic component mounted on the first pads 12 and the second pads 13 can be effectively prevented through the insulating layer 11.
In the present embodiment, a printed circuit board is provided, which specifically includes a substrate and a pad structure.
Wherein, the substrate can be a core plate; in one embodiment, the core board may be a copper clad board, the copper clad board is a base material for manufacturing the circuit board, and includes a base material board and a copper foil covered on the base material board, the base material board is made by impregnating materials such as a paper substrate, a glass fiber cloth substrate, a synthetic fiber cloth substrate, a non-woven fabric substrate, a composite substrate, etc. with resin to make a bonding sheet, and is made by combining a plurality of bonding sheets, the single side or double sides of the manufactured base material board are covered with the copper foil, and then the copper clad board is manufactured by hot-pressing and curing.
Specifically, the core board is provided with a circuit layer to communicate with each electronic component attached to the core board.
The pad structure may be specifically the pad structure 10 according to the above embodiment, which is taken as an example in the following embodiment; specifically, the pad structure 10 is specifically disposed on the substrate and electrically connected to the circuit layer on the substrate; the pad structure 10 is specifically used for being connected to a pin of an electronic component, so as to communicate the electronic component with a circuit layer on a substrate.
Specifically, the pad structure 10 includes an insulating layer 11, a plurality of first pads 12, and a second pad 13.
The insulating layer 11 comprises a plurality of independently arranged first hollow-out areas and second hollow-out areas; in a specific embodiment, the first hollow-out area and the second hollow-out area are independently arranged; the insulating layer 11 may be a solder resist layer.
Specifically, the plurality of first hollow areas are uniformly distributed at two opposite ends of the insulating layer 11; in an embodiment, the number of the first hollow-out areas is eight, four of the eight first hollow-out areas are longitudinally arranged and formed at one end of the insulating layer 11, and the other four first hollow-out areas are also longitudinally arranged and formed at the other end of the insulating layer 11.
Specifically, the second hollow-out area is positioned between the plurality of first hollow-out areas; in one embodiment, the second hollow areas are located between the first hollow areas and are offset to one side edge of the insulating layer 11.
The first pads 12 are respectively and correspondingly arranged in the first hollow areas of the insulating layer 11 and used for being connected with pins of the electronic component; in an embodiment, one first pad 12 is correspondingly disposed in each first hollow area, and the shape and the size of each first pad 12 are the same. Specifically, the shape of the first pad 12 may be rectangular, square or circular, which is not limited in this embodiment.
Specifically, a plurality of first pads 12 are uniformly distributed at two opposite ends of the insulating layer 11; in a specific embodiment, the number of the first pads 12 is eight, and four of the eight first pads 12 are disposed at one end of the insulating layer 11 in a longitudinal arrangement, and the other four first pads 12 are also disposed at the other end of the insulating layer 11 in a longitudinal arrangement.
The second pad 13 is correspondingly arranged in the second hollow-out area of the insulating layer 11 and is used for being connected with a pin of an electronic component; therefore, the mounting of the electronic component is realized through the first bonding pad 12 and the second bonding pad 13, and better heat dissipation is realized through the plurality of first bonding pads 12 and the second bonding pad 13; meanwhile, because the pads connected with the pins of the electronic component in the pad structure 10 are the first pads 12 arranged independently and the second pads 13 arranged independently from the first pads 12, compared with a structure that the pins of the electronic component are directly connected with the pads with a larger area in the prior art, the amount of solder adsorbed on the surface of each pad in the pad structure 10 is less, and the solder on the pads at other positions does not pull the solder on the pad at the current position to move the solder, so that the probability of the offset problem of the electronic component mounted on the surface of the pad structure due to the movement of the solder can be greatly reduced; in addition, since the first pads 12 and the second pads 13 in the pad structure 10 are connected through the insulating layer 11, the insulating layer 11 can effectively prevent the short circuit between the leads of the electronic component mounted on the first pads 12 and the second pads 13.
In a specific embodiment, the second pads 13 are located between the first pads 12 and are biased to one side edge of the insulating layer 11, which is distributed in a manner as shown in fig. 1 and 2. Specifically, the size of the second pad 13 is larger than that of the first pad 12, which can effectively improve the heat dissipation capability of the pad structure 10. And in one embodiment, the second pad 13 is the same shape as the first pad 12; the second pad 13 may be rectangular, square or circular.
Specifically, after the solder on the second land 13 is melted, the center of the melted solder overlaps the center of the second land 13, thereby further preventing the electronic component mounted on the land structure 10 from being displaced.
Specifically, when the pad structure 10 is disposed on a substrate, the first pad 12 and the second pad 13 respectively correspond to positions of a circuit layer on the substrate, so that the electronic component mounted on the surface thereof is communicated with the circuit layer through the first pad 12 and the second pad 13.
In the printed circuit board provided by the embodiment, by arranging the substrate, the pad structure 10 for mounting the asymmetric component is arranged on the substrate, the pad structure 10 is arranged to include the insulating layer 11, the insulating layer 11 is arranged to include a plurality of independently arranged first hollow areas and a second hollow area, a plurality of first pads 12 are arranged at positions corresponding to the first hollow areas, and second pads 13 are arranged at positions corresponding to the second hollow areas, so that the first pads 12 and the second pads 13 are connected with pins of the electronic component, thereby realizing mounting of the electronic component, and realizing better heat dissipation through the plurality of first pads 12 and the second pads 13; meanwhile, because the pads connected with the pins of the electronic component in the pad structure 10 are the first pads 12 arranged independently and the second pads 13 arranged independently from the first pads 12, compared with a structure that the pins of the electronic component are directly connected with the pads with a larger area in the prior art, the amount of solder adsorbed on the surface of each pad in the pad structure 10 is less, and the solder on the pads at other positions does not pull the solder on the pad at the current position to move the solder, so that the probability of the offset problem of the electronic component mounted on the surface of the pad structure due to the movement of the solder can be greatly reduced; in addition, since the first pads 12 and the second pads 13 in the pad structure 10 are connected through the insulating layer 11, the short circuit problem between the leads of the electronic component mounted on the first pads 12 and the second pads 13 can be effectively prevented through the insulating layer 11.
The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.
Claims (10)
1. A pad structure for asymmetric components of paster characterized in that includes:
the insulating layer comprises a plurality of independently arranged first hollow-out areas and second hollow-out areas; the first hollow-out area and the second hollow-out area are independently arranged;
the first bonding pads are respectively and correspondingly arranged in the first hollow-out areas of the insulating layer; and the number of the first and second groups,
the second bonding pad is correspondingly arranged in the second hollow-out area of the insulating layer; the first bonding pad and the second bonding pad are used for being connected with pins of an electronic component.
2. The pad structure for the asymmetric component mounted on the chip as claimed in claim 1, wherein the first pads are uniformly distributed at two opposite ends of the insulating layer.
3. The pad structure for the asymmetric component mounted on a chip as claimed in claim 1, wherein the number of the first hollowed-out areas is eight, each first hollowed-out area is provided with one first pad, and the shape and size of each first pad are the same.
4. The pad structure for the asymmetric component of patch according to claim 3, wherein said first pad is rectangular, square or circular.
5. The pad structure for the asymmetric component of patch according to claim 1, wherein the second hollowed-out area is located at a position between the first hollowed-out areas;
the size of the second bonding pad is larger than that of the first bonding pad, and after the soldering tin on the second bonding pad is melted, the center of the melted soldering tin is superposed with the center of the second bonding pad.
6. The pad structure for the asymmetric component on the chip as recited in claim 5, wherein the second pad is the same shape as the first pad.
7. The pad structure for the asymmetric component mounted on a chip as claimed in claim 5, wherein the second pad is rectangular, square or circular.
8. A pad structure for asymmetric component mounting according to any of claims 1 to 7, wherein the insulating layer is a solder resist layer.
9. A printed circuit board comprising a substrate and a pad structure disposed on the substrate, wherein the pad structure is the pad structure for a chip asymmetric component as claimed in any one of claims 1 to 8.
10. The printed circuit board of claim 9, wherein the substrate is a core.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020965313.1U CN212324460U (en) | 2020-05-30 | 2020-05-30 | Pad structure for asymmetric component of paster and printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020965313.1U CN212324460U (en) | 2020-05-30 | 2020-05-30 | Pad structure for asymmetric component of paster and printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212324460U true CN212324460U (en) | 2021-01-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020965313.1U Active CN212324460U (en) | 2020-05-30 | 2020-05-30 | Pad structure for asymmetric component of paster and printed circuit board |
Country Status (1)
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|---|---|
| CN (1) | CN212324460U (en) |
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- 2020-05-30 CN CN202020965313.1U patent/CN212324460U/en active Active
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