CN211629119U - Diode with junction barrier Schottky structure - Google Patents

Diode with junction barrier Schottky structure Download PDF

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CN211629119U
CN211629119U CN201922355717.9U CN201922355717U CN211629119U CN 211629119 U CN211629119 U CN 211629119U CN 201922355717 U CN201922355717 U CN 201922355717U CN 211629119 U CN211629119 U CN 211629119U
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epitaxial layer
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contact electrode
schottky
substrate
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郑柳
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Chongqing Weitesen Electronic Technology Co ltd
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Chongqing Weitesen Electronic Technology Co ltd
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Abstract

A structure of a junction barrier Schottky structure diode specifically comprises: a substrate of a first conductivity type; an epitaxial layer of a first conductive type is arranged on the upper surface of the substrate, and a buffer layer of the first conductive type is arranged between the substrate and the epitaxial layer; a Schottky contact electrode arranged on the upper surface of the epitaxial layer; an ohmic contact electrode is arranged on the lower surface of the substrate, and a second isolation medium layer is arranged between the substrate and the ohmic contact electrode; the second conductive type well regions are arranged on two sides of the upper surface of the epitaxial layer; first isolation medium layers which correspond to the second conductive type well regions and are equal in width are arranged on two sides of the lower surface of the Schottky contact electrode; the utility model discloses combine schottky diode and Pin structure together, get rid of the restriction of tunneling current to the highest blocking voltage through the PN junction barrier for Junction Barrier Schottky (JBS) structure is compared in Schottky (SBD) device, under reverse mode, can have lower reverse leakage current on the basis that does not sacrifice forward conduction voltage drop, and higher blocking voltage.

Description

Diode with junction barrier Schottky structure
Technical Field
The utility model relates to the field of semiconductor technology, in particular to diode of junction barrier schottky structure.
Background
A Schottky Barrier Diode (SBD) is a low-power consumption and ultra-high speed semiconductor device, and because the Schottky barrier height is lower than the PN junction barrier height, the forward conduction threshold voltage and the forward voltage drop of the Schottky barrier diode are lower than those of the PN junction diode. SBD is also a majority carrier conducting device, without minority carrier lifetime and reverse recovery problems, and because its reverse recovery charge is very small, switching speed is very fast, switching losses are also very small, especially suitable for high frequency applications.
The reverse barrier of the Schottky diode is thin, and breakdown is easy to occur on the surface of the Schottky diode, so that the reverse breakdown voltage is lower, thermal breakdown is easy, and the reverse leakage current is larger than that of a PN junction diode, so that the SBD is difficult to apply to the high-voltage field. However, in a high-frequency circuit, the reverse recovery time of the PiN diode is long, the peak current is large, and the energy consumption is high.
SUMMERY OF THE UTILITY MODEL
To the above feature, the utility model provides a diode of SiC junction barrier schottky structure with low forward breakover voltage, high reverse breakdown voltage.
For realizing the purpose of the utility model, the technical proposal adopted is that:
a diode of a junction barrier Schottky structure, comprising the following structure:
a SiC substrate of a first conductivity type;
a SiC epitaxial layer made of a first conductive type is arranged on the upper surface of the SiC substrate, and a SiC buffer layer made of a first conductive type is arranged between the SiC substrate and the SiC epitaxial layer;
a Schottky contact electrode is arranged on the upper surface of the SiC epitaxial layer; an ohmic contact electrode is arranged on the lower surface of the SiC substrate, and a second isolation medium layer is arranged between the SiC substrate and the ohmic contact electrode;
second conductive type well regions are arranged on two sides of the upper surface of the SiC epitaxial layer, and the surfaces of the second conductive type well regions are flush with the upper surface of the SiC epitaxial layer;
first isolation dielectric layers which correspond to the second conduction type well regions and are equal in width are arranged on two sides of the lower surface of the Schottky contact electrode, and the interface of the Schottky contact electrode and the SiC epitaxial layer is overlapped with the interface of the second conduction type well regions and the first isolation dielectric layers;
further, the second conductive type well region planar graph structure is one or more of rectangle, circle, ring, hexagon, pentagon, and the thickness of the above-mentioned well region graph is 0.1um-500um, and the side length size is 0.1um-30um, and the interval of graph is 0.1um-30 um.
Adopt the utility model discloses a preparation method combines schottky diode and Pin structure together, gets rid of the restriction of tunneling current to the highest blocking voltage through the PN junction barrier, has combined advantage between them for the Junction Barrier Schottky (JBS) structure is compared in Schottky (SBD) device, under reverse mode, can have lower reverse leakage current on the basis that does not sacrifice forward conduction voltage drop, and higher blocking voltage.
Drawings
Fig. 1 is a structural diagram of a diode having a junction barrier schottky structure according to the present invention.
Fig. 2 is another structure diagram of a diode having a junction barrier schottky structure according to the present invention.
A SiC substrate; 02, SiC buffer layer; 03. an epitaxial layer of SiC; 04. doping the well region; 05. 06, 07, 08 metal or other conductive material; 10. metal or silicon dioxide, polysilicon, amorphous silicon, silicon nitride, and the like.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the objects of the present invention, the diode according to the junction barrier schottky structure of the present invention will be described in detail with reference to the accompanying drawings and the following detailed description.
Example 1
Referring to fig. 1, a diode with a junction barrier schottky structure is characterized by comprising the following structures:
a SiC substrate 01 of a first conductivity type;
a SiC epitaxial layer 03 made of a first conductive type is arranged on the upper surface of the SiC substrate 01, and a SiC buffer layer 02 made of a first conductive type is arranged between the SiC substrate 01 and the SiC epitaxial layer 03;
a Schottky contact electrode 06 is arranged on the upper surface of the SiC epitaxial layer 03; an ohmic contact electrode 08 is arranged on the lower surface of the SiC substrate 01, and a second isolation dielectric layer 07 is arranged between the SiC substrate 01 and the ohmic contact electrode 08;
second conduction type well regions 04 are arranged on two sides of the upper surface of the SiC epitaxial layer 03, and the surfaces of the second conduction type well regions 04 are flush with the upper surface of the SiC epitaxial layer 03;
first isolation dielectric layers 05 which correspond to the second conduction type well regions 04 and are equal in width are arranged on two sides of the lower surface of the Schottky contact electrode 06, and the interface of the Schottky contact electrode 06 and the SiC epitaxial layer 03 and the interface of the second conduction type well regions 04 and the first isolation dielectric layers 05 are overlapped.
The diode based on the junction barrier Schottky structure comprises the following specific manufacturing steps:
step 1: selecting a SiC substrate 01, growing a SiC epitaxial layer 03 on the upper surface of the SiC substrate 01, and growing a SiC buffer layer 02 between the SiC substrate 01 and the SiC epitaxial layer 03;
step 2: forming second conductivity type well regions 04 on two sides of the upper surface of the SiC epitaxial layer 03;
and step 3: a first isolation dielectric layer 05 with the same width as the second conductive type well region 04 is formed on the upper surface of the second conductive type well region 04;
and 4, step 4: a Schottky contact electrode 06 covering the first isolation dielectric layer 05 and the SiC epitaxial layer 03 is formed above the SiC epitaxial layer 03;
and 5: an ohmic contact electrode 08 is formed below the SiC substrate 01 and a second insulating dielectric layer 07 located between the SiC substrate 01 and the ohmic contact electrode 08 is formed.
Further, the thicknesses of the SiC substrate 01 and the SiC epitaxial layer 03 are both 0-500 um; the thickness of the SiC buffer layer 02 is 0um-50 um; the thickness of the second conductive type well region 04 is 0.1um-500 um; the thicknesses of the films of the first isolation dielectric layer 05, the Schottky contact electrode 06, the second isolation dielectric layer 07 and the ohmic contact electrode 08 are all 0.001-10 um.
Further, the doping concentrations of the SiC substrate 01 and the SiC buffer layer 02 are both 1010～1022um-3(ii) a The doping concentration of the SiC epitaxial layer 03 is 1010～1019um-3(ii) a The doping distribution of the SiC substrate 01, the SiC buffer layer 02 and the SiC epitaxial layer 03 is single doping or gradient doping or step doping.
Further, the crystal forms of the SiC substrate 01, the SiC buffer layer 02 and the SiC epitaxial layer 03 are 4H or 6H; the first conductivity type is n-type, and the second conductivity type is p-type; the materials of the first isolation dielectric layer 05, the Schottky contact electrode 06, the second isolation dielectric layer 07 and the ohmic contact electrode 08 are all metal or other conductive materials.
Further, the planar graph structure of the well region 04 of the second conductive type is one or more of rectangle, circle, ring, hexagon and pentagon, the side length of the graph of the well region 04 is 0.1um-30um, the interval of the graph of the well region is 0.1um-30um, and the thickness of the well region is 0.1um-500 um.
Further, the conductive material 10 is metal or one or more of silicon dioxide, polysilicon, amorphous silicon and silicon nitride, and the doping type of the polysilicon and the amorphous silicon is p-type doping with a doping concentration of 1010um-3。
Further, the SiC substrate 01 is grown by physical vapor deposition ((PVD) or Chemical Vapor Deposition (CVD)), and the SiC buffer layer 02 is grown by Chemical Vapor Deposition (CVD).
Further, the second conductivity type well region 04 is formed by ion implantation and re-etching or secondary epitaxy after etching or ion implantation after etching.
Further, high-temperature treatment processes are carried out between the first isolation dielectric layer 05 and the surface of the second conduction type well region 04, between the Schottky contact electrode 06 and the surface of the SiC epitaxial layer 03, between the second isolation dielectric layer 07 and the surface of the SiC substrate 01, and between the ohmic contact electrode 08 and the surface of the second isolation dielectric layer 07, wherein the treatment modes comprise Rapid Thermal Annealing (RTA) or Laser Annealing (LA) or a high-temperature furnace; the gas atmosphere in the treatment process is a vacuum environment or a nitrogen and inert gas atmosphere, and the inert gas is preferably argon.
Example 2
Referring to fig. 2, a diode with a junction barrier schottky structure is characterized by comprising the following structures:
a SiC epitaxial layer 03 made of a first conductive type is arranged on the upper surface of the SiC substrate 01, and a SiC buffer layer 02 made of a first conductive type is arranged between the SiC substrate 01 and the SiC epitaxial layer 03;
a Schottky contact electrode 06 is arranged on the upper surface of the SiC epitaxial layer 03; an ohmic contact electrode 08 is arranged on the lower surface of the SiC substrate 01, and a second isolation dielectric layer 07 is arranged between the SiC substrate 01 and the ohmic contact electrode 08;
second conduction type well regions 04 are arranged on two sides of the upper surface of the epitaxial layer 03, conductive materials 10 are filled in the second conduction type well regions 04, and the upper surfaces of the second conduction type well regions 04, the upper surfaces of the conductive materials 10 and the upper surface of the SiC epitaxial layer 03 are flush;
first isolation dielectric layers 05 which correspond to the second conduction type well regions 04 and are equal in width are arranged on two sides of the lower surface of the Schottky contact electrode 06, and the interface of the Schottky contact electrode 06 and the epitaxial layer 03 and the interface of the second conduction type well regions 04 and the first isolation dielectric layers 05 are overlapped.
The diode based on the junction barrier Schottky structure comprises the following specific manufacturing steps:
step 1: selecting a SiC substrate 01, growing a SiC epitaxial layer 03 on the upper surface of the SiC substrate 01, and growing a SiC buffer layer 02 between the SiC substrate 01 and the first conductive type epitaxial layer 03;
step 2: forming second conductivity type semiconductors 04 on two sides of the upper surface of the SiC epitaxial layer 03, forming a trench in the second conductivity type semiconductors 04, and filling a conductive material 10;
and step 3: a first isolation dielectric layer 05 with the same width as the second conductive type well region 04 is formed on the upper surfaces of the second conductive type well region 04 and the conductive material 10;
and 4, step 4: a Schottky contact electrode 06 covering the first isolation dielectric layer 05 and the SiC epitaxial layer 03 is formed above the SiC epitaxial layer 03;
and 5: an ohmic contact electrode 08 is formed below the SiC substrate 01 and a second insulating dielectric layer 07 located between the SiC substrate 01 and the ohmic contact electrode 08 is formed.
Further, the thicknesses of the SiC substrate 01 and the SiC epitaxial layer 03 are both 0-500 um; the thickness of the SiC buffer layer 02 is 0um-50 um; the thickness of the second conductive type well region 04 is 0.1um-500 um; the thicknesses of the films of the first isolation dielectric layer 05, the Schottky contact electrode 06, the second isolation dielectric layer 07 and the ohmic contact electrode 08 are all 0.001-10 um.
Further, the doping concentrations of the SiC substrate 01 and the SiC buffer layer 02 are both 1010～1022um-3(ii) a The doping concentration of the SiC epitaxial layer 03 is 1010～1019um-3(ii) a The doping distribution of the SiC substrate 01, the SiC buffer layer 02 and the SiC epitaxial layer 03 is single doping or gradient doping or step doping.
Further, the crystal forms of the SiC substrate 01, the SiC buffer layer 02 and the SiC epitaxial layer 03 are 4H or 6H; the first conductivity type is n-type, and the second conductivity type is p-type; the materials of the first isolation dielectric layer 05, the Schottky contact electrode 06, the second isolation dielectric layer 07 and the ohmic contact electrode 08 are all metal or other conductive materials.
Further, the planar graph structure of the well region 04 of the second conductive type is one or more of rectangle, circle, ring, hexagon and pentagon, the side length of the graph of the well region 04 is 0.1um-30um, the interval of the graph of the well region is 0.1um-30um, and the thickness of the well region is 0.1um-500 um.
Further, the conductive material 10 is metal or one or more of silicon dioxide, polysilicon, amorphous silicon and silicon nitride, and the doping type of the polysilicon and the amorphous silicon is p-type doping with a doping concentration of 1010um-3。
Further, the SiC substrate 01 is grown by physical vapor deposition ((PVD) or Chemical Vapor Deposition (CVD)), and the SiC buffer layer 02 is grown by Chemical Vapor Deposition (CVD).
Further, the second conductivity type well region 04 is formed by ion implantation and re-etching or secondary epitaxy after etching or ion implantation after etching.
Further, high-temperature treatment processes are carried out between the first isolation dielectric layer 05 and the surface of the second conduction type well region 04, between the Schottky contact electrode 06 and the surface of the SiC epitaxial layer 03, between the second isolation dielectric layer 07 and the surface of the SiC substrate 01, and between the ohmic contact electrode 08 and the surface of the second isolation dielectric layer 07, wherein the treatment modes comprise Rapid Thermal Annealing (RTA) or Laser Annealing (LA) or a high-temperature furnace; the gas atmosphere in the treatment process is a vacuum environment or a nitrogen and inert gas atmosphere, and the inert gas is preferably argon.
After carrying out the experiment under the same environment, will the technical scheme of the utility model and ordinary schottky diode experimental data contrast, have as follows:
Figure DEST_PATH_GDA0002633665470000051
the following conclusions can be drawn from the comparative analysis of the data:
compared with a Schottky device, the junction barrier Schottky structure has the advantages that under the reverse mode, on the basis of not sacrificing forward conduction voltage drop, the junction barrier Schottky structure has lower reverse leakage current and higher blocking voltage.
The above-mentioned embodiments further describe the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above description is only a specific implementation method of the present invention, and is not intended to limit the present invention, and any modifications, equivalent substitutions and improvements made within the spirit of the present invention should be included in the protection scope of the present invention.

Claims (3)

1. A diode of a junction barrier Schottky structure, comprising the following structure:
a SiC substrate (01) of a material of a first conductivity type;
a SiC epitaxial layer (03) made of a first conductive type is arranged on the upper surface of the SiC substrate (01), and a SiC buffer layer (02) made of the first conductive type is arranged between the SiC substrate (01) and the SiC epitaxial layer (03);
a Schottky contact electrode (06) is arranged on the upper surface of the SiC epitaxial layer (03); an ohmic contact electrode (08) is arranged on the lower surface of the SiC substrate (01), and a second isolation dielectric layer (07) is arranged between the SiC substrate (01) and the ohmic contact electrode (08);
second conductive type well regions (04) are arranged on two sides of the upper surface of the SiC epitaxial layer (03), and the surfaces of the second conductive type well regions (04) are flush with the upper surface of the SiC epitaxial layer (03);
first isolation dielectric layers (05) which correspond to the second conduction type well regions (04) and are equal in width are arranged on two sides of the lower surface of the Schottky contact electrode (06), and the interface of the Schottky contact electrode (06) and the SiC epitaxial layer (03) is overlapped with the interface of the second conduction type well regions (04) and the first isolation dielectric layers (05);
the planar graph structure of the second conductive type well region (04) is one or more of rectangle, circle, ring, hexagon and pentagon, the thickness of the well region graph is 0.1um-500um, the side length size is 0.1um-30um, and the distance of the graph is 0.1um-30 um.
2. The diode of a junction barrier schottky structure of claim 1, wherein:
the crystal forms of the SiC substrate (01), the SiC buffer layer (02) and the SiC epitaxial layer (03) are 4H or 6H; the first conductivity type is n-type, and the second conductivity type is p-type; the materials of the first isolation dielectric layer (05), the Schottky contact electrode (06), the second isolation dielectric layer (07) and the ohmic contact electrode (08) are all metal or conductive materials.
3. The diode of the junction barrier schottky structure according to claim 1 or 2, characterized in that: and a groove is further formed in the upper surface of the second conduction type well region (04), a conductive material (10) is filled in the groove, and the upper surface of the second conduction type well region (04), the upper surface of the SiC epitaxial layer (03) and the upper surface of the conductive material (10) are flush.
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