CN111029410A - Diode with junction barrier Schottky structure and manufacturing method thereof - Google Patents
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- 238000000034 method Methods 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000005224 laser annealing Methods 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000004151 rapid thermal annealing Methods 0.000 claims description 6
- 239000011261 inert gas Substances 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims description 3
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- 230000015556 catabolic process Effects 0.000 description 5
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Abstract
A junction barrier Schottky structure diode and a preparation method thereof comprise the following steps: 1, selecting a SiC substrate with a SiC epitaxial layer, wherein a SiC buffer layer is arranged between the SiC substrate and the SiC epitaxial layer; 2, forming second conductive type well regions on two sides of the upper surface of the SiC epitaxial layer, wherein the well regions can be filled with conductive materials; 3 a first isolation medium layer is formed on the upper surface of the second conductive type well region; 4 forming a Schottky contact electrode covering the first isolation medium layer and the SiC epitaxial layer above the SiC epitaxial layer; and 5, forming an ohmic contact electrode below the SiC substrate and forming a second isolation medium layer between the ohmic contact electrode and the SiC substrate. The Schottky diode and the Pin structure are combined together, and the limitation of tunneling current on the highest blocking voltage is eliminated through the PN junction barrier, so that the Junction Barrier Schottky (JBS) structure has lower reverse leakage current and higher blocking voltage compared with a Schottky (SBD) device under the reverse mode without sacrificing forward conduction voltage drop.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a diode with a junction barrier Schottky structure and a manufacturing method thereof.
Background
A Schottky Barrier Diode (SBD) is a low-power consumption and ultra-high speed semiconductor device, and because the Schottky barrier height is lower than the PN junction barrier height, the forward conduction threshold voltage and the forward voltage drop of the Schottky barrier diode are lower than those of the PN junction diode. SBD is also a majority carrier conducting device, without minority carrier lifetime and reverse recovery problems, and because its reverse recovery charge is very small, switching speed is very fast, switching losses are also very small, especially suitable for high frequency applications.
The reverse barrier of the Schottky diode is thin, and breakdown is easy to occur on the surface of the Schottky diode, so that the reverse breakdown voltage is lower, thermal breakdown is easy, and the reverse leakage current is larger than that of a PN junction diode, so that the SBD is difficult to apply to the high-voltage field. However, in a high-frequency circuit, the reverse recovery time of the PiN diode is long, the peak current is large, and the energy consumption is high.
Disclosure of Invention
Aiming at the characteristics, the invention provides the SiC junction barrier Schottky diode with low forward conduction voltage and high reverse breakdown voltage and the preparation method thereof.
The technical scheme adopted for realizing the purpose of the invention is as follows:
a junction barrier Schottky structure diode comprising the structure:
a SiC substrate of a first conductivity type;
a SiC epitaxial layer made of a first conductive type is arranged on the upper surface of the SiC substrate, and a SiC buffer layer made of a first conductive type is arranged between the SiC substrate and the SiC epitaxial layer;
a Schottky contact electrode is arranged on the upper surface of the SiC epitaxial layer; an ohmic contact electrode is arranged on the lower surface of the SiC substrate, and a second isolation medium layer is arranged between the SiC substrate and the ohmic contact electrode;
second conductive type well regions are arranged on two sides of the upper surface of the SiC epitaxial layer, and the surfaces of the second conductive type well regions are flush with the upper surface of the SiC epitaxial layer;
first isolation dielectric layers which correspond to the second conduction type well regions and are equal in width are arranged on two sides of the lower surface of the Schottky contact electrode, and the interface of the Schottky contact electrode and the SiC epitaxial layer is overlapped with the interface of the second conduction type well regions and the first isolation dielectric layers;
further, the second conductive type well region planar graph structure is one or more of rectangle, circle, ring, hexagon, pentagon, and the thickness of the above-mentioned well region graph is 0.1um-500um, and the side length size is 0.1um-30um, and the interval of graph is 0.1um-30 um.
The manufacturing method of the diode based on the junction barrier Schottky structure comprises the following steps:
step 1: selecting a SiC substrate to grow a SiC epitaxial layer on the upper surface of the SiC substrate, and simultaneously growing a SiC buffer layer between the SiC substrate and the SiC epitaxial layer;
step 2: forming second conductive type well regions on two sides of the upper surface of the SiC epitaxial layer;
and step 3: a first isolation medium layer with the same width as the second conductive type well region is formed on the upper surface of the second conductive type well region;
and 4, step 4: forming a Schottky contact electrode covering the first isolation dielectric layer and the SiC epitaxial layer above the SiC epitaxial layer;
and 5: an ohmic contact electrode is formed below the SiC substrate and a second insulating dielectric layer is formed between the SiC substrate and the ohmic contact electrode.
Further, the following steps are included between step S3 and step S4:
and etching the upper surface of the second conductivity type well region to form a groove, filling a conductive material in the groove, and leveling the upper surface of the second conductivity type well region, the upper surface of the SiC epitaxial layer and the upper surface of the conductive material.
By adopting the preparation method, the Schottky diode and the Pin structure are combined together, the limitation of tunneling current to the highest blocking voltage is eliminated through the PN junction barrier, and the advantages of the Schottky diode and the Pin structure are combined, so that the Junction Barrier Schottky (JBS) structure has lower reverse leakage current and higher blocking voltage on the basis of not sacrificing forward conduction voltage drop in a reverse mode compared with a Schottky (SBD) device.
Drawings
Fig. 1 is a structural view of a junction barrier schottky structure diode formed without step a 1.
Fig. 2 is a structural diagram of a junction barrier schottky structure diode formed in step a 1.
A SiC substrate; 02, SiC buffer layer; 03. an epitaxial layer of SiC; 04. doping the well region; 05. 06, 07, 08 metal or other conductive material; 10. metal or silicon dioxide, polysilicon, amorphous silicon, silicon nitride, and the like.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, the junction barrier schottky structure diode according to the present invention will be described in detail with reference to the accompanying drawings and the detailed description.
Example 1
Referring to fig. 1, a junction barrier schottky structure diode is characterized by comprising the following structures:
a SiC substrate 01 of a first conductivity type;
a SiC epitaxial layer 03 made of a first conductive type is arranged on the upper surface of the SiC substrate 01, and a SiC buffer layer 02 made of a first conductive type is arranged between the SiC substrate 01 and the SiC epitaxial layer 03;
a Schottky contact electrode 06 is arranged on the upper surface of the SiC epitaxial layer 03; an ohmic contact electrode 08 is arranged on the lower surface of the SiC substrate 01, and a second isolation dielectric layer 07 is arranged between the SiC substrate 01 and the ohmic contact electrode 08;
second conduction type well regions 04 are arranged on two sides of the upper surface of the SiC epitaxial layer 03, and the surfaces of the second conduction type well regions 04 are flush with the upper surface of the SiC epitaxial layer 03;
first isolation dielectric layers 05 which correspond to the second conduction type well regions 04 and are equal in width are arranged on two sides of the lower surface of the Schottky contact electrode 06, and the interface of the Schottky contact electrode 06 and the SiC epitaxial layer 03 and the interface of the second conduction type well regions 04 and the first isolation dielectric layers 05 are overlapped.
The diode with the junction barrier Schottky structure comprises the following specific manufacturing steps:
step 1: selecting a SiC substrate 01, growing a SiC epitaxial layer 03 on the upper surface of the SiC substrate 01, and growing a SiC buffer layer 02 between the SiC substrate 01 and the SiC epitaxial layer 03;
step 2: forming second conductivity type well regions 04 on two sides of the upper surface of the SiC epitaxial layer 03;
and step 3: a first isolation dielectric layer 05 with the same width as the second conductive type well region 04 is formed on the upper surface of the second conductive type well region 04;
and 4, step 4: a Schottky contact electrode 06 covering the first isolation dielectric layer 05 and the SiC epitaxial layer 03 is formed above the SiC epitaxial layer 03;
and 5: an ohmic contact electrode 08 is formed below the SiC substrate 01 and a second insulating dielectric layer 07 located between the SiC substrate 01 and the ohmic contact electrode 08 is formed.
Further, the thicknesses of the SiC substrate 01 and the SiC epitaxial layer 03 are both 0-500 um; the thickness of the SiC buffer layer 02 is 0um-50 um; the thickness of the second conductive type well region 04 is 0.1um-500 um; the thicknesses of the first isolation dielectric layer 05, the Schottky contact electrode 06, the second isolation dielectric layer 07 and the ohmic contact electrode 08 are all 0.001-10 um.
Further, the doping concentrations of the SiC substrate 01 and the SiC buffer layer 02 are both 1010~1022um-3(ii) a The doping concentration of the SiC epitaxial layer 03 is 1010~1019um-3(ii) a The doping distribution of the SiC substrate 01, the SiC buffer layer 02 and the SiC epitaxial layer 03 is single doping or gradient doping or step doping.
Further, the crystal forms of the SiC substrate 01, the SiC buffer layer 02 and the SiC epitaxial layer 03 are 4H or 6H; the first conductivity type is n-type, and the second conductivity type is p-type; the materials of the first isolation dielectric layer 05, the Schottky contact electrode 06, the second isolation dielectric layer 07 and the ohmic contact electrode 08 are all metal or other conductive materials.
Further, the planar graph structure of the well region 04 of the second conductive type is one or more of rectangle, circle, ring, hexagon and pentagon, the side length of the graph of the well region 04 is 0.1um-30um, the interval of the graph of the well region is 0.1um-30um, and the thickness of the well region is 0.1um-500 um.
Further, the conductive material 10 is metal or one or more of silicon dioxide, polysilicon, amorphous silicon and silicon nitrideThe doping type of the polycrystalline silicon and the amorphous silicon is p-type doping, and the doping concentration is 1010~1022um-3。
Further, the SiC substrate 01 is grown by physical vapor deposition ((PVD) or Chemical Vapor Deposition (CVD)), and the SiC buffer layer 02 is grown by Chemical Vapor Deposition (CVD).
Further, the second conductivity type well region 04 is formed by ion implantation and re-etching or secondary epitaxy after etching or ion implantation after etching.
Further, high-temperature treatment processes are carried out between the first isolation dielectric layer 05 and the surface of the second conduction type well region 04, between the Schottky contact electrode 06 and the surface of the SiC epitaxial layer 03, between the second isolation dielectric layer 07 and the surface of the SiC substrate 01, and between the ohmic contact electrode 08 and the surface of the second isolation dielectric layer 07, wherein the treatment modes comprise Rapid Thermal Annealing (RTA) or Laser Annealing (LA) or a high-temperature furnace; the gas atmosphere in the treatment process is a vacuum environment or a nitrogen and inert gas atmosphere, and the inert gas is preferably argon.
Example 2
Referring to fig. 2, a junction barrier schottky structure diode is characterized by comprising the following structures:
a SiC epitaxial layer 03 made of a first conductive type is arranged on the upper surface of the SiC substrate 01, and a SiC buffer layer 02 made of a first conductive type is arranged between the SiC substrate 01 and the SiC epitaxial layer 03;
a Schottky contact electrode 06 is arranged on the upper surface of the SiC epitaxial layer 03; an ohmic contact electrode 08 is arranged on the lower surface of the SiC substrate 01, and a second isolation dielectric layer 07 is arranged between the SiC substrate 01 and the ohmic contact electrode 08;
second conduction type well regions 04 are arranged on two sides of the upper surface of the epitaxial layer 03, conductive materials 10 are filled in the second conduction type well regions 04, and the upper surfaces of the second conduction type well regions 04, the upper surfaces of the conductive materials 10 and the upper surface of the SiC epitaxial layer 03 are flush;
first isolation dielectric layers 05 which correspond to the second conduction type well regions 04 and are equal in width are arranged on two sides of the lower surface of the Schottky contact electrode 06, and the interface of the Schottky contact electrode 06 and the epitaxial layer 03 and the interface of the second conduction type well regions 04 and the first isolation dielectric layers 05 are overlapped.
The diode based on the junction barrier Schottky structure comprises the following specific manufacturing steps:
step 1: selecting a SiC substrate 01, growing a SiC epitaxial layer 03 on the upper surface of the SiC substrate 01, and growing a SiC buffer layer 02 between the SiC substrate 01 and the first conductive type epitaxial layer 03;
step 2: forming second conductivity type semiconductors 04 on two sides of the upper surface of the SiC epitaxial layer 03, forming a trench in the second conductivity type semiconductors 04, and filling a conductive material 10;
and step 3: a first isolation dielectric layer 05 with the same width as the second conductive type well region 04 is formed on the upper surfaces of the second conductive type well region 04 and the conductive material 10;
and 4, step 4: a Schottky contact electrode 06 covering the first isolation dielectric layer 05 and the SiC epitaxial layer 03 is formed above the SiC epitaxial layer 03;
and 5: an ohmic contact electrode 08 is formed below the SiC substrate 01 and a second insulating dielectric layer 07 located between the SiC substrate 01 and the ohmic contact electrode 08 is formed.
Further, the thicknesses of the SiC substrate 01 and the SiC epitaxial layer 03 are both 0-500 um; the thickness of the SiC buffer layer 02 is 0um-50 um; the thickness of the second conductive type well region 04 is 0.1um-500 um; the thicknesses of the first isolation dielectric layer 05, the Schottky contact electrode 06, the second isolation dielectric layer 07 and the ohmic contact electrode 08 are all 0.001-10 um.
Further, the doping concentrations of the SiC substrate 01 and the SiC buffer layer 02 are both 1010~1022um-3(ii) a The doping concentration of the SiC epitaxial layer 03 is 1010~1019um-3(ii) a The doping distribution of the SiC substrate 01, the SiC buffer layer 02 and the SiC epitaxial layer 03 is single doping or gradient doping or step doping.
Further, the crystal forms of the SiC substrate 01, the SiC buffer layer 02 and the SiC epitaxial layer 03 are 4H or 6H; the first conductivity type is n-type, and the second conductivity type is p-type; the materials of the first isolation dielectric layer 05, the Schottky contact electrode 06, the second isolation dielectric layer 07 and the ohmic contact electrode 08 are all metal or other conductive materials.
Further, the planar graph structure of the well region 04 of the second conductive type is one or more of rectangle, circle, ring, hexagon and pentagon, the side length of the graph of the well region 04 is 0.1um-30um, the interval of the graph of the well region is 0.1um-30um, and the thickness of the well region is 0.1um-500 um.
Further, the conductive material 10 is metal or one or more of silicon dioxide, polysilicon, amorphous silicon and silicon nitride, and the doping type of the polysilicon and the amorphous silicon is p-type doping with a doping concentration of 1010~1022um-3。
Further, the SiC substrate 01 is grown by physical vapor deposition ((PVD) or Chemical Vapor Deposition (CVD)), and the SiC buffer layer 02 is grown by Chemical Vapor Deposition (CVD).
Further, the second conductivity type well region 04 is formed by ion implantation and re-etching or secondary epitaxy after etching or ion implantation after etching.
Further, high-temperature treatment processes are carried out between the first isolation dielectric layer 05 and the surface of the second conduction type well region 04, between the Schottky contact electrode 06 and the surface of the SiC epitaxial layer 03, between the second isolation dielectric layer 07 and the surface of the SiC substrate 01, and between the ohmic contact electrode 08 and the surface of the second isolation dielectric layer 07, wherein the treatment modes comprise Rapid Thermal Annealing (RTA) or Laser Annealing (LA) or a high-temperature furnace; the gas atmosphere in the treatment process is a vacuum environment or a nitrogen and inert gas atmosphere, and the inert gas is preferably argon.
After the experiment is carried out in the same environment, the technical scheme of the invention is compared with the experimental data of a common Schottky diode, and the method comprises the following steps:
| forward pressure drop VF（V） | On-resistance Ron,sp（mΩ.cm2） | Leakage current density JR（A/cm2） | Reverse breakdown VB（V） | |
| Example 1 | 1.05 | 2.8 | 7.3×10-5 | 1872 |
| Example 2 | 1.01 | 4.0 | 7.8×10-7 | 1880 |
| SBD | 1.08 | 2.6 | 62.5 | 400 |
The following conclusions can be drawn from the comparative analysis of the data:
compared with a Schottky device, the junction barrier Schottky structure has the advantages that under the reverse mode, on the basis of not sacrificing forward conduction voltage drop, the junction barrier Schottky structure has lower reverse leakage current and higher blocking voltage.
The above-mentioned embodiments are further described in detail for the purpose of illustrating the invention, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the invention and are not intended to limit the invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit of the invention should be included in the scope of the invention.
Claims (9)
1. A junction barrier Schottky structure diode comprising the structure:
a SiC substrate (01) of a material of a first conductivity type;
a SiC epitaxial layer (03) made of a first conductive type is arranged on the upper surface of the SiC substrate (01), and a SiC buffer layer (02) made of the first conductive type is arranged between the SiC substrate (01) and the SiC epitaxial layer (03);
a Schottky contact electrode (06) is arranged on the upper surface of the SiC epitaxial layer (03); an ohmic contact electrode (08) is arranged on the lower surface of the SiC substrate (01), and a second isolation dielectric layer (07) is arranged between the SiC substrate (01) and the ohmic contact electrode (08);
second conductive type well regions (04) are arranged on two sides of the upper surface of the SiC epitaxial layer (03), and the surfaces of the second conductive type well regions (04) are flush with the upper surface of the SiC epitaxial layer (03);
first isolation dielectric layers (05) which correspond to the second conduction type well regions (04) and are equal in width are arranged on two sides of the lower surface of the Schottky contact electrode (06), and the interface of the Schottky contact electrode (06) and the SiC epitaxial layer (03) is overlapped with the interface of the second conduction type well regions (04) and the first isolation dielectric layers (05);
the planar graph structure of the second conductive type well region (04) is one or more of rectangle, circle, ring, hexagon and pentagon, the thickness of the well region graph is 0.1um-500um, the side length size is 0.1um-30um, and the distance of the graph is 0.1um-30 um.
2. The junction barrier schottky structure diode of claim 1, wherein:
the crystal forms of the SiC substrate (01), the SiC buffer layer (02) and the SiC epitaxial layer (03) are 4H or 6H; the first conductivity type is n-type, and the second conductivity type is p-type; the materials of the first isolation dielectric layer (05), the Schottky contact electrode (06), the second isolation dielectric layer (07) and the ohmic contact electrode (08) are all metal or conductive materials.
3. The junction barrier schottky structure diode as described in claim 1 or 2, wherein: and a groove is further formed in the upper surface of the second conduction type well region (04), a conductive material (10) is filled in the groove, and the upper surface of the second conduction type well region (04), the upper surface of the SiC epitaxial layer (03) and the upper surface of the conductive material (10) are flush.
4. The junction barrier schottky structure diode of claim 3, wherein:
the conductive material (10) is metal or one or more of silicon dioxide, polysilicon, amorphous silicon and silicon nitride, the doping types of the silicon dioxide, the polysilicon, the amorphous silicon and the silicon nitride are n-type or p-type doping, and the doping concentration is 1010~1022um-3。
5. The method for manufacturing a junction barrier Schottky structure diode based on any one of claims 1 to 2, comprising the steps of:
step 1: selecting a SiC substrate (01), growing a SiC epitaxial layer (03) on the upper surface of the SiC substrate, and growing a SiC buffer layer (02) between the SiC substrate (01) and the SiC epitaxial layer (03);
step 2: forming second conductive type well regions (04) on two sides of the upper surface of the SiC epitaxial layer (03);
and step 3: a first isolation dielectric layer (05) with the same width as the second conduction type well region (04) is formed on the upper surface of the second conduction type well region (04);
and 4, step 4: a Schottky contact electrode (06) covering the first isolation medium layer (05) and the SiC epitaxial layer (03) is formed above the SiC epitaxial layer (03);
and 5: an ohmic contact electrode (08) is formed below the SiC substrate (01) and a second isolation dielectric layer (07) is formed between the SiC substrate (01) and the ohmic contact electrode (08).
6. The method of manufacturing a junction barrier Schottky structure diode according to claim 5, wherein: the second conduction type well region (04) is formed by ion implantation and etching or secondary epitaxy after etching or ion implantation after etching.
7. The method of manufacturing a junction barrier schottky structure diode as described in claim 5 or 6, wherein: the surface of the first isolation dielectric layer (05) and the surface of the second conduction type well region (04), the surface of the Schottky contact electrode (06) and the surface of the SiC epitaxial layer (03), the surface of the second isolation dielectric layer (07) and the surface of the SiC substrate (01), and the surface of the ohmic contact electrode (08) and the surface of the second isolation dielectric layer (07) are subjected to high-temperature treatment in a Rapid Thermal Annealing (RTA), Laser Annealing (LA) or high-temperature furnace; the gas atmosphere in the treatment process is vacuum environment, nitrogen or inert gas atmosphere.
8. The method for manufacturing a junction barrier Schottky structure diode according to any one of claims 5 to 7, further comprising the following steps between the step S3 and the step S4: and etching the upper surface of the second conductivity type well region (04) to form a groove, and filling the groove with a conductive material (10).
9. The method of manufacturing a junction barrier schottky structure diode as described in claim 8, wherein: the filling of the conductive material (10) is realized by in-situ doping or annealing activation after ion implantation, and the doping distribution is single doping or gradual doping or step doping.
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