KR101415878B1 - Structure and Fabrication Method of High-Voltage UFRED - Google Patents

Abstract

The UFRED structure of the present invention includes an n ⁺ type substrate defined by an active region and a field region, an n-type buried plug doped at a lower concentration than the substrate on the active region substrate, the p-type having a first guard ring, a lower second depth greater than the first depth of the p-type having a first depth from the upper surface of the base layer to the base layer, the field region of the type ^- n is lightly doped than the buried plug A p-type anode junction layer having a second depth lower than the second depth from the upper surface of the base layer in the active region, a p ⁺ -type ion implantation layer formed in the anode junction layer, An ohmic metal forming an ohmic contact of the ohmic metal, and an anode metal pad bonded to the ohmic metal. According to the present invention, even if the breakdown voltage is increased, an effect that the operation speed is high can be expected.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an epi-

The present invention relates to a structure for a high performance UFRED device switching at high voltage and a method of manufacturing the same. Fast recovery diodes (FRDs) used for high frequency (1kHz to 100MHz) switching of power controllers such as SMPS (Switched Mode Power Supply) have static losses, dynamic losses, soft recovery characteristics To operate in compliance with EMC (Electro Magnetic Compatibility) specifications. Snappy recovery, on the other hand, induces voltage spikes, which can damage the UFRED itself as well as the surrounding circuitry, causing problems with EMI / RFI (Electromagnetic Interference / Radio Frequency Interference). Thus, UFRED reduces both Trr (reverse recovery time) and Qr (reverse recovery capacitance) to reduce the dynamic loss, as well as reduce the heat generation of the power driven device, reduce EMI / RFI, It is possible to enhance the reliability in the long-term switching power control operation of the device.

Generally, FRD (Fast Recovery Diode), a rectifier element for high voltage, is used as a free wheeling diode, snubber, and clamp diode in a switching circuit that operates at high speed. Has come. However, recently, the operation speed of IGBT, GTO, and Power MOSFET, which are power control main semiconductor devices, has been increased, and the switching current control slope (dI / dt) has rapidly been controlled so as not to exceed 100 [A / us] In control switching, problems such as overvoltage and power loss become serious. Therefore, in today's FRD, it is necessary to take measures against smaller Irr and small power loss in recovery operation. Therefore, recent FRD technology has been focused on improving operating voltage and soft recovery operation characteristics with less overvoltage and oscillation.

In the past, a common PIN diode was used initially as a rectifier for power control. However, in this case, due to the problem of overvoltage, a snubber circuit had to be used together. However, SNUERBAR has developed a PIN diode device that can be used without a snubber since the circuit is complicated and expensive, and various semiconductor technologies have been applied to improve its performance.

Recent advances in semiconductor technology have made it very attractive to cope with the limitations of high-speed operation and withstand voltage characteristics of silicon semiconductors. Although the development of a high voltage FRD device replacing a PIN device has become easier in recent years, the performance of the FRD device still needs to be improved in terms of operation speed, power consumption, overvoltage, reliability, and power driving. On the other hand, a technique for a high-power high-voltage device using a wide bandgap semiconductor such as SiC or GaN having high heat resistance and high withstand voltage characteristics is attracting attention. However, in terms of long-term reliability of devices, silicon-based power semiconductor devices are expected to supply core components for a considerably long period of time.

FIGS. 1A to 1G show patents and papers on FRD using conventional silicon semiconductors and present the related arts.

FIG. 1A relates to FRD proposed in Patent Document 1 (U.S. Patent No. 7,259,440 B2, Aug. 21, 2007, "Fast Switching Diode with Low Leakage Current," U. Kelberlau, IXYS corporation) In this case, Pt is accumulated at a high concentration on the surface, and n-type is transformed into p-type, and leakage current depends on the concentration of Pt and the concentration of n-type. However, since the interface between p ^- and n ^- (n ⁺ ) increases, the performance of Qr and trr may deteriorate, complicating the fabrication process.

FIG. 1B relates to FRD proposed in Patent Document 2 (Korean Patent Registration No. 10-0263912, May 23, 2000, "Diodes of Semiconductor Devices and Their Manufacturing Method," Kim Nam Jin, Hohyun Kim, Fairchild Korea Semiconductor) The formed FED increases the amount of electrons injected into the anode by the formation of a wavy p ⁺ -n ^- junction and improves the breakdown voltage characteristics by slowly controlling the decrease of the reverse current. However, it is possible to reduce the reliability of the circuit by inducing negative resistance by the npn junction structure, and the high resistance characteristic of the p ^- metal junction can arise from the structure of the device.

FIG. 1C is a schematic view of a device according to Patent Document 3 (U.S. Patent No. 6,261,874 B1) Jul. 17, 2001, "Fast Recovery Diode," R. Francis, M. Beach, C. Ng, International Rectifier Corporation). The FRD proposed in Merged-PIN-Schottky (MPS) is proposed to reduce VF and Trr by combining the advantages of PIN and Schottky junctions. However, the reverse effect shows that the Schottky junction increases the leakage current, and the VF increases when the current density increases due to the reduced area ohmic junction.

1D is a FRD proposed in Patent Document 4 (US Patent Registration No. US 0104456 A1) May 3, 2012, "Fast Recovery Reduced PN Junction Rectifier". The proposed FRD has a p ⁺ The structure of the MPS (Merged Pin Schottky) is obtained by inserting a p-layer between the p-type layer and the p-type layer, so that the VF can be lowered and the soft recovery characteristic can be improved. The height is more demanding.

1E is a schematic diagram of a radiation enhanced diffusion (RED) diode realization of a large area p ⁺ -p ^- n ^- 1, which is described in Non-Patent Document 1 (J. Vobecky, V. Zahlava, K. Hemmann, M. Arnold, M. Rahimo, -n ⁺ structure with high SOA, "). The proposed FRE implies drive-in of Pd and Pt metals at high temperature and at the same time heavily injects He ions to a certain depth The structure to control the carrier concentration of the P layer was proposed. Therefore, the p ^- layer is additionally formed on the pn junction to expand the SOA, thus widening the current and voltage range.

FIG. 1F is a block diagram of an embodiment of a nonvolatile semiconductor memory device according to the present invention, which is disclosed in Non-Patent Document 2 (M. Mori, H. Kobayashi, Y. Yasuda, "6.5 kV Ultra Soft-Fast Recovery Diode with High Reverse Recovery Capability," ISPSO 2000, The proposed FRD shows the structure of a device using p ^- metal junction and p ^- Schottky junction. In order to improve the trade-off between the VF and the reverse recovery characteristics, the guard ring and the HiRC region are optimized to provide a 6.5 kV ultra soft and fast FRD device. In other words, the high resistance is positioned at the edge of the active area as the ballast resister increases, and the optimized design of the guard ring attenuates the snappy recovery characteristic. Thereby improving the soft recovery characteristic.

1G is a FRD proposed in Non-Patent Document 3 (JV Subhas chandra Boss, Iain Imrie, H. Ostymann, P. Igram, "SONIC-A new generation of fast recovery diodes," IXTS, Germany) FRD proposed a structure in which multiple guard rings were used and a deep trap center was placed at the pn junction by Pt drive (drive-in) and He ion implantation. It is a frequently proposed structure for high voltage with very high breakdown voltage. However, there is a problem that the area of the chip increases because of a large number of guard rings, and efforts to further improve soft recovery characteristics are required.

On the other hand, a rectifier element of a simple structure FRD widely used conventionally has a large Trr of 0.1 to 1 us, and the generation of noise due to EMI is serious. Therefore, SBD (Schottky Barrier Diode), which operates with Trr <0.1 us, is mainly used for relatively low voltage of 200 V or less. In addition, power loss and EMI are strengthened by using FRD with high power control performance at high voltage of 150 ~ several kV. Especially, the soft recovery characteristics of FRD devices are improved by the diffusion of heavy metal (eg, Pt, Au) or electron beam irradiation to the existing PIN or MPS device structure. However, recently, as the operating frequency of the power device has increased from 1 KHz to 100 MHz and the driving voltage has also increased to several kV, there has been a need to develop a technology for RFD that has higher speed operation characteristics than the conventional technology .

As described above, conventional techniques are papers and patents on known PIN or FRD structures. Most junction interfaces are fabricated using impurity dopant implantation and diffusion processes, and the reproducibility and uniformity of junction locations and concentrations formed through ion implantation and diffusion processes is poor. The device can be manufactured within the limit of the trade-off between VF and Trr, which is mostly associated with the physical characteristics of the silicon semiconductor substrate. Therefore, there is a limit in improving the soft recovery performance of the high-voltage FRD device remarkably in the conventional method.

1. US Patent Registration No. US 7,259,440 B2 (Aug. 21, 2007) 2. Korea Patent Registration No. 10-0263912 (2000. 05. 23) 3. US Patent Registration No. US 6,261,874 B1 (July 17, 2001) 4. US Patent Registration No. US 0104456 A1 (May 05, 2012)

 1. The radiation enhanced diffusion (RED) diode realization of a large area p + -p - n - n + structure with high SOA, "  2. Mori Mori, H. Kobayashi, Y. Yasuda, "6.5 kV Ultra Soft-Fast Recovery Diode with High Reverse Recovery Capability," ISPSO 2000, France, May 22-25, IEEE 2000  3. J.V. Subhas chandra Boss, Iain Imrie, H. Ostymann, P. Igram, "SONIC-A new generation of fast recovery diodes," IXTS, Germany

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is as follows.

Semiconductor devices operate with the limitation of figure-of-merit (FOM) that (breakdown voltage x operating speed) maintains a generally constant value. Therefore, when the breakdown voltage is increased to increase the drive voltage, the operation speed is decreased, and the drive voltage and the operation speed are in a trade-off relationship. In order to overcome these physical limitations, it is necessary to provide a method of changing the structure of a device or introducing a material having a different characteristic into a material.

In the case of a conventional FRD device, the concentration gradient is increased at a shallow junction in order to reduce the Trr, which causes an increase in the snappy recovery operation. In the interval of 50 to 100 kHz where the frequency is high, EMI Magnetic Interference) intensity is as high as 70 dB V / m. Therefore, by improving the soft recovery characteristic by changing the device structure, it should be reduced to <60 dB V / m to meet the standardization standard.

The present invention provides a unique device structure and a manufacturing method for locally forming a bonding layer of buried plug having a concentration gradient and disposing a guard ring having a difference in concentration and depth. A doped layer of n-type at a low concentration by an ion implantation, and an external diffusion (out-diffusion) n ^- to form in the interior of the layers improving the properties soft recovery (soft recovery), and increasing a forward current drive power and reduce the VF, p ⁺ When the reverse voltage is applied by controlling the distribution of the concentration and depth of the guard ring, the breakdown voltage is increased by increasing the radius of the boundary of the depletion depletion layer due to the gentle interface of the depletion layer. This is the structure to maximize the operating speed even at a high breakdown voltage even if the thickness of the n ^- layer is reduced as much as possible.

In the present invention, when the power is switched off, the minority carrier is rapidly recombined to be destroyed to reduce Qr <20 nC and Trr <15 to 30 ns. Therefore, a UFRED new device is fabricated which has a trade-off between VF and Trr, which is generally smaller than the conventional simple PIN junction.

In particular, high-speed operation in a rectifier for high-performance switching is important because it must have the ability to control the speed of tens of nanoseconds. The high operating speed of high-performance UFRED not only reduces power consumption for high-frequency switching on-off, but also suppresses EMI and stably protects internal electronic circuits and low-voltage components. Do.

According to an aspect of the present invention, there is provided a UFRED comprising: a substrate of a first conductivity type defined as an active region and a field region; A buried plug of a first conductivity type doped, a substrate corresponding to the field region, and a base layer of a first conductivity type doped at a lower concentration than the buried plug on the buried plug, A guard ring of a second conductivity type having a predetermined depth from an upper surface of the base layer, an anode junction layer of a second conductivity type formed in the active region and having a lower depth than the guard ring from an upper surface of the base layer, And an anode metal pad forming an ohmic contact with the bonding layer.

As described above, according to the configuration of the present invention, the following effects can be expected.

The present invention provides a high-voltage UFRED new device having Trr reduced at higher voltage and improved soft recovery characteristics compared with the conventional PIN or MPS device structure. Using the features of the device structure, the accumulation of charge by the minority carriers in the low concentration epitaxial layer (n ^- type) is reduced, and the minority carriers are quickly eliminated during switch-off. This causes snappy recovery, which reduces ringing, EMI, and power loss. When operating in a switching mode at high temperatures, on-off power consumption increases and EAS and leakage current characteristics degrade. Therefore, in the case of being used in a circuit such as a filter or an SMPS, it is not necessary to use a snubber circuit, and miniaturization and cost reduction can be achieved. It is possible to reduce the power consumption and EMI in the electric power driving apparatus of the electric car, the solar battery and the LED lighting circuit, which have been used in recent years, as well as to enhance the effect on environmentally friendly and high efficiency.

FIGS. 1A to 1G are cross-sectional views and characteristic diagrams showing configurations of various types of rectifier devices according to the prior art.
2A to 2D are cross-sectional views illustrating a configuration of a UFRED according to an embodiment of the present invention.
Figs. 3A to 3D are graphs showing the electrical operation characteristics of Figs. 2A to 2D.
4A to 4H are sectional views showing the manufacturing method of Fig. 2C.
Figs. 5A to 5J are cross-sectional views showing the manufacturing method of Fig. 2D.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the detailed description of known functions and configurations incorporated herein will be omitted when it may unnecessarily obscure the subject matter of the present invention.

The same reference numerals are used for portions having similar functions and functions throughout the drawings.

In addition, in the entire specification, when a part is referred to as being 'connected' to another part, it may be referred to as 'indirectly connected' not only with 'directly connected' . Also, to include an element does not exclude other elements unless specifically stated otherwise, but may also include other elements.

&Lt; Structural Example 1 >

2A illustrates a p ⁺ -n ^- structure for a low voltage according to an embodiment of the present invention. In this structure, there is a pn junction interface between the p ⁺ layer 202 and the n ^- layer 203 on the anode 201 side. The breakdown voltage of the device is once the concentration of the n ^- layer 203 and pn Is controlled by the depth (W) of the depletion layer from the junction interface to the n ⁺ layer (204). However, if the concentration of the n ^- layer 203 is sufficiently low and at the same time sufficiently thick, it is affected by the radius of curvature r of the pn junction interface and the radius of curvature R of the depletion boundary. The tendency for this structure is

, And it is very important to increase the curvature radii r and R as compared with W. Thus, in order to increase the breakdown voltage, the thickness of the n ^- layer 203 must be increased, which represents a trade-off from the problem of slowing down the operation speed. Therefore, in order to solve this problem, it is necessary to change or optimize the device structure in the device design. According to the above device structure, although the structure is simple, there is a limitation in increasing the operating voltage due to the drawbacks of leakage current and hard recovery.

&Lt; Structural Example 2 >

FIG. 2B illustrates a p ⁺ -n ^- structure according to an embodiment of the present invention, in which a guard ring 301 is further added to the structure of FIG. 2A. According to such a guard ring structure, since there are many unsafe defects at the interface between the semiconductor surface and the oxide film, it is effective to control the leakage current generated at the side of the semiconductor-oxide film interface and the dielectric breakdown caused thereby. Although a relatively simple manufacturing method is advantageous, there is a limit similar to that of Fig. 2A for increasing the breakdown voltage and reducing the leakage current. The number of the guard rings 301 can be increased to 2 to 10 in order to enhance the breakdown voltage and the leakage current characteristic. However, the cross-sectional area increases and the production cost increases.

&Lt; Structural Example 3 >

FIG. 2C provides a UFRED structure for controlling the breakdown voltage and leakage current by adjusting the concentration and depth of the guard ring in FIG. 2B.

Referring to FIG. 2C, the UFRED structure of the third embodiment includes an n ⁺ -type substrate 400 defined by an active region AR and a field region FR, a substrate 400 on the active region AR, n is lightly doped than the buried plug 402 on the substrate 400 and the buried plugs 402 buried plug 402, the field region (FR) of the n-type is doped at a low concentration than the 400 ^- Type first guard ring 405 having a first depth from the top surface of the base layer 504 in the field region FR and a p-type first guard ring 405 having a second depth lower than the first depth, A p-type anode junction layer 407 having a third depth lower than the second depth from the upper surface of the base layer 403 in the active region AR, a second guard ring 406 of the anode junction layer 407, forming p ⁺ type ion-implanted layer 408, the ion-implanted layer 408 to the metal phase which is-ohmic metal 409, and the ohmic metal 409 and the anode metal pads 410 are bonded to form an ohmic contact of the semiconductor Include The.

FIG. 2C shows that in FIG. 2B, an n-layer buried plug 402 having a concentration gradient on top of the n ⁺ layer locally aligns best with the active region AR. Thus, the radius of curvature at the edges of the active junction can be further increased by the first and second guard rings 405, 406 controlling the gradient of the concentration and depth. 2A, the radius of curvature of the p ⁺ layer and the depletion layer is increased to minimize the leakage current flowing in the edge and the lateral direction, and at the same time, the leakage current or the breakdown voltage flowing in the vertical direction can be controlled . The number of guard rings can be reduced even with the same breakdown voltage, and a UFRED device having a structure in which the operating speed is maximized by keeping the thickness of the n ^- layer in conjunction with the operation speed of the device thin can be manufactured. In particular, the bonding of the locally formed n-type buried plug 402 controls the recombination with the concentration of the minority carrier, thereby greatly improving the soft-recovery and reliability characteristics.

&Lt; Structural Example 4 >

Figure 2d is a p edaga structure of Figure 2c ^- relates to the layer and the p ⁺ layer structure in which a more improved EAS and soft-recovery characteristics arranged in mesh form.

2D, an n ⁺ -type substrate 500 defined as an active region AR and a field region FR, an n-type buffer layer 501 doped at a lower concentration than the substrate 500 on the substrate 500, An n type buried plug 503 doped at a lower concentration than the substrate 500 on the buffer layer 501 of the active region AR, a buffer layer 501 of the field region FR, and a buried plug 503, An n ^- type base layer 504 doped at a lower concentration than the buried plug 503 on the p-type first guard ring 503, a p-type first guard ring 504 having a first depth from the upper surface of the base layer 504 of the field region FR A second guard ring 507 having a second depth lower than the first depth, a second guard ring 507 having a second depth lower than the second depth from the upper surface of the base layer 504, A p ^- type ion implantation layer 509 which is doped at a lower concentration than the anode junction layer 508 on the surface of the base layer 504, a p ^- type ion implantation layer 509 which is doped at a lower concentration than the anode junction layer 508, On the surface A p ⁺ -type ion implantation layer 510 doped at a higher concentration than the anode junction layer 508, an ohmic metal 511 to be bonded to the ion implantation layers 509 and 510 and an anode metal 511 to be bonded to the ohmic metal layer 511, Pad &lt; / RTI &gt;

The Schottky junction is formed on the p ^- layer of the semiconductor surface by a Schottky junction to reduce the VF and to use the breakdown voltage as high as 2 ~ 6 kV. Attention is paid to the formation of key junctions.

FIG. 3A shows the distribution of the impurity doping concentration of the p ⁺ -n ^- -n ⁺ junction which is an active area in the device structure of FIGS. 2C and 2D. This is a method for high breakdown voltage and soft recovery operation. The p ⁺ layer for the metal - semiconductor junction of the anode, the p ^- layer to reduce the minority carrier implant, the n ^- layer to control the breakdown voltage, the n ^- layer to control the distribution and elimination of the minority carriers, and an n ⁺ layer. The concentration of p layer is controlled to 10 ¹⁷ ~ 10 ¹⁸ cm ^-3 and the concentration of n ^- layer is controlled to 10 ¹³ ~ 10 ¹⁵ cm ^-3 directly at the breakdown voltage .

FIG. 3B shows the reverse I-V characteristic in the device structure of FIG. 2A, FIG. 2B, and FIG. 2C. 2A is a PIN (P) structure without a guard ring, and has a lower breakdown voltage and a higher leakage current than the elements corresponding to FIGS. 2B and 2C. The device of FIG. 2B has a high breakdown voltage due to the presence of a guard-ring, but the leakage current is still higher than that of the device of FIG. 2C. The UFRED (U) device corresponding to FIG. 2C of the present invention is relatively excellent in breakdown voltage and leakage current characteristics. Control of the leakage current is important to increase reliability for EAS and high temperature operation.

FIG. 3C shows the I-V characteristics of the UFRED and the low VF UFRED devices compared to FIG. 2C and FIG. 2D of the present invention. Compared with the UFRED structure of FIG. 2C, the low VF UFRED device structure of FIG. 2D reduces the VF to a level of 0.5 to 1 V at a level of 1 to 2 V by adding an active layer similar to MPS, An effect of forming a Schottky junction can be obtained.

Figure 3d shows the Trr characteristics for the UFRED (U) structure compared to the conventional PIN (P) and MPS (M) structures. Snappy phenomenon is very serious and Trr is large in the conventional PIN structure. The MPS structure, which is also a conventional technique, greatly improves the disadvantages of the PIN structure, in particular, reduces VF. In the UFRED (U) structure of the present invention, a burr plug of a graded junction of a guard ring and a cathode plug adjusted in concentration and depth is employed to reduce the Trr, (snappy recovery) phenomenon was relaxed. In the case of the unique structure UFRED, the breakdown voltage, Trr, and soft recovery characteristics can be optimized.

&Lt; Method First Embodiment >

4A to 4J are cross-sectional views illustrating a method of manufacturing a UFRED according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, a semiconductor substrate 400 doped with an impurity of a first conductivity type (e.g., n ⁺ type) at a high concentration is prepared. The substrate 400 is defined as an active area AR and a field area FR. An oxide film 401 is formed on the substrate 400. [ The oxide film 401 may be grown by a thermal oxidation process or may be formed by a CVD deposition process. A region capable of ion implantation or selective epitaxial growth is formed in the active region AR through a photolithography process and then an impurity of the first conductivity type (for example, n Type buried plug 402 is formed. The buried flood 402 is doped at a lower concentration than the substrate 400. [ After the doping, the oxide film 401 is removed.

Referring to FIG. 4B, a base layer 403 doped with impurities of a first conductivity type (e.g., n ^- type) of a low concentration of a group V element (e.g., As, Sb or P) at intrinsic semiconductor level, Lt; / RTI &gt; Base layer 403 is controlled by in-situ (in-situ) lightly doped with up to 10 ¹⁴ cm ^-3. The buried plug 402 10 ²⁰ cm ^-3 at a high concentration to a low concentration of 10 ¹⁴ cm ^-3 is varied with graded junction (graded junction), a cathode (cathode) side buried plug (buried plug) 402 of the Lt; / RTI &gt; This profile of the impurity concentration is important for controlling the concentration distribution of the minority carrier (hole) injected from the anode side. The transmission of electrons occurs mainly in the vertical direction in the active region AR and the degree of the flow in the lateral direction of the field region FR, which is the edge region of the active region, is reduced. In such a device structure, when the switch-off is performed, the small number of carriers is moved to the upper side quickly, and the device disappears.

Referring to FIG. 4C, an insulating film 404 is deposited or grown, a region to be ion-implanted through a photolithography process and an etching process is formed, and then doped with an impurity of a second conductivity type (for example, boron) Thereby forming the first guard ring 405. The ion implantation of the first guard ring 405 doped with the above-described impurity ion-implies impurities (for example, B ⁺ or BF2 ⁺ ) of 30 to 200 [keV].

4D, a diffusion process of implanted impurities is performed to form a first guard ring 405 at a deep first depth of the semiconductor junction (e.g., pn). The substrate 400 is subjected to heat treatment at a temperature of 800 to 1100 [占 폚] to perform activation and diffusion of impurities, followed by control to form a junction with a concentration of 10 ¹⁸ cm ^-3 or more. Subsequently, the step of forming the second guard ring 406 junction having the intermediate depth through the ion implantation process and the diffusion process of the impurity (for example, B ⁺ or BF2 ⁺ ) is repeated to form the first guard ring 405 Thereby forming a second guard ring 406 of a second depth lower than the depth. For example, the second guard ring 406 is deeper than the first guard ring 405. Similarly, the substrate is subjected to heat treatment at a temperature of 800 to 1100 [占 폚] so that activation and diffusion of the third impurity occurs, and then the junction of the intermediate depth second guard ring 406 is formed at a concentration of 10 ¹⁸ cm ^-3 or more .

Referring to FIG. 4E, impurities (for example, boron) are ion-implanted and diffused into the active region AR through a photolithography process, as in FIGS. 4C and 4D, to form an anode junction layer 407 of a second conductivity type, As shown in FIG. The anode junction layer 407 is formed at a third depth from the upper surface of the base layer 403. [ The third depth of the anode junction layer 407 is lower than the first and second depths of the first and second guard rings 405 and 406. Further, the substrate 400 is subjected to heat treatment at a temperature of 800 to 1100 [占 폚] so that activation and diffusion of the impurities occur, and then a junction is formed at a concentration of 10 ¹⁸ cm ^-3 or more. At this time, the impurity distribution is controlled to be isotropic so that the electric field is uniformly distributed at a high voltage. Controlling the profile of the etch interface so that the local electric field is not focused will directly affect the concentration distribution of impurities. "Two-dimensional dopant profiling in P ⁺ / n junctions using scanning electron microscopy coupled with selective electrochemical etching", Electronic Materials (KAIST), Korea Institute of Science and Technology (KAIST) Lett. Vol. 6, No. 2, pp. 55-58, May 2010)

Referring to FIG. 4F, the insulating film 404 is patterned and a high concentration p ⁺ type ion implantation layer 408 for ohmic junction is doped at a high concentration (eg p ⁺ ) by ion implantation of impurities (for example, boron) .

Heavy metal diffusion, He ion implantation, electron beam irradiation can then additionally be carried out in a manner known per se to control the lifetime of minority carriers. In the case of heavy metals (eg Au, Pd, Pt, Mo) forming deep quasi-semiconductors in the semiconductor, a thin film with a thickness of about 1 nm is deposited on the backside of the wafer and diffused by heat treatment. The method of ion implantation of high energy He is useful for reducing the lifetime of minority carriers intensively in the local area. The electron beam irradiation is carried out at 1 to 12 [MeV], and uniformly irradiated onto the entire wafer. Trr is reduced by artificially injecting the recombination center of the minority carriers.

Referring to FIG. 4G, ohmic metal 409 is deposited to form a metal-semiconductor ohmic junction. A metal junction is formed on the p ⁺ ion implanted layer 408 at a high concentration by an Ohmic junction having a small resistance. In this case, metals (for example, Al, Pt, Ti, Ni, Pd, W) or silicides (for example, TiSi2, NiSi2, WSi, CoSi) may be used for the metal-semiconductor junction.

Referring to FIG. 4H, a metal thin film is deposited on the ohmic metal 409 to form a metal pad 410. At the same time, a metal field plate 411 is formed in the insulating film 404 on the upper portions of the first and second guard rings 405 and 406 as well. The field plate 411 formed on the insulating film 404 is directly connected to the first and second guard rings 405 and 406 formed in the lower semiconductor if necessary, The characteristics can be improved.

Although not shown in the drawing, a passivation film may be finally formed on the upper surface of the substrate 400, and only the metal pad 410 may be exposed to perform wire bonding. Then, the back surface of the substrate 400 is polished using a conventional technique to reduce the thickness of the substrate 400 to a thickness of 60 to 150 [mu] m, followed by depositing a back metal, do.

The high-performance UFRED device of the present invention is completed by connecting a metal junction to a junction with a plurality of junction interfaces as described above. The process steps of fabricating the UFRED for the present invention through the process of FIGS. 4A through 4H are relatively simple. Because the process steps are clear and the number of masks is small, process control is simple and accurate, and the product is excellent in mass productivity and reliability.

&Lt; Method Second Embodiment >

5A to 5J are process cross-sectional views illustrating a method of manufacturing a UFRED having a VF of 0.5 V or lower according to the cross-sectional structure of FIG. 2D according to an embodiment of the present invention.

Referring to FIG. 5A, a semiconductor substrate 500 doped with an impurity of a first conductivity type (for example, n ⁺ type) is prepared. The substrate 400 is defined as an active area AR and a field area FR. The n-type buffer layer 501 doped with impurities (for example, As, Sb) at a low concentration is grown on the substrate 500 by chemical vapor deposition. At this time, the impurity concentration of the n-type buffer layer 501 is controlled by in-situ doping to a level of 10 ¹⁶ to 10 ¹⁸ cm ^-3 .

5B, an oxide film 502 is grown on the substrate 500, a region capable of selective ion implantation or epitaxial growth is formed through a photolithography process, and then an ion implantation or an ion implantation is performed in the active region AR. A buried plug 503 is formed by ion implanting a second impurity (e.g., phosphorous) by an epitaxial growth method. Here, the buried plug 503 to which the impurity ions are implanted is changed to a graded junction at a high concentration of 10 ¹⁶ to 10 ¹⁸ cm ^-3 to 10 ¹³ to 10 ¹⁵ cm ^-3 , And acts as a graded buried plug 503. This profile of impurity concentration is important for controlling the concentration distribution of minority carriers (holes) injected from the anode. It is also important to control the phenomenon of snappy recovery by quickly moving the minority carrier upward during switch-off.

Referring to FIG. 5C, a low-concentration base layer 504 of an intrinsic semiconductor level is grown using impurities (As, Sb or P). At this time, the low-concentration base layer 504 is controlled by doping in-situ at a low concentration of 10 ¹³ to 10 ¹⁵ cm ^-3 .

5D, an insulating layer 505 is deposited, a region to be ion-implanted through photolithography and etching is formed, and then a deep first guard ring 506 is formed by ion implantation of impurities (e.g., boron) do. Ion implantation of impurities in the first guard ring layer 506 dopes ions of 30-200 keV (e.g., B ⁺ or BF ₂ ⁺ ). The impurity implanted is diffused to form a guard ring of the pn junction. By heating the temperature of the substrate 500 at 800 ~ 1100 ^o C causes activation and diffusion of impurities, and after concentration is 10 to ¹⁸ cm ^- is controlled so as to be bonded is formed of ^three or more. A junction is formed between the low-concentration base layer 504 and the first guard ring 506 doped with the impurity.

Referring to FIG. 5E, the step of diffusing the impurity implanted with the impurity (for example, Boron) to form the intermediate depth second guard ring 507 junction of pn is repeated to form the first depth first Thereby forming a second guard ring 507 having a second depth that is lower than the depth of the guard ring 506. Such that the middle depth of the second guard ring (507) bonded to not less than ³ is formed ^- similarly to the heat treatment the temperature of the semiconductor substrate 500 in 800 ~ 1100 ^o C causes activation and diffusion of impurities, and after concentration of 10 ¹⁸ cm in .

Referring to FIG. 5F, a step of forming a junction of pn using a diffusion process after ion implantation of an impurity (for example, boron) into an active area through a photolithography process as in FIGS. 5D and 5E . At this time, the p-type anode junction layer 508, which is designed in a mesh-like shape and doped with the same coin type impurity as the first and second guard rings 506 and 507, is used to form the MPS. In addition, the heat treatment temperature of the semiconductor substrate 500 in 800 ~ 1100 ^o C is activated and diffusion of impurities occurs, and the concentration is 10 ¹⁸ cm ^{after-controls} so that the junction is formed in a ^three or more. At this time, the distribution of the impurities is controlled as isotropic as possible so that the electric field is uniformly distributed at a high voltage.

Referring to FIG. 5G, ion implantation of an impurity (e.g., boron) is then performed at an energy of 30 to 100 keV to form a low concentration p ^- type ion implanted layer 509. The thickness and the impurity concentration of the p ^- type ion implantation layer 509 are very important because they control not only the concentration of the minority carriers (holes) injected into the cathode side but also the Schottky junction characteristics with the upper metal It must be precisely controlled. The p ^- -type ion implantation layer 506 forms a p ^- n ^- junction interface with the base layer 504 of low concentration (e.g. n ^- type).

Referring to FIG. 5H, a p ⁺ -type impurity is implanted into the anode junction layer 508 having a mesh-like structure of an active area by ion implantation or an epitaxial growth method at a high concentration for ohmic junction of the anode electrode (for example, p ⁺ Type) ion implantation layer 510 is formed. At this time, deposition of the p ⁺ -type ion implantation layer 510 or the heterojunction thin film doped with a high concentration (for example, p ⁺ -type) of the impurity is used.

As an example of forming the high concentration p ⁺ type ion implanted layer 510, Si _{1 -x} Ge _x (x = 0 to 1) is used when a silicon semiconductor epitaxial layer is used. The SiGe layer is very useful for locally forming a p ⁺ layer by concentrating boron at a high concentration in a certain section. And the selective epitaxial growth of the SiGe layer is affected by the shape and density of the pattern, so that the arrangement is appropriately reflected in the shape of the device structure. The uniformity and reproducibility of the UFRED device characteristics are maintained because the semiconductor substrate 500 is selectively deposited at a relatively low temperature of 800 ^° C or lower and the diffusion of impurities in the junction is limited.

 Subsequently, heavy metal diffusion, He ion implantation, electron beam irradiation may be additionally performed in a manner known per se to control the lifetime of the minority carriers. In the case of heavy metals (eg Au, Pd, Pt) present deep inside the semiconductor, a thin film of about 1 nm thickness is deposited on the backside of the wafer and diffused by heat treatment. He is useful to reduce the life span of the minority carriers intensively to the local area. The electron beam irradiation is performed at 1.5 to 12 MeV, and uniformly irradiated onto the entire wafer. Trr is reduced by artificially injecting the recombination center of the minority carriers.

5i, ohmic metal 511 is deposited to form a metal-semiconductor junction. The impurity forms a Schottky junction over the lightly doped layer (p ^- layer) region, and the third impurity forms an ohmic junction with a small resistance over the heavily doped layer (p ⁺ layer) region. In this case, metals (for example, Al, Pt, Ti, Ni, Pd, W and Mo) or silicides (for example, TiSi ₂ , NiSi ₂ , WSi and CoSi) conventionally used conventionally can be used for the metal-semiconductor junction.

Referring to FIG. 5J, a metal thin film is deposited on the ohmic metal 511 and patterned to form the metal pad 512, and the insulating film 505 on the upper portions of the first and second guard rings 506 and 507 Similarly, a field plate of metal is formed in the form of a guard ring 513. The field plate 513 formed on the insulating film 505 is directly connected to the first and second guard rings 506 and 507 formed on the lower semiconductor to remove the breakdown voltage and the reliability The characteristics can be improved.

Finally, a passivation oxide layer is formed on the top of the chip and only the metal pad 512 is exposed for wire bonding, although not shown in the drawing. Then, the back surface of the substrate 500 is polished by a conventional technique to reduce the thickness of the substrate to a thickness of 60 to 150 μm, followed by depositing a back metal, and then performing heat treatment to complete the fabrication of the chip.

The present invention can be manufactured and manufactured in various modified forms through simplification and application based on the structure using a plurality of semiconductor junction layers as described above. For example, in the present invention, a fabrication method using a silicon semiconductor substrate has been described as an embodiment. However, the device structure and fabrication method of the present invention are applicable to compound semiconductors such as GaAs, InP, GaN and SiC and similar semiconductors using the same principle and method . As is known, it is general to optimize the mass production of a product in comparison with the performance of a product in terms of yield, reliability, productivity, and production cost.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. To those skilled in the art.

400: substrate 401: oxide film
402: buried plug 403: base layer
404: insulating film 405: first guard ring
406: second guard ring 407: anode bonding layer
408: ion implantation layer 409: ohmic metal
410: metal pad 411: field plate
500: substrate 501: buffer layer
502: oxide film 503: buried plug
504: base layer 505: insulating film
506: first guard ring 507: second guard ring
508: Anodic bonding layer 509: p ^- type ion implantation layer
510: p ⁺ -type ion implantation layer 511: ohmic metal
512: metal pad 513: field plate

Claims (16)

A substrate of a first conductivity type defined as an active region and a field region;
A buried plug of a first conductivity type doped on a substrate corresponding to the active region at a lower concentration than the substrate;
A substrate corresponding to the field region and a base layer of a first conductivity type doped on the buried plug at a lower concentration than the buried plug;
A guard ring of a second conductive type formed in the field region and having a predetermined depth from an upper surface of the base layer;
An anode junction layer of the second conductivity type formed in the active region and having a lower depth than the guard ring from an upper surface of the base layer; And
And an anode metal pad forming an ohmic contact with the anode junction layer,
Wherein the buried plug has a diffusion coefficient higher than that of the substrate, so that the relative concentration gradually decreases toward the base layer. The method according to claim 1,
Wherein the guard ring includes a first guard ring having a first depth from an upper surface of the base layer and a second guard ring having a second depth lower than the first depth from an upper surface of the base layer, A ring is arranged between the first guard ring and the anode junction layer. delete The method according to claim 1,
The buried plugs, UFRED, characterized in that in the substrate is graded from high concentration of 10 ²⁰ cm ^-3 it goes to the base layer 10 to the low concentration of ¹⁴ cm ^-3. The method according to claim 1,
And a second conductivity type ion implantation layer formed on the surface of the anode junction layer and doped at a higher concentration than the anode junction layer. 6. The method of claim 5,
And an ohmic metal formed between the ion implanted layer and the anode metal pad to form ohmic junctions of the metal-semiconductor. A substrate of a first conductivity type defined as an active region and a field region;
A buffer layer of a first conductivity type doped on the substrate at a lower concentration than the substrate;
A buried plug of a first conductivity type doped on a buffer layer corresponding to the active region at a lower concentration than the substrate;
A buffer layer corresponding to the field region and a base layer of a first conductivity type doped on the buried plug at a lower concentration than the buried plug;
A guard ring of a second conductive type formed in the field region and having a predetermined depth from an upper surface of the base layer;
A second conductive type anode junction layer formed in the active region in a mesh shape and having a lower depth than the guard ring from the upper surface of the base layer; And
And an anode metal pad forming an ohmic contact with the anode junction layer,
Wherein the buried plug forms a grade junction in which the concentration gradually decreases toward the base layer. 8. The method of claim 7,
A p ^- type ion implantation layer of a second conductivity type formed on the surface of the base layer and doped at a lower concentration than the anode junction layer; And
And a p ⁺ -type ion implantation layer of a second conductivity type formed on the surface of the anode junction layer and doped at a higher concentration than the anode junction layer. delete 8. The method of claim 7,
Wherein the guard ring is comprised of a plurality of guard rings whose depth of doping gradually increases toward the field region. Doping a substrate composed of an active region and a field region into an n ⁺ type;
Selectively epitaxially depositing an n-type buried plug on the active region of the substrate;
Epitaxially growing an n ^- type base layer on the substrate and the buried plug;
Implanting a base layer corresponding to the field region to a first depth to form a p-type first guard ring;
Implanting a base layer corresponding to the field region to a second depth to form a p-type second guard ring;
Implanting a base layer corresponding to the active region to a third depth to form a p-type anode junction layer;
Doping the anode junction layer to form a p ^& lt ^{; + &} gt ^; type ion implanted layer for ohmic junction; And
Depositing ohmic metal and metal pads on the ion implanted layer in sequence. &Lt; RTI ID = 0.0 &gt; 11. &lt; / RTI &gt; 12. The method of claim 11,
Wherein the doping depth of the impurity is adjusted such that the first depth, the second depth, and the third depth are sequentially lowered. delete delete Doping a substrate composed of an active region and a field region into an n ⁺ type;
Epitaxially growing a buffer layer on the substrate and doping the buffer layer into n-type;
Selectively epitaxially growing a buried plug on the active region of the buffer layer and doping the buried plug into n-type;
Epitaxially growing a base layer on the buffer layer and the buried plug and doping the n ^- type into the base layer;
Implanting a base layer corresponding to the field region to a first depth to form a first guard ring;
Implanting a base layer corresponding to the field region to a second depth to form a p-type second guard ring;
Implanting the base layer corresponding to the active region to a third depth, and forming a p-type anode junction layer in a mesh shape;
Forming a p ^- type ion implanted layer by doping the base layer of the mesh type at a low concentration;
Forming a p ⁺ -type ion-implanted layer by doping the mesh-type anode junction layer at a high concentration; And
The anode bonding layer, the p ^- type ion implantation layer, and the p ⁺ type ion implantation to form a metal pad, the anode on the layer, the p ^- is a Schottky junction between the type ion implantation layer and the anode metal pad, wherein lt ^; RTI ID = 0.0 ^& gt ^; ohmic ^& lt ^{; /} RTI ^& gt ^; junction between the p ⁺ type ion implanted layer and the anode metal pad. delete

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