KR101448158B1 - Structure and Fabrication Method of High-Performance FRD for low voltage and high current - Google Patents
Structure and Fabrication Method of High-Performance FRD for low voltage and high current Download PDFInfo
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Abstract
Description
BACKGROUND OF THE
Therefore, the HP-FRD of the present invention reduces the Trr (reverse recovery time, approximately 1 to 30 ns) and Qr (reverse recovery capacitance), thereby reducing the dynamic loss and reducing the Vf to 0.3 to 1.1 V To reduce the heat generation of the power driving device, to minimize the occurrence of EMI / RFI, and at the same time to improve the reliability in the long-term switching power control operation of the device. Since the reverse leakage current is low and stable at high temperature operation, the conventional technology has an operating temperature range of 100 to 150 DEG C, whereas the device of the present invention can increase the operation range to 150 to 200 DEG C. Especially, it solves weakness of power control FRD against breakdown voltage and leakage current avalanche characteristics and improves EAS performance.
In general, FRD (Fast Recovery Diode), a rectifier element for power control, is used as a free wheeling diode, snubber, and clamp diode in a switching circuit that operates at high speed. Has come. Representative FRD devices of the prior art are based on PIN-FRD (P-i-n type FRD) and MPS-FRD (Merged PIN Schottky) structures. In a power device, the voltage used is usually about 0 to 2 kV, and the voltage used for a high-voltage device is usually about 2 to 1,000 kV.
Recently, the operation speed of IGBT, GTO, and Power MOSFET, which are power control main semiconductor devices, has been rapidly increased, and the current control slope (dI / dt) of switching has been rapidly controlled without exceeding 100 [A / us]. As a result, problems such as overvoltage and power loss in power control switching have become serious. Therefore, in recent years FRD has been required to take measures against smaller trr and small power loss in recovery operation. In addition, it focuses on improving the operation characteristics of soft recovery, which not only increases the operating voltage but also has an overvoltage and an oscillation.
In the past, a common PIN diode was used initially as a rectifier for power control. However, in this case, due to the problem of overvoltage, a snubber circuit had to be used together. However, SNUERBAR has developed a PIN diode device that can be used without a snubber since the circuit is complicated and expensive, and various semiconductor technologies have been applied to improve its performance.
Recently, it seems to be very attractive to cope with the development of the semiconductor technology and to expand the limit of the high-speed operation and the withstand voltage characteristic of the silicon semiconductor at the same time. Although the development of a high-voltage FRD device replacing a PIN diode device has been facilitated in recent years, the performance of an FRD device still needs to be improved in terms of operation speed, power consumption, overvoltage, reliability, and power driving.
On the other hand, a technique for a high-power high-voltage device using a wide bandgap semiconductor such as SiC or GaN having high heat resistance and high withstand voltage characteristics is attracting attention. However, in terms of long-term reliability of devices, silicon-based power semiconductor devices are expected to supply core components for a considerably long period of time.
FIGS. 1A to 1I show patents and papers on FRD using conventional silicon semiconductors and present the related arts.
FIG. 1A relates to FRD proposed in Patent Document 1 (U.S. Patent No. 7,259,440 B2, Aug. 21, 2007, "Fast Switching Diode with Low Leakage Current," U. Kelberlau, IXYS corporation) When the Pt acting as a time killer is diffused and used, Pt is accumulated at a high concentration on the surface, and the n-type is deformed into the p-type, so that the leakage current occurs depending on the concentration of Pt and the concentration of n-type. However, since the interface between p - and n - (n + ) increases, the performance of Q r and T rr may deteriorate and the fabrication process becomes complicated.
FIG. 1B relates to FRD proposed in Patent Document 2 (Korean Patent Registration No. 10-0263912, May 23, 2000, "Diodes of Semiconductor Devices and Their Manufacturing Method," Kim Nam Jin, Hohyun Kim, Fairchild Korea Semiconductor) The formed FED increases the amount of electrons injected into the anode by the formation of a wavy p + -n - junction and improves the breakdown voltage characteristics by slowly controlling the decrease of the reverse current. However, it is possible to reduce the reliability of the circuit by inducing negative resistance by the npn junction structure, and the high resistance characteristic of the p - metal junction can arise from the structure of the device. Therefore, there is a problem in that the phenomenon of snappy recovery is deepened in the reverse recovery operation.
FIG. 1C is a schematic view of a device according to Patent Document 3 (U.S. Patent No. 6,261,874 B1) Jul. 17, 2001, "Fast Recovery Diode," R. Francis, M. Beach, C. Ng, International Rectifier Corporation). The FRD proposed in Merged-PIN-Schottky (MPS) is proposed to reduce the V F and T rr by combining the advantages of PIN and Schottky junctions. However, as a counterproductive effect, leakage current increases due to the Schottky junction, and if the current density is increased due to the ohmic junction of the reduced area, the reliability of the device deteriorates.
1D is a FRD proposed in Patent Document 4 (US Patent Registration No. US 0104456 A1) May 3, 2012, "Fast Recovery Reduced PN Junction Rectifier". The proposed FRD has a p + The structure of MPS (Merged Pin Schottky) is obtained by inserting a p-layer between the p-type layer and the p-type layer, and thus V F can be lowered and soft recovery characteristics can be improved. The process of forming a Schottky junction while thinning it adds to the difficulty in controlling reproducibility and uniformity.
FIG. 1E shows a FRD proposed in US Patent No. 7,169,634 B2, January 30, 2007, "Design and fabrication of rugged FRED" by S. Zhao, D. Sdrulla, Advanced Power Technology Inc. The proposed FRD allows the current to be primarily focused into the active area by causing the p + -n junction to be additionally counter doped to form in the active area. Therefore, the avalanche occurs mainly in the active area, thereby improving the E AS performance. However, in this case, it is difficult to control the reproducibility and uniformity of the interface at a high concentration with a counter doping. Therefore, to improve the E AS, but the disadvantage is jinige to secure productivity and a high yield through the control of the breakdown voltage.
Fig. 1F is a schematic diagram of the radiation enhanced diffusion (RED) diode realization of a large area p + -p - n - 1, which is described in Non-Patent Document 1 (J. Vobecky, V. Zahlava, K. Hemmann, M. Arnold, M. Rahimo, -n + structure with high SOA, "). The proposed FRE implies drive-in of Pd and Pt metals at high temperature and at the same time heavily injects He ions to a certain depth The structure to control the carrier concentration of the P layer was proposed. Therefore, the p - layer is additionally formed on the pn junction to expand the SOA, thus widening the current and voltage range. It is advantageous for devices with very high breakdown voltages (<5 to 10 [kV]), but the ion implantation of high energy helium (He) causes an increase in process cost and imposes difficulties in precisely controlling the heat treatment steps for defect control do.
FIG. 1G is a block diagram of a nonvolatile semiconductor memory device according to a second embodiment of the present invention, which is disclosed in Non-Patent Document 2 (M. Mori, H. Kobayashi, Y. Yasuda, "6.5 kV Ultra Soft-Fast Recovery Diode with High Reverse Recovery Capability," ISPSO 2000, The proposed FRD shows the structure of a device using p - metal junction and p - Schottky junction. In order to improve the trade-off between VF and reverse recovery characteristics, the guard ring and the HiRC region are optimized to provide a 6.5 [kV] ultra soft and fast FRD device. In other words, the high resistance is positioned at the edge of the active area as the ballast resister increases while the high voltage is increased. The optimized design of the guard ring attenuates the snappy recovery characteristic, Thereby improving the soft recovery characteristic.
1H relates to FRD proposed in Non-Patent Document 3 (JV Subhas chandra Boss, Iain Imrie, H. Ostymann, P. Igram, "SONIC-A new generation of fast recovery diodes," IXTS, Germany) FRD proposed a structure in which multiple guard rings were used and a deep trap center was placed at the pn junction by Pt drive (drive-in) and He ion implantation. This structure is frequently proposed for a high voltage with a very high breakdown voltage. However, since the number of guard rings is large, there is a problem that the area of the chip is increased, and efforts to further improve soft recovery characteristics are required.
FIG. 1I is a schematic diagram of a method of manufacturing a semiconductor device according to Patent Document 6 (U.S. Patent No. 6,979,861 B2, December 27, 2005, "Power Device Having Reduced Reverse Bias Leakage Current" by V. Rodov, P. Chang, GM Hurtz, GC Chern, The present invention relates to a power semiconductor device proposed by APD Semiconductor Inc., a structure in which at least one gate is formed on a semiconductor surface, with one conductivity being vertically controlled. When the forward bias is applied to the gate, the channel is formed at the lower end of the gate so that the current flows well. When the reverse bias is applied, the lower end of the gate electrode is doped at a low concentration and the current does not flow. In this device structure, the channel formed at the lower portion of the gate is simple, which limits the ability to drive the current under the condition that the low-voltage forward bias is applied. In addition, it is difficult to ensure reproducibility and uniformity as a whole by forming a p-type region narrowing the inversion at the bottom of the gate.
On the other hand, a rectifier element of a simple structure FRD widely used conventionally has a large T rr of 0.1 to 1 [us], and the generation of noise due to EMI is serious. Therefore, SBD (Schottky Barrier Diode) which operates at T rr <0.1 [us] is mainly used for relatively low voltage less than 200 [V]. In addition, power loss and EMI are reinforced by using FRD with high power control performance for high voltage 200 ~ several kV. Especially, the soft recovery characteristics of FRD devices are improved by the diffusion of heavy metal (for example, Pt, Au) or electron beam irradiation to the conventional PIN diode or MPS diode structure. However, recently, as the operating frequency of the power device has increased from 1 KHz to 100 MHz and the driving voltage has also increased to several kV, there has been a need to develop a technology for RFD that has higher speed operation characteristics than the conventional technology .
As mentioned above, the prior art is the papers and patents on the previously known FRD structures of PIN, MPS, or MOS diodes. Most junction interfaces are fabricated using impurity dopant implantation and diffusion processes, and the reproducibility and uniformity of junction locations and concentrations formed through ion implantation and diffusion processes is poor.
In addition, the device can be fabricated within the limit of the trade-off between VF and Trr, which is mostly associated with the physical characteristics of the silicon semiconductor substrate. Therefore, there is a limitation in improving the EAS and the soft recovery performance of the FRD device, which is a power switching device for low voltage-high current (generally 0 to 400 V, 0 to 60 A) by the conventional method.
SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art.
Semiconductor devices operate with the limitation of figure-of-merit (FOM) that (breakdown voltage x operating speed) maintains a generally constant value. Therefore, when the breakdown voltage is increased to increase the drive voltage, the operation speed is decreased, and the drive voltage and the operation speed are in a trade-off relationship. In order to overcome these physical limitations, a method of changing the structure of a device or introducing a material having a different characteristic into a material is provided.
In the case of a conventional FRD device, the concentration gradient is increased at a shallow junction in order to reduce the Trr, which leads to an increase in the snappy recovery operation. In the interval of 50 to 100 [kHz] (Electro Magnetic Interference) intensity of about 70 [dB] [V / m]. Therefore, by improving the soft recovery characteristic by changing the device structure, it should be reduced to 60 [dB] [V / m] or less to meet the standardization standard. Particularly, in the case of the FRD device based on the SBD in the related art, there is a limit in reducing the reverse recovery time (Trr) and the on-state voltage (Vf) at the same time.
The present invention provides a unique FRD device structure and a manufacturing method based on a self-aligning technique using a MOS gate as a mask.
An epitaxial layer is grown on a semiconductor substrate doped at a high concentration to control the impurity concentration distribution to improve soft recovery characteristics and to increase the forward current driving force by using the heterojunction epitaxial layer to reduce Vf. In addition, the MOS gate is used as a mast to self-align the ion implantation for the base layer and drive-in deeply to increase the radius of the boundary which is depleted when reverse bias is applied, Improves performance. The avalanche breakdown energy (EAS) is generally 50 to 150 mJ in the prior art, whereas the present invention can optimize the device structure and fabrication process to exceed 200 mJ. Similarly, a collector layer is formed by using a MOS gate as a mask to control the carrier injection in a region where the carrier path of the carrier is connected to the collector, the base, and the emitter layer. Which is dispersed and exhibits resistance to avalanche, is enhanced, and a manufacturing method thereof.
As described above, the present invention provides a new device structure and a manufacturing method that can improve Trr, Vf, leakage current, soft recovery, and EAS in the low voltage-high current FRD. That is, in the present invention, when the power is switched off, the minority carriers are rapidly recombined to disappear, thereby reducing Qr <20 [nC] and Trr <1 to 20 [ns]. Therefore, the present invention provides an HP-FRD new device having a VF (<0.3 to 1.1 V) and a trade-off with Trr as a whole in comparison with a conventional simple PIN junction.
Especially, high-speed operation in a rectifier for high-performance switching is important because it has a function to control the speed of several tens of nanoseconds. The total power consumption (Ptotal) of the device consists of four parts: P total = P on + P blocking + P swithing - on + P switching - off . The high operating speed of the high performance HP-FRD not only reduces power consumption (P swithing - on + P switching - off ) for high-frequency switching-on and switching-off, It is very important to suppress the occurrence and to stably protect the internal electronic circuits and low-voltage parts. In addition, the high E AS and forward current driving capability significantly improve long term reliability while reducing power consumption (P on ) in the on state, and the low reverse leakage current reduces the power consumption (off) P blocking , while improving reliability.
According to an aspect of the present invention, there is provided an HP-FRD comprising: a first conductive semiconductor substrate; a first conductive epitaxial layer grown on the semiconductor substrate, the first conductive epitaxial layer including a mesa pattern; A gate oxide film formed between the MOS gate and the epi layer; a second conductive type self-aligned to the MOS gate on the epi layer; A first conductivity type ion implantation layer self-aligned with the MOS gate on the second conductivity type ion implantation layer, and a second conductivity type ion implantation ohmic junction layer over the first conductivity type ion implantation layer .
As described above, according to the configuration of the present invention, the following effects can be expected.
In the present invention, Vf is reduced to 0.3 to 1.1 V and Trr is reduced to about 1 to 20 ns in the low-voltage-high-current driving in comparison with the device structure of the normal PIN-FRD and MPS-FRD, and soft recovery Thereby providing an improved low-voltage-high current HP-FRD new device. Since the self-alignment structure and the process technology using the MOS gate are applied, the conventional CMOS process technology can be utilized as compared with the SBD-based FRD device, and the manufacturing process is relatively simple and clear. The main applications are power semiconductor devices used in switching mode in the range of 0 ~ 2kV, 0 ~ 60A for low voltage - high current.
Using the features of the device structure, the accumulation of charge by the minority carriers in the low concentration epitaxial layer (n-layer) is reduced, and the minority carriers are quickly eliminated during switch-off. This can eliminate problems such as ringing, EMI, or power loss in which snappy recovery occurs. Similarly, when operating in a switching mode at a high temperature, on / off power consumption is reduced and EAS and leakage current characteristics are improved. The avalanche breakdown energy (EAS) is generally in the range of 50 to 150 mJ in the prior art, while the present invention can optimize the device structure and fabrication process to exceed 200 mJ. Particularly, by newly inventing a self-aligned structure and a device manufacturing process using a MOS gate as a mask, the uniformity and reproducibility can be improved and the reliability of the device can be increased. Accordingly, since the reverse leakage current is low and stable at high temperature operation, the conventional technology has an operating temperature of 100-150 DEG C, whereas the device of the present invention can increase the operation range to 150-200 DEG C. The HP-FRD device, which can operate at such a high temperature, is very useful for reducing power consumption in a circuit operating in a switching mode.
Therefore, when it is used in a circuit such as a filter or an SMPS-FRD, it is not necessary to use a snubber circuit, and miniaturization and cost reduction can be achieved. It is possible to reduce the power consumption and EMI in the electric power driving apparatus of the electric car, the solar battery and the LED lighting circuit, which have been used in recent years, as well as to enhance the effect on environmentally friendly and high efficiency.
Further, the present invention can be advantageously used to design a more novel RFD device by bonding with a PIN, Zener, or TVS diode semiconductor device including a higher voltage (for example, 400V to 3kV) FRD.
FIGS. 1A to 1I are cross-sectional views and characteristic diagrams showing configurations of various kinds of rectifier devices according to the prior art.
FIGS. 2A to 2C are cross-sectional views illustrating a configuration of an HP-FRD according to an embodiment of the present invention.
Figs. 3A to 3D are graphs showing the electrical operation characteristics of Figs. 2A to 2C. Fig.
Figs. 4A to 4H are cross-sectional views showing a manufacturing method of the embodiment of Fig. 2C.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the detailed description of known functions and configurations incorporated herein will be omitted when it may unnecessarily obscure the subject matter of the present invention.
The same reference numerals are used for portions having similar functions and functions throughout the drawings.
In addition, in the entire specification, when a part is referred to as being 'connected' to another part, it may be referred to as 'indirectly connected' not only with 'directly connected' . Also, to include an element does not exclude other elements unless specifically stated otherwise, but may also include other elements.
≪ Structural Example 1 >
2A illustrates a p + -n - structure for a low voltage according to an embodiment of the present invention.
2A, a p + layer 202 for a metal-semiconductor junction of an
In this structure, there is a pn junction interface between the p + layer 202 and the n - layer 203 on the
, And it is very important to increase the curvature radii r and R as compared with W. Thus, to increase the breakdown voltage, the thickness of the n - layer 203 must be increased, which represents a trade-off with slowing down the operation. Therefore, in order to solve this problem, it is necessary to change or optimize the device structure in the device design. According to the above device structure, although the structure is simple, there is a limitation in increasing the operating voltage due to the drawbacks of leakage current and hard recovery.
≪ Structural Example 2 >
FIG. 2B shows a Merged-PIN Schottky (MPS) diode structure according to one embodiment.
Referring to FIG. 2B, the p + layer 202 for the metal-semiconductor junction of the
≪ Structural Example 3 >
2C illustrates an HP-FRD structure according to the present invention.
Referring to FIG. 2C, a first
The HP-FRD according to the embodiment is characterized by a structure and a manufacturing method of forming a base and a collector layer by ion-implanting by self alignment using a
Therefore, various control of the
3A shows relatively typical forward IV characteristics in the device structure of Figs. 2A to 2C. For PIN diodes, both turn-on (VF) voltage and leakage current are high. EAS performance is relatively low, which causes additional problems such as power consumption and heat generation. For MPS diodes, the turn-on (VF) voltage is low and likewise the maximum allowable value of the forward drive current is low. In the case of the PIN-FRD and MPS-FRD structures, the HP-FRD structure can be reduced to a level of 0.3 to 1.1 [V], compared to a forward voltage (V F ) of 0.7 to 2 [V] . In particular, PIN-FRD and MPS-FRD diode technologies are subject to limited controllable power because they can experience a snap-off due to limitations in current drive capability in forward operation.
FIGS. 3B and 3C show the change in current voltage at the time of switching-on and switching-off. In the PIN diode structure, snappy recovery phenomenon is very serious and Trr is also large. In order to reduce power consumption by switching, it is necessary to solve the problem that Vfm is greatly increased due to overshoot in the case of switching-on. On the other hand, in the case of switching-off, it is necessary to reduce the size of the Vrm. It is important to reduce the reverse recovery time (trr), and the EMI noise caused by the snappy recovery operation It is necessary to prevent the generation or the reliability of the interface from deteriorating.
3B and 3C, Vfm and Vrm must be reduced as much as possible, since high voltage is applied on the circuit in the switching operation and at the same time switching power consumption is increased. Basically, it is important that an inductance component is reduced because an inductance component is present at both ends of the anode and cathode electrodes of the device as shown in the equation of V = L (dI / dt) and a voltage is applied. In the junction of the device, the DC resistance component and the mobility of the minority carriers must be adjusted to reduce Vfm as the response time at which the minority carrier is injected through the junction in the case of the forward applied voltage. As described above, in the case of the reverse applied voltage in the junction of devices, the response time in which the minority carriers are exhausted through recombination, the control of the lifetime using the time killer and the optimization of the device structure to reduce Vrm Should be adjusted. The soft recovery characteristic of the HP-FRD in FIG. 3C is also superior to the PIN-FRD, thereby minimizing EMI generation and providing a very important advantage in maintaining stable circuit operation.
Figure 3d is a semi-log graph of the forward current-voltage characteristics of SBR, SBD, and HP-FRD. The disadvantage of SBR is that the current drive is low at low voltage compared with SBD. Therefore, the power consumption of SBR is higher than that of SBD for low power in switching operation. That is, below the cross-point of the figure, the SBD is better than the SBR. The HP-FRD device according to the present invention increases the current driving force at a low voltage because the MOS driving part increases twice, so that the performance is remarkably improved as compared with the SBD and SBR device as shown in FIG. 3D.
The MPS diode structure also improves the disadvantages of the PIN diode structure in particular, but it has a drawback that it is difficult to secure the thermal stability of the Schottky interface, although it has an advantage of reducing the VF. SBD has a small Vf, but has a high leakage current, is limited in terms of current drive reliability, and similarly, it is difficult to raise the drive voltage. The SBR device structure is less efficient than SBD under the conditions of low power driving. This is because the overall channel resistance is high in the low power section driven by the low voltage and it is possible to improve the efficiency in the low power driving section.
Particularly, by applying a time killer in the HP-FRD of the present invention, the current handling capability is improved, and the fast recovery and the soft recovery characteristics are improved, A diode for switching can be obtained.
<Method Example>
FIGS. 4A to 4I are cross-sectional views illustrating a method of manufacturing the HP-FRD according to the cross-sectional structure of FIG. 2D according to an embodiment of the present invention.
4A is a cross-sectional view of the first conductive
4B is a cross-sectional view illustrating a MOS region formed by photolithography using a photoresist and forming a
4C shows the use of the polysilicon
FIG. 4D etches polysilicon with a dry etch to form a gate in the form of a side-wall. 4D shows a cross-sectional structure in which a polycrystalline silicon thin film (404 in FIG. 4C) is deposited and dry etched to form a side wall. The sidewall formed of the polycrystalline silicon
Next, the second conductive impurity is ion-implanted, followed by heat treatment at a high temperature to drive-in. At this time, the
FIG. 4E shows a cross-sectional structure in which a pattern is formed by lithography using a photoresist and ion-implanted with a first conductivity type (e.g., n + ) impurity using the same as a mask and subjected to activation heat treatment. In this process step, the first conductive type ion-implanted
4F, a photoresist pattern is formed, and a second conductive type (e.g., p + ) impurity is ion-implanted using the photoresist pattern as a mask. In this process step, a p + ion implanted layer is formed. And the ion-implanted
4G shows a cross-sectional structure in which the
4H shows a cross-sectional structure of a first metal-
In order to complete the device of the present invention, the rear surface of the
In the above-described HP-FRD device, the metal thin film formed on the upper surface of the semiconductor substrate functions as an anode, and the metal thin film formed on the rear surface of the semiconductor substrate acts as a cathode do.
The present invention can be manufactured and manufactured in various modified forms through simplification and application based on the structure using a plurality of semiconductor junction layers as described above. For example, in the present invention, a method of fabricating a semiconductor device using a silicon semiconductor substrate is described as an example. However, the device structure and fabrication method of the present invention can be applied to a compound semiconductor such as GaAs, InP, GaN, SiC, SiGe, Can be used. As is known, it is general to optimize the mass production of a product in comparison with the performance of a product in terms of yield, reliability, productivity, and production cost.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. To those skilled in the art.
400: semiconductor substrate 401: epi layer
402: mesa pattern 403: thermal oxide film
404: Silicon thin film 405: MOS gate
406A and 406B: second conductive type ion-implanted
408A, 408B: ion-implanted Ohmic bonding layer 409: gate oxide film
410: First metal-semiconductor ohmic junction 411: Second metal-semiconductor ohmic junction
Claims (10)
A first conductive type epitaxial layer grown on the semiconductor substrate, the first conductive type epitaxial layer including a mesa pattern of upper and side walls formed by partially removing dry etching;
A MOS gate in the form of a side wall integrally formed on the upper portion and the sidewall of the mesa pattern;
A gate oxide film formed between the MOS gate and the epi layer;
A second conductive type ion implantation layer self-aligned to the MOS gate on the epi layer;
A first conductive type ion implantation layer self-aligned to the MOS gate on the second conductive type ion implantation layer; And
A second conductive type ion-implanted ohmic contact layer on the second conductive type ion-implanted layer; 0.0 > HP-FRD. ≪ / RTI >
The semiconductor substrate is doped with an n-type high-concentration impurity (10 18 to 10 20 cm -3 ) to have low resistance, and the epitaxial layer is doped with n-type low-concentration impurity (10 13 to 10 16 cm -3 ) And a high resistance.
Wherein a height of the mesa pattern corresponding to the sidewall is greater than a sum of thicknesses of the second conductive type ion-implanted layer and the first conductive type ion-implanted layer.
Wherein the MOS gate forms a vertical MOS channel formed from the top downward through the sidewalls of the mesa pattern and a horizontal MOS channel formed horizontally at the bottom of the sidewalls of the mesa pattern. .
A first metal-semiconductor ohmic junction formed on the epi layer; And
A second metal-semiconductor ohmic junction formed on the bottom surface of the semiconductor substrate; Further comprising an HP-FRD.
Wherein the first metal-semiconductor ohmic junction is used as an anode electrode for simultaneously connecting the first conductive type ion-implanted layer, the second conductive type ion-implanted Ohmic contact layer, and the MOS gate,
Wherein the second metal-semiconductor ohmic junction is used as a cathode electrode.
Etching a portion of the epilayer to form a mesa pattern;
Forming a thermal oxide film on the epi layer;
Depositing a silicon thin film of a second conductivity type;
Etching the silicon thin film to form a side-wall type MOS gate;
Forming a second conductive type ion implanted layer in the first conductive type epilayer to a predetermined depth using the MOS gate as a self-aligned mask;
Forming a first conductivity type ion implantation layer in the second conductivity type ion implantation layer to a predetermined depth by using the MOS gate as a self alignment mask;
Forming an ion-implanted Ohmic contact layer of a second conductivity type in the first conductive type ion-implanted layer and the second conductive type ion-implanted layer to a predetermined depth;
Removing the thermally oxidized film to form a gate oxide film except for a region where the MOS gate is covered;
Forming a metal thin film for metal-semiconductor ohmic contact on the epi layer; And
Forming a metal thin film for metal-semiconductor ohmic contact on the bottom surface of the semiconductor substrate; FRD. ≪ / RTI >
The second conductive type ion implantation layer, a low concentration p-type impurity is doped with (10 16 ~10 19 cm -3) , the second conductive type ion implantation ohmic contact layer has a high concentration of impurities (10, 18 of p-type To 10 < 21 > cm < -3 >).
Depositing and diffusing a heavy metal thin film selected from Au, Pt, or Mo on the bottom surface of the semiconductor substrate after forming the thermal oxide film; Further comprising the steps of:
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| KR101680147B1 (en) | 2015-03-09 | 2016-11-29 | 퍼스트 실리콘 주식회사 | High speed switching diode with high breakdown voltage |
| KR101737966B1 (en) | 2015-12-24 | 2017-05-29 | 주식회사 시지트로닉스 | Semiconductor element and method thereof using hetero tunneling junction |
| CN108735823A (en) * | 2018-06-01 | 2018-11-02 | 电子科技大学 | A kind of diode and preparation method thereof |
| CN115295613A (en) * | 2022-10-08 | 2022-11-04 | 烟台台芯电子科技有限公司 | Fast recovery diode structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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