CN211480025U - 一种晶体管结构 - Google Patents

一种晶体管结构 Download PDF

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CN211480025U
CN211480025U CN202020257664.7U CN202020257664U CN211480025U CN 211480025 U CN211480025 U CN 211480025U CN 202020257664 U CN202020257664 U CN 202020257664U CN 211480025 U CN211480025 U CN 211480025U
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substrate
structures
gate
side wall
oxide layer
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张静
金起準
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Nexchip Semiconductor Corp
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Abstract

本实用新型公开了一种晶体管结构，属于半导体技术领域。本实用新型的晶体管结构包括：基底；多个栅极结构，其设置在所述基底上，相邻所述栅极结构之间设有预设间隔距离；侧墙结构，其设置在每个所述栅极结构的两侧；台阶结构，其设置在所述侧墙结构与所述基底的连接处；薄膜层，其设置在所述基底上，且覆盖所述基底、所述多个栅极结构、所述侧墙结构和所述台阶结构。本实用新型解决了由于栅极结构侧墙与基底处薄膜生长速率的差异，造成的在薄膜沉积过程中出现深坑或孔洞等缺陷的问题，这避免了后继接触管道的漏电及器件的失效，从而保证了晶体管产品的质量。

Description

一种晶体管结构
技术领域
本实用新型属于半导体技术领域，特别是涉及一种晶体管结构。
背景技术
为了隔离存储器单元源漏区和栅极区，以避免源漏区离子注入区域离栅极区太近而引发短沟道效应，同时保护栅极区的侧壁，在栅极区的侧壁通常制作有侧墙(spacer)。而对于部分存储器单元，相邻侧墙之间区域的深宽比对于薄膜沉积能力要求苛刻，即使依靠高密度等离子体化学气相沉积(HDP)这种填洞能力良好的工艺，也无法覆盖较大的深坑，侧墙与基底处薄膜生长速率的差异，容易在“深坑”中间造成凹陷或夹断，且严重时，会使得两侧墙肩部形成缝隙或孔洞，造成后继接触管道的漏电，器件失效，从而影响存储器产品的质量。另外由于侧墙的一个重要作用就是在后继较深的离子植入时保护轻掺杂漏极(LDD)，源/漏扩展(SDE)，袋植入工程(Halo)等区域，从而既有效的抑制短通道效应，又降低因浅接面造成源/漏极高阻值影响。因此必须要求制程能够严格控制源/漏极区域和大小，这也限制着现有的侧墙结构不能进行直接减薄调整。
实用新型内容
本实用新型的目的在于提供一种晶体管结构，解决了由于栅极结构侧墙与基底处薄膜生长速率的差异，造成的在薄膜沉积过程中出现深坑或孔洞等缺陷的问题，这避免了后继接触管道的漏电及器件的失效，从而保证了晶体管产品的质量。
为解决上述技术问题，本实用新型是通过以下技术方案实现的：
本实用新型提供了一种晶体管结构，其包括：
基底；
多个栅极结构，其设置在所述基底上，相邻所述栅极结构之间设有预设间隔距离；
侧墙结构，其设置在每个所述栅极结构的两侧；
台阶结构，其设置在所述侧墙结构与所述基底的连接处；
薄膜层，其设置在所述基底上，且覆盖所述基底、所述多个栅极结构、所述侧墙结构和所述台阶结构。
在本实用新型的一个实施例中，所述晶体管结构还包括栅极氧化层，所述栅极氧化层设置在所述基底上，且位于所述基底与所述多个栅极结构之间。
在本实用新型的一个实施例中，所述栅极氧化层为氧化硅层。
在本实用新型的一个实施例中，所述预设间隔距离为80-110nm。
在本实用新型的一个实施例中，所述侧墙结构为氧化硅层。
在本实用新型的一个实施例中，所述台阶结构为氧化硅层。
在本实用新型的一个实施例中，所述侧墙结构的厚度为6-10nm。
在本实用新型的一个实施例中，所述台阶结构的厚度为6-10nm。
在本实用新型的一个实施例中，所述栅极结构为堆叠栅结构。
在本实用新型的一个实施例中，所述基底为硅、锗、硅锗、碳化硅、绝缘体上覆硅(SOI)、绝缘体上覆锗(GOI)、砷化镓等Ⅲ、Ⅴ族化合物中的一种。
本实用新型通过扩大相邻栅极结构侧墙之间的区域空间，使薄膜的沉积更加均匀，沉积过程的界面更加平整，有效的避免了在间隙沉积薄膜容易产生缝隙和孔洞的问题，扩大相邻栅极结构侧墙之间的区域空间，可以有效的避免由于侧墙处薄膜与靠近基底处薄膜生长速率差异，而在侧墙与基底之间造成的薄膜晶体结构的凹陷和夹断，避免了后期器件的漏电和失效。本实用新型通过侧墙结构和台阶结构保证了对栅极结构和基底的覆盖，确保后续的离子植入过程不会干扰前期的制程区域。
当然，实施本实用新型的任一产品并不一定需要同时达到以上所述的所有优点。
附图说明
为了更清楚地说明本实用新型实施例的技术方案，下面将对实施例描述所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本实用新型的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本实用新型一种晶体管结构的制备方法流程图；
图2为图1中步骤S1的剖面示意图；
图3为图1中步骤S2和S3的剖面示意图；
图4-图5为图1中步骤S4的剖面示意图；
图6为图1中步骤S5的剖面示意图；
图7为图1中步骤S6的剖面示意图。
具体实施方式
下面将结合本实用新型实施例中的附图，对本实用新型实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本实用新型一部分实施例，而不是全部的实施例。基于本实用新型中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本实用新型保护的范围。
请参阅图1至图7所示，本实用新型提供了一种晶体管结构，其包括：基底100、多个栅极结构200、侧墙结构600和台阶结构700和薄膜层800。
请参阅图1至图7所示，所述基底100可以包括存储单元区域和外围电路区域，本实施例中仅以存储单元区域为例，但可以理解本实用新型的方法过程在外围电路区域也同样适用。在基底100的存储单元区域上设有多个栅极结构200，在栅极结构200上设有覆盖所述栅极结构200的介质层，所述介质层包括在栅极结构200表面依次形成的氧化硅层300和氮化硅层400。
请参阅图1至图7所示，在其他一些实施例中，在基底100和多个栅极结构200之间还可以形成栅极氧化层900，栅极氧化层900充当栅极结构200与基底100之间的绝缘介质，本实施例中，栅极氧化层例如可以由二氧化硅材料制成。
请参阅图1至图7所示，所述基底100的材料可以为硅、锗、硅锗或碳化硅等，也可以是绝缘体上覆硅(SOI)或者绝缘体上覆锗(GOI)，或者还可以为其他的材料，例如砷化镓等Ⅲ、Ⅴ族化合物。所述基底100可以根据设计需求注入一定的掺杂粒子以改变电学参数，例如上述基底100可以是一p型或n型硅基底100。
请参阅图1至图7所示，在存储器例如闪存的制造工艺中，在同一基底100上往往同时进行存储单元、逻辑晶体管和高压晶体管的制造工艺，其中，存储单元和高压晶体管为高压区域，用于形成闪存，本领域技术人员应当理解，利用本实用新型的工艺在同一基底100上也可以制作逻辑电路。
请参阅图1至图7所示，本实施例中的栅极结构200可以为堆叠栅结构，具体包括基底100表面依次堆叠形成的栅极氧化层900、浮栅和控制栅，浮栅和控制栅之间形成有隧穿氧化层，控制栅和浮栅通常由多晶硅制成，能通过隧穿效应进行数据的写入和擦除。
请参阅图1至图7所示，在每个栅极结构200的两侧形成侧墙结构600，同时在侧墙结构600与基底100之间形成台阶结构700，其中侧墙结构600和台阶结构700为氧化硅层300，侧墙结构600的厚度例如为6-10nm，台阶结构700的厚度例如为6-10nm。
请参阅图1至图7所示，在源漏极离子注入后形成的侧墙结构600较现有的栅极结构200之间的侧墙厚度要薄，这使得相邻栅极结构200之间的区域空间变大，从而有效的保证了后期薄膜层800沉积过程界面的平整度，防止在相邻栅极结构200之间形成缝隙和孔洞等缺陷。特别是在深宽比比较特殊的闪存存储器结构中，这种效果尤其明显。而台阶结构700的设置使得在扩大相邻侧墙结构600之间区域的同时保证了基底100的覆盖区域没有减小，从而确保后期的制程不会对前期的制程造成影响。
请参阅图1所示，本实用新型中晶体管结构的制备方法，其至少包括以下步骤：
S1.提供一基底100，所述基底100上设有多个栅极结构200，相邻所述栅极结构200之间设有预设间隔距离；
S2.在每个所述栅极结构200的两侧壁上形成第一侧墙结构500，所述第一侧墙结构500包括氧化硅层300和氮化硅层400，同时去除相邻所述第一侧墙结构500之间且位于所述基底100上的所述氮化硅层400；
S3.在所述基底100上进行离子注入；
S4.去除相邻所述第一侧墙结构500之间且位于所述基底100上的所述氧化硅层300，暴露相邻所述第一侧墙结构500之间的所述基底100；
S5.去除所述第一侧墙结构500中的所述氮化硅层400，形成侧墙结构600和所述台阶结构700，所述侧墙结构600设置在每个所述栅极结构200的两侧，所述台阶结构700设置在所述侧墙结构600与所述基底100之间；
S6.在所述基底100上形成薄膜层800，所述薄膜层800覆盖所述基底100、所述多个栅极结构200、所述侧墙结构600和所述台阶结构700。
以下结合图2至图7对本实用新型一种存储器的制备方法进行更详细的说明。
请参阅图2所示，在步骤S1中，首先提供一基底100，所述基底100可以包括存储单元区域和外围电路区域，本实施例中仅以存储单元区域为例，但可以理解本实用新型的方法过程在外围电路区域也同样适用。在基底100的存储单元区域上设有多个栅极结构200，在栅极结构200上设有覆盖所述栅极结构200的介质层，所述介质层包括在栅极结构200表面依次形成的氧化硅层300和氮化硅层400。
请参阅图2所示，在其他一些实施例中，在步骤S1中，还可以在所述基底100上形成栅极氧化层900，栅极氧化层900的材料例如可为氧化硅，本实施例中，例如可通过炉管氧化，快速热退火氧化，原位水蒸汽氧化或其他热氧化法形成氧化硅材质的栅极氧化层900。
请参阅图2所示，在步骤S1中，所述基底100的材料可以为硅、锗、硅锗或碳化硅等，也可以是绝缘体上覆硅(SOI)或者绝缘体上覆锗(GOI)，或者还可以为其他的材料，例如砷化镓等Ⅲ、Ⅴ族化合物。所述基底100可以根据设计需求注入一定的掺杂粒子以改变电学参数，例如上述基底100可以是一p型或n型硅基底100。
请参阅图2所示，在步骤S1中，在存储器例如闪存的制造工艺中，在同一基底100上往往同时进行存储单元、逻辑晶体管和高压晶体管的制造工艺，其中，存储单元和高压晶体管为高压区域，用于形成闪存，本领域技术人员应当理解，利用本实用新型的工艺在同一基底100上也可以制作逻辑电路。
请参阅图2所示，在步骤S1中，本实施例中的栅极结构200可以为堆叠栅结构，具体包括基底100表面依次堆叠形成的栅极氧化层900、浮栅和控制栅，控制栅和浮栅通常由多晶硅制成，能通过隧穿效应进行数据的写入和擦除。相邻栅极结构200之间的预设间隔距离为80-110nm。
请参阅图2所示，在步骤S1中，本实施例中栅极结构200的形成可利用化学气相沉积、光刻等方法，具体可以用本领域技术人员公知的方法形成栅极结构200，本实施例不再详述。因此，在本步骤中，可以认为在基底100上已经完成了但不限于下列工艺步骤：在存储单元区域进行的阱注入，例如深N阱注入，并且，在存储单元区域中均已形成有隔离沟道，例如浅沟槽隔离结构。此外，图中仅示出了两个栅极结构200，但是，本领域技术人员应当理解，为使得图示能清楚的表达本申请的核心思想，图中仅以示意图的形式表示了存储器部分存储单元区域的器件和结构，但这并不代表本实用新型涉及的存储器工艺仅包括这些部分，公知的存储器结构和工艺步骤也可包含在其中。
请参阅图2所示，在步骤S1中，形成所述栅极结构200之后，可以在栅极结构200的表面形成ON(oxide-nitride，即氧化物-氮化物)介质层，ON介质层覆盖栅极结构200。本实施例中，所述ON介质层包括在栅极结构200表面依次形成的氧化硅层300和氮化硅层400，其中氧化硅层300例如可以为氮氧化硅或者二氧化硅。具体的，氧化硅层300覆盖栅极结构200的表面，包括侧壁以及暴露的基底100表面，氮化硅层400叠加形成在氧化硅层300的表面。
请参阅图2所示，在步骤S1中，上述ON介质层可利用化学气相沉积工艺形成。本实施例中，ON介质层的各层厚度可以采用现有工艺设定，且各层厚度可为常规厚度。
请参阅图3所示，在步骤S2中，制作第一侧墙结构500，所述第一侧墙结构500覆盖栅极结构200的侧壁，所述第一侧墙结构500包括氧化硅层300和氮化硅层400。
请参阅图3所示，在步骤S2中，具体的，可以利用干法刻蚀工艺，在垂直于基底100的方向向下刻蚀ON介质层，从而去除形成于栅极结构200的顶部以及相邻第一侧墙结构500之间位于基底100上的氮化硅层400，暴露栅极结构200顶部表面及相邻第一侧墙结构500之间位于基底100上的氧化硅层300。
请参阅图3所示，在步骤S2中，干法刻蚀可采用由HBr、HeHBr、Cl2、O2、N2、NF3、Ar或HeO2和CF4组成的组中的一种或多种作为刻蚀气体。
请参阅图3所示，在步骤S3中，在基底100上进行源漏离子注入过程，形成源区和漏区，对所述基底100进行源漏注入以形成源区和漏区的方法可以采取公知的方法，在进行源漏注入过程中，为了避免对基底100上非注入区域造成影响，可以用光阻遮挡非注入区域。
请参阅图3所示，在步骤S3中，本实施例中，第一侧墙结构500可以避免源区和漏区离栅极结构200太近而引发短沟道效应，同时保护栅极结构200的侧壁。
请参阅图4所示，在步骤S4中，去除相邻第一侧墙结构500之间，位于基底100上的氧化硅层300，暴露此处的基底100，在一些实施例中，去除相邻第一侧墙结构500之间，位于基底100上的氧化硅层300及栅极氧化层，暴露此处的基底100，具体的，可以利用湿法刻蚀工艺去除氧化硅层300，本实施例中，例如采用HF酸溶液去除此处基底100上的氧化硅层300。在其他实施例中，还可以采用干法刻蚀工艺，并且选择对氧化硅和氮化硅具有高刻蚀选择比，例如大于10的干法刻蚀条件，去除氧化硅层300。
请参阅图5所示，在步骤S4中，在暴露的基底100及栅极结构200顶部表面处沉积Co或Ni，形成金属硅化物层1000,作用是降低栅极顶部接触窗和基底100的接触电阻。
请参阅图6所示，在步骤S5中，去除剩余的氮化硅层400，在每个栅极结构200的两侧形成侧墙结构600，同时在侧墙结构600与基底100之间形成台阶结构700，其中侧墙结构600的厚度例如为6-10nm，台阶结构700的厚度例如为6-10nm，台阶结构700的长度可以根据具体的产品进行调整，这里只是举例，并不做具体限定。具体的，可以利用湿法刻蚀工艺中具有选择性腐蚀的溶液去除氮化硅层400，本实施例中，例如采用磷酸溶液去除剩余的氮化硅层400，由于磷酸溶液对氮化硅层400和氧化硅层300具有选择性腐蚀的作用，可以仅对氮化硅层400进行腐蚀，而对于氮化硅层400却腐蚀很少，所以选择磷酸作为刻蚀溶液可以完全去除氮化硅层400而保留氧化硅层300。氮化硅层400被移除后，扩大了后期薄膜沉积的空间，减少薄膜沉积界面出现凹陷，有效的保证了薄膜沉积界面的平整度，防止在相邻栅极结构200之间形成缝隙和孔洞。同时前期制程区域，例如漏端轻掺杂区、源/漏扩展区，由于有氧化硅层300的保护，可以确保不会受到后期更深的离子注入的影响，有效的提高了最终产品的质量。
请一并参阅图7，在步骤S6中，在基底100上沉积电介质薄膜层800，并进行常规的后续制程步骤，从而获得本实用新型的存储器结构。
请一并参阅图7，在步骤S6中，本实用新型的电介质薄膜层800可以为层间介电质(ILD)，材料例如选用二氧化硅(SiO2)，硼硅玻璃(PSG)等，可以采用化学气相沉积的方法沉积电介质薄膜，例如采用APCVD、LPCVD或PECVD中的一种。
请一并参阅图1至图6所示，综上所述，通过扩大相邻侧墙结构600之间的区域空间，减少薄膜沉积界面出现凹陷，从而有效的保证了后期薄膜层沉积过程界面的平整度，防止在相邻栅极结构200之间形成缝隙和孔洞等缺陷，特别是在深宽比大的存储器结构中，这种效果尤其明显。在扩大相邻侧墙结构600之间区域的同时保证了基底100的覆盖区域没有减小，从而确保后期的制程不会对前期的制程造成影响。
以上公开的本实用新型选实施例只是用于帮助阐述本实用新型。优选实施例并没有详尽叙述所有的细节，也不限制该实用新型仅为所述的具体实施方式。显然，根据本说明书的内容，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本实用新型的原理和实际应用，从而使所属技术领域技术人员能很好地理解和利用本实用新型。本实用新型仅受权利要求书及其全部范围和等效物的限制。

Claims (10)

1.一种晶体管结构，其特征在于，其包括：
基底；
多个栅极结构，其设置在所述基底上，相邻所述栅极结构之间设有预设间隔距离；
侧墙结构，其设置在每个所述栅极结构的两侧；
台阶结构，其设置在所述侧墙结构与所述基底的连接处；
薄膜层，其设置在所述基底上，且覆盖所述基底、所述多个栅极结构、所述侧墙结构和所述台阶结构。
2.根据权利要求1所述一种晶体管结构，其特征在于，所述晶体管结构还包括栅极氧化层，所述栅极氧化层设置在所述基底上，且位于所述基底与所述多个栅极结构之间。
3.根据权利要求2所述一种晶体管结构，其特征在于，所述栅极氧化层为氧化硅层。
4.根据权利要求1所述一种晶体管结构，其特征在于，所述预设间隔距离为80-110nm。
5.根据权利要求1所述一种晶体管结构，其特征在于，所述侧墙结构为氧化硅层。
6.根据权利要求1所述一种晶体管结构，其特征在于，所述台阶结构为氧化硅层。
7.根据权利要求1所述一种晶体管结构，其特征在于，所述侧墙结构的厚度为6-10nm。
8.根据权利要求1所述一种晶体管结构，其特征在于，所述台阶结构的厚度为6-10nm。
9.根据权利要求1所述一种晶体管结构，其特征在于，所述栅极结构为堆叠栅结构。
10.根据权利要求1所述一种晶体管结构，其特征在于，所述基底为硅基底。
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CN107994025B (zh) * 2017-12-06 2019-01-18 武汉新芯集成电路制造有限公司 增加浮栅型闪存侧墙宽度的方法以及浮栅型闪存结构
CN211480025U (zh) * 2020-01-02 2020-09-11 合肥晶合集成电路有限公司 一种晶体管结构

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CN111261633A (zh) * 2020-01-02 2020-06-09 合肥晶合集成电路有限公司 一种晶体管结构及其制备方法
CN115295494A (zh) * 2022-10-08 2022-11-04 合肥晶合集成电路股份有限公司 一种半导体结构的制作方法

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