CN211455672U - 一种半导体封装结构 - Google Patents

一种半导体封装结构 Download PDF

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CN211455672U
CN211455672U CN201922351399.9U CN201922351399U CN211455672U CN 211455672 U CN211455672 U CN 211455672U CN 201922351399 U CN201922351399 U CN 201922351399U CN 211455672 U CN211455672 U CN 211455672U
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redundant
chip
bonding
bonding wire
bonding pad
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朱卫华
张明俊
李全兵
牛传凯
李国奎
李中伟
顾颖
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Abstract

本实用新型涉及一种半导体封装结构，它包括基板(1)，所述基板(1)表面设置有芯片(2)，所述芯片(2)外围设置大焊盘(3)，所述芯片(2)与大焊盘(3)之间通过功能焊线(4)相连接，所述大焊盘(3)上设置有若干冗余焊线(5)，所述冗余焊线(5)采用焊线或焊球形式,所述基板(1)上表面、芯片(2)、大焊盘(3)、功能焊线(4)、冗余焊线(5)包封在塑封树脂内。本实用新型一种半导体封装结构，它通过在多余焊垫面积上进行冗余焊线，能够增加与塑封树脂的结合力，防止分层现象产生。

Description

一种半导体封装结构
技术领域
本实用新型涉及一种半导体封装结构，属于半导体封装技术领域。
背景技术
传统封装电子产品中多使用焊线作业，因设计需求会有面积较大的焊垫，较大的焊垫面积意味着较大的铜面露出，铜与塑封树脂的接合面积大，两者之间易出现分层的缺陷，为了增强铜与塑封树脂的结合力，可在铜面上增加凹槽设计或者预喷涂绝缘材料，但是同一焊垫可能打多根焊线，焊线间距太密，无法对铜面进行上述处理。
实用新型内容
本实用新型所要解决的技术问题是针对上述现有技术提供一种半导体封装结构，它通过在多余焊垫面积上进行冗余焊线，能够增加与塑封树脂的结合力，防止分层现象产生。
本实用新型解决上述问题所采用的技术方案为：一种半导体封装结构，它包括基板，所述基板表面设置有芯片，所述芯片外围设置大焊盘，所述芯片与大焊盘之间通过功能焊线电性连接，所述大焊盘上设置有若干冗余焊线，所述冗余焊线采用焊线或焊球形式形成，所述基板上表面、芯片、大焊盘、功能焊线、冗余焊线包封在塑封树脂内。
优选的，所述功能焊线和冗余焊线布满大焊盘区域，所述大焊盘外露面积小于0.035mm2。
优选的，所述大焊盘为单边长度超过1000um或整体面积超过300000um2的焊盘。
优选的，所述冗余焊线采用焊球时，焊球与焊球之间的距离大于26um。
优选的，所述冗余焊线设置于同一大焊盘上或同功能的大焊盘与大焊盘之间。
与现有技术相比，本实用新型的优点在于：
1、本实用新型在不改变现有的制程基础上，通过冗余焊线的方式，减少大焊盘与塑封树脂的直接接触面积，防止分层问题，提高产品可靠性；
2、本实用新型冗余焊线与正常的焊线可同时作业，不需要额外的工艺流程，成本变化小。
附图说明
图1为本实用新型一种半导体封装结构实施例1的示意图。
图2为图1的截面示意图。
图3为本实用新型一种半导体封装结构实施例2的示意图。
图4为图3的截面示意图。
图5为本实用新型一种半导体封装结构实施例3的示意图。
图6为图5的截面示意图。
其中：
基板1
芯片2
大焊盘3
功能焊线4
冗余焊线5。
具体实施方式
以下结合附图实施例对本实用新型作进一步详细描述。
实施例1：
如图1、图2所示，本实施例中的一种半导体封装结构，它包括基板1，所述基板1表面设置有芯片2，所述芯片2外围设置有大焊盘3，所述芯片2与大焊盘3之间通过功能焊线4电性连接，所述大焊盘3上设置有若干冗余焊线5，所述冗余焊线5采用焊线形式形成，所述基板1上表面、芯片2、大焊盘3、功能焊线4、冗余焊线5包封在塑封树脂内；
所述功能焊线4和冗余焊线5布满大焊盘3区域，所述大焊盘3外露面积小于0.035mm2；
所述大焊盘3为单边长度超过1000um或整体面积超过300000um2的焊盘。
实施例2：
如图3、图4所示，实施例2与实施例1的区别在于：所述冗余焊线5采用焊球形式；
焊球与焊球之间的距离大于26um；
实施例3：
如图5、图6所示，实施例3与实施例1的区别在于：所述冗余焊线5设置于同一大焊盘3上或同功能的大焊盘3与大焊盘3之间。
除上述实施例外，本实用新型还包括有其他实施方式，凡采用等同变换或者等效替换方式形成的技术方案，均应落入本实用新型权利要求的保护范围之内。

Claims (4)

1.一种半导体封装结构，其特征在于：它包括基板(1)，所述基板(1)表面设置有芯片(2)，所述芯片(2)外围设置大焊盘(3)，所述芯片(2)与大焊盘(3)之间通过功能焊线(4)相连接，所述大焊盘(3)上设置有若干冗余焊线(5),所述冗余焊线(5)采用焊线或焊球形式形成，所述基板(1)上表面、芯片(2)、大焊盘(3)、功能焊线(4)、冗余焊线(5)包封在塑封树脂内。
2.根据权利要求1所述的一种半导体封装结构，其特征在于：所述功能焊线(4)和冗余焊线(5)布满大焊盘(3)区域，所述大焊盘(3)外露面积小于0.035mm2。
3.根据权利要求1所述的一种半导体封装结构，其特征在于：所述冗余焊线(5)采用焊球时，焊球与焊球之间的距离大于26um。
4.根据权利要求1所述的一种半导体封装结构，其特征在于：所述冗余焊线(5)设置于同一大焊盘(3)上或同功能的大焊盘(3)与大焊盘(3)之间。
CN201922351399.9U 2019-12-24 2019-12-24 一种半导体封装结构 Active CN211455672U (zh)

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