CN211295075U - 一种芯片封装结构 - Google Patents

一种芯片封装结构 Download PDF

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CN211295075U
CN211295075U CN202020260446.9U CN202020260446U CN211295075U CN 211295075 U CN211295075 U CN 211295075U CN 202020260446 U CN202020260446 U CN 202020260446U CN 211295075 U CN211295075 U CN 211295075U
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copper frame
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李世雄
陆阳
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Joulwatt Technology Co Ltd
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Joulwatt Technology Hangzhou Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
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    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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Abstract

本实用新型是一种芯片封装结构,包括铜质框架体,承载在所述铜质框架体上的至少一个芯片,将所述芯片包封在所述铜质框架体上的塑封层,其中所述铜质框架具有粗糙的第一表面,所述塑封层的至少部分覆盖在所述铜质框架体的第一表面上。本实用新型解决现有的半导体封装结构中,塑封材料与引线框架结合的部位容易分层的问题。从而增加器件整体的可靠性和稳定性。

Description

一种芯片封装结构
技术领域
本实用新型涉及半导体技术领域,尤其是涉及一种芯片的封装结构。
背景技术
半导体塑料封装元器件基本采用多种物质相结合的封装体,其中的材料主要有金属引线框、环氧树脂、金属丝、高分子粘合剂、金属镀层等。但是,不同的物质会因温度、湿度、振动等因素的变化而容易造成在不同物质之间产生分层;尤其是在高温环境中,由于不同物质的热膨胀系数是不一样的,所以会在水平方向或垂直方向产生不同程度的拉、推应力,进而在不同物质间产生分层。
请参见图1,图1是一种现有的芯片封装结构示意图,如图所示,该芯片封装结构包括引线框架,该引线框架一般是铜为主体,然后在铜质的引线框架表面镀银。在塑封材料层包封芯片之后,塑封材料与镀银表面接触结合。但是镀银层的框架表面比较光滑,和塑封材料结合不会那么牢固,尤其是塑封体大于6mm以上时,还有可能因为机械应力的原因导致应力分层,使得塑封材料与银表面接触的地方分层,如图中所示,最终导致半导体塑料封装元器件的功能缺陷或早期失效等问题。
因此,有必要针对现有技术中存在的技术问题,提供一种可以改善半导体塑料封装体内元器件分层的封装结构。
发明内容
有鉴于此,本实用新型的目的在于提出一种芯片封装结构,能够解决现有的半导体封装结构中,塑封材料与引线框架结合的部位容易分层的问题。从而增加器件整体的可靠性和稳定性。
根据本实用新型的目的提出的一种芯片封装结构,包括铜质框架体,承载在所述铜质框架体上的至少一个芯片,将所述芯片包封在所述铜质框架体上的塑封层,其中所述铜质框架具有粗糙的第一表面,所述塑封层的至少部分覆盖在所述铜质框架体的第一表面上。
优选地,所述铜质框架体包括至少一个基岛,所述至少一个芯片承载在所述至少一个基岛上。
优选地,所述铜质框架体还包括至少一个引脚,所述引脚设置在所述基岛外围,所述芯片的至少一个输入输出接口通过引线连接到所述引脚上。
优选地,所述芯片为表面贴装元件,所述芯片的输入输出接口设置在所述芯片的顶面,所述引线焊接在所述输入输出接口上。
优选地,所述芯片为直插式集成电路,所述基岛上设有与该芯片的输入输出接口焊接的焊脚,所述引线由该焊脚引出。
优选地,所述基岛的面积大于所述芯片的面积,使得芯片承载在该基岛上时,基岛表面有部分露出于芯片之外,该部分表面构成所述第一表面的一部分,并受所述塑封层的覆盖。
优选地,所述芯片和所述基岛之间还设有粘结层。
本实用新型通过让塑封材料直接包封在铜质框架体的表面,因为铜质框架体表面本身具有一定的粗糙度,可以使得该塑封材料很好的附着到该铜质框架体上,解决了现有技术中,塑封材料包封在镀银层表面容易发生分层的问题。有利于提高元器件的散热能力和抗热应力变化能力,产品的密封性、功能参数以及可靠性都得到了很好的保证。同时也简化了器件封装工序,节省了成本。
附图说明
图1是一种现有的芯片封装结构的剖面示意图。
图2是本实用新型第一实施方式下的芯片封装结构的剖面示意图。
图3是本实用新型芯片封装结构的俯视图。
图4本实用新型第二实施方式下的芯片封装结构的剖面示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本实用新型进行详细描述,但这些实施方式并不限制本实用新型,本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本实用新型的保护范围内。
如背景技术中所述的,现有的芯片封装结构中,采用的引线框架一般是铜为主体,然后在铜上面镀银,镀银的框架表面比较光滑,和塑封料结合不会那么牢固,尤其是塑封体大于6mm以上,还有可能因为机械应力的原因导致应力分层,本实用新型的目的在于克服上述不足,提供一种可以改善半导体塑料封装体内元器件分层的封装结构。
下面将通过具体实施方式对本实用新型的技术方案做详细描述。
实施方式一
请参见图2和图3,图2是本实用新型第一实施方式下的芯片封装结构的剖面示意图,图3是该芯片封装结构的俯视图。如图所示,该芯片封装结构100包括铜质框架体10,承载在所述铜质框架体10上的至少一个芯片20,将所述芯片20包封在所述铜质框架体10上的塑封层30,其中所述铜质框架10具有粗糙的第一表面14,所述塑封层30的至少部分覆盖在所述铜质框架体10的第一表面14上。
铜质框架体10包括至少一个基岛11,所述至少一个芯片20承载在基岛11上。基岛11通常位于铜质框架体11的中间位置,并且当芯片20固定在基岛11上之后,使用塑封材料对芯片20进行包封,同时会将基岛11覆盖。形成如图3中阴影的效果。图2中的芯片为表面贴装元件,采用表面贴装工艺将该芯片20固定在基岛11上。此时该芯片20和基岛11之间会使用高分子粘合剂作为粘结层21进行固定。
所述铜质框架体11还包括至少一个引脚12,所述引脚12设置在所述基岛11外围,所述芯片20的至少一个输入输出接口通过引线13连接到所述引脚12上。在图3中,基岛11的上下两侧都设有多个引脚12,引脚12的数量视芯片的输入输出端口数量而定。由于在本实施方式中,芯片20的输入输出端口位于该芯片的顶部,所以引线13直接焊接在这些输入输出端口和引脚12之间。
请再见图2,图2中,铜质框架体10的第一表面14是指具有器件绑定的一面,实际上包括了基岛11、引脚12以及其它部位的面积。由于芯片20通常小于该基岛11,因此当芯片固定在基岛11上之后,基岛11还会有一部分面积露出来,这部分露出来的面积也会和塑封层30进行接触,构成了第一表面的一部分,并受塑封层30的覆盖。
在实际生产中,由于铜质框架体10在生产过程中,本身的表面粗糙度较大,因此可以直接在铜质框架体10的粗糙面上填充塑封材料。也可以对铜质框架体10的第一表面做进一步的粗糙化处理,使得该第一表面14更加粗糙。所示粗糙化处理包括但不限于刻蚀、研磨、冲压等工艺。
第二实施方式
请参见图4,图4是本实用新型第二实施方式下的芯片封装结构的剖面示意图。如图所示,在该实施方式中,芯片20’采用直插式集成电路,所述基岛11’上设有与该芯片的输入输出接口焊接的焊脚。此时引线由基岛上的焊脚引出,连接到引脚12’上。其它结构与实施方式一相同,在此不再赘述。
综上所述,由于本实用新型在与塑封层结合的金属引线框的表面直接使用铜金属,不做镀银等处理,这样的金属引线框的表面制作粗糙。粗糙的金属引线框与环氧树脂间的接触面积和结合力都有大的提升,可以降低二者在X与Y平面方向上因不同物质膨胀/收缩所产生的剪应力;同时,粗糙的表面增加了与环氧树脂间的结合面积,减少因拉力等因素造成的金属引线框与环氧树脂之间的滑动力。因此,以上方案的结合使用可以使金属引线框与环氧树脂之间相互咬得更紧,从而起到防止或减少分层的作用。
尽管为示例目的,已经公开了本实用新型的优选实施方式,但是本领域的普通技术人员将意识到,在不脱离由所附的权利要求书公开的本实用新型的范围和精神的情况下,各种改进、增加以及取代是可能的。

Claims (7)

1.一种芯片封装结构,其特征在于:包括铜质框架体,承载在所述铜质框架体上的至少一个芯片,将所述芯片包封在所述铜质框架体上的塑封层,其中所述铜质框架具有粗糙的第一表面,所述塑封层的至少部分覆盖在所述铜质框架体的第一表面上。
2.如权利要求1所述的芯片封装结构,其特征在于:所述铜质框架体包括至少一个基岛,所述至少一个芯片承载在所述至少一个基岛上。
3.如权利要求2所述的芯片封装结构,其特征在于:所述铜质框架体还包括至少一个引脚,所述引脚设置在所述基岛外围,所述芯片的至少一个输入输出接口通过引线连接到所述引脚上。
4.如权利要求3所述的芯片封装结构,其特征在于:所述芯片为表面贴装元件,所述芯片的输入输出接口设置在所述芯片的顶面,所述引线焊接在所述输入输出接口上。
5.如权利要求3所述的芯片封装结构,其特征在于:所述芯片为直插式集成电路,所述基岛上设有与该芯片的输入输出接口焊接的焊脚,所述引线由该焊脚引出。
6.如权利要求2所述的芯片封装结构,其特征在于:所述基岛的面积大于所述芯片的面积,使得芯片承载在该基岛上时,基岛表面有部分露出于芯片之外,该部分表面构成所述第一表面的一部分,并受所述塑封层的覆盖。
7.如权利要求2所述的芯片封装结构,其特征在于:所述芯片和所述基岛之间还设有粘结层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116666344A (zh) * 2023-07-26 2023-08-29 深圳市锐骏半导体股份有限公司 一种框架结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116666344A (zh) * 2023-07-26 2023-08-29 深圳市锐骏半导体股份有限公司 一种框架结构

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