CN211150551U - 厚薄铜片引线框架结构 - Google Patents

厚薄铜片引线框架结构 Download PDF

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CN211150551U
CN211150551U CN202020131060.8U CN202020131060U CN211150551U CN 211150551 U CN211150551 U CN 211150551U CN 202020131060 U CN202020131060 U CN 202020131060U CN 211150551 U CN211150551 U CN 211150551U
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copper
chip
bottom frame
boss
solder
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陶涛
王连慧
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Changzhou Galaxy Century Microelectronics Co ltd
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Changzhou Galaxy Century Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8534—Bonding interfaces of the connector
    • H01L2224/85345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本实用新型公开了一种厚薄铜片引线框架结构，它包括塑封料、第一底部框架、第二底部框架、芯片和铜跳线，所述第一底部框架和第二底部框架固定在塑封料的底部，所述芯片的底部通过焊料固定在第一底部框架的顶部，所述铜跳线的厚端底部设置有凸台，所述凸台的底部通过焊料固定在芯片的顶部，所述凸台与芯片的连接部位呈圆弧形，所述铜跳线的薄端通过焊料固定在第二底部框架的顶部。本实用新型提供一种厚薄铜片引线框架结构，采用厚薄铜跳线，同时设计凸台为圆弧结构，采用顶部、底部双面露铜设计，提高了芯片的性能，散热效果更好。

Description

厚薄铜片引线框架结构
技术领域
本实用新型涉及一种厚薄铜片引线框架结构，属于二极管生产领域。
背景技术
目前，半导体引线框架均为同一厚度，此方式优点为加工方便，价格低廉，缺点难以满足更高的二极管器件要求。为了更高的可靠性能，在产品工作时能最大的散发其产生的热量，为了解决此难题，很多厂家采用底板露铜设计，单一的底部露铜设计已经无法满足散热要求，必须另寻方法。同时如何才能将芯片能力发挥最大化，也是一个难题。
发明内容
本实用新型所要解决的技术问题是，克服现有技术的不足，提供一种厚薄铜片引线框架结构，采用厚薄铜跳线，同时设计凸台为圆弧结构，采用顶部、底部双面露铜设计，提高了芯片的性能，散热效果更好。
为了解决上述技术问题，本实用新型的技术方案是：
一种厚薄铜片引线框架结构，它包括塑封料、第一底部框架、第二底部框架、芯片和铜跳线，所述第一底部框架和第二底部框架固定在塑封料的底部，所述芯片的底部通过焊料固定在第一底部框架的顶部，所述铜跳线的厚端底部设置有凸台，所述凸台的底部通过焊料固定在芯片的顶部，所述凸台与芯片的连接部位呈圆弧形，所述铜跳线的薄端通过焊料固定在第二底部框架的顶部。
进一步，所述铜跳线的厚端与薄端的过渡面底部设置有倒钩式挡锡槽。
进一步，并所述采用顶部、底部双面露铜设计。
采用了上述技术方案，本实用新型具有以下的有益效果：
1、铜跳线结构采用厚薄铜片，与芯片接触采用圆弧设计，能最大发挥芯片性能，并有效解决芯片连极等一系列问题。
2、若直接将跳线的高度直接设计成顶部露铜结构，由于焊接高度不受控，产品在塑封时，极易被塑封模具合模时压破芯片，造成质量隐患。
3、铜跳线上开有卡口挡锡槽，防止焊料过多时产生回流。
附图说明
图1为本实用新型的厚薄铜片引线框架结构的结构示意图。
具体实施方式
为了使本实用新型的内容更容易被清楚地理解，下面根据具体实施例并结合附图，对本实用新型作进一步详细的说明。
如图1所示，一种厚薄铜片引线框架结构，它包括塑封料1、第一底部框架2、第二底部框架3、芯片4和铜跳线5。第一底部框架2和第二底部框架3固定在塑封料1的底部，第一底部框架2和第二底部框架3用于放置铜跳线5，减少成型切断的应力。
如图1所示，芯片4的底部通过焊料6固定在第一底部框架2的顶部，铜跳线5的厚端底部设置有凸台7，凸台7的底部通过焊料6固定在芯片4的顶部，凸台7与芯片4的连接部位呈圆弧形71，圆弧形71可以爬锡，防止这中间间隙较小后，产生连极的隐患。铜跳线5的薄端通过焊料6固定在第二底部框架3的顶部。能最大发挥芯片性能，并有效解决芯片连极等问题。铜跳线5顶部采用平板结构，通过后期加工，可将跳线背部露出胶体，在产品底部散热的同时，可以新增30％以上顶部散热面积，大大提升产品可靠性能。铜跳线5前端较厚，也有利于对于散热。
如图1所示，为了防止焊料6过多时，产生虹吸作用回流，铜跳线5的厚端与薄端的过渡面底部设置有倒钩式挡锡槽8。
如图1所示，塑封料1的顶部和底部均设置有露铜面9，可以更好地散热，减少工作时的热量，降低芯片失效的概率。
以上所述的具体实施例，对本实用新型解决的技术问题、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本实用新型的具体实施例而已，并不用于限制本实用新型，凡在本实用新型的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本实用新型的保护范围之内。

Claims (3)

1.一种厚薄铜片引线框架结构，其特征在于：它包括塑封料(1)、第一底部框架(2)、第二底部框架(3)、芯片(4)和铜跳线(5)，所述第一底部框架(2)和第二底部框架(3)固定在塑封料(1)的底部，所述芯片(4)的底部通过焊料(6)固定在第一底部框架(2)的顶部，所述铜跳线(5)的厚端底部设置有凸台(7)，所述凸台(7)的底部通过焊料(6)固定在芯片(4)的顶部，所述凸台(7)与芯片(4)的连接部位呈圆弧形(71)，所述铜跳线(5)的薄端通过焊料(6)固定在第二底部框架(3)的顶部。
2.根据权利要求1所述的厚薄铜片引线框架结构，其特征在于：所述铜跳线(5)的厚端与薄端的过渡面底部设置有倒钩式挡锡槽(8)。
3.根据权利要求1所述的厚薄铜片引线框架结构，其特征在于：所述塑封料(1)的顶部和底部均设置有露铜面(9)。
CN202020131060.8U 2020-01-20 2020-01-20 厚薄铜片引线框架结构 Active CN211150551U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115440686A (zh) * 2022-11-09 2022-12-06 华羿微电子股份有限公司 一种铜片及粘片结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115440686A (zh) * 2022-11-09 2022-12-06 华羿微电子股份有限公司 一种铜片及粘片结构
CN115440686B (zh) * 2022-11-09 2023-03-10 华羿微电子股份有限公司 一种铜片及粘片结构

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