CN211124030U - PCI-Express signal acquisition handles carrier plate based on Kintex UltraScale - Google Patents

PCI-Express signal acquisition handles carrier plate based on Kintex UltraScale Download PDF

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CN211124030U
CN211124030U CN201921624342.5U CN201921624342U CN211124030U CN 211124030 U CN211124030 U CN 211124030U CN 201921624342 U CN201921624342 U CN 201921624342U CN 211124030 U CN211124030 U CN 211124030U
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pci
fpga chip
express
module
signal acquisition
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盖武
盖昱升
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Chengdu Ruinaibo Technology Co ltd
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Chengdu Ruinaibo Technology Co ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The utility model discloses a PCI-Express signal acquisition handles support plate based on Kitex ultra Scale, a serial communication port, including first FPGA chip and the second FPGA chip of connection, the second FPGA chip is Kitex-7 framework, be provided with multichannel PCI-Express interface, through multichannel PCI-Express interface connection PCI-Express support plate, still be connected with DDR memory module, SPI Flash module, differential clock module, first FPGA chip is Kitex ultra Scale framework, be provided with two high-speed expansion joint interfaces, still be connected with DDR memory module, SPI Flash module, differential clock module, TT L control module the utility model discloses in, adopt 2 FPGA chip framework, one of them is connected PCI-Express and is carried the card and accomplish the high-speed collection of multichannel, another accomplishes the function that high performance can handle, 2 FPGA chips also can high performance handle in the high-efficient collection, limitation 1 FPGA chip framework is broken, and the TT L control module that adopts makes PCI-Express acquisition handle the card and accomplish low power consumption when high performance.

Description

PCI-Express signal acquisition handles carrier plate based on Kintex UltraScale
Technical Field
The utility model belongs to the technical field of data acquisition transmission, concretely relates to PCI-Express signal acquisition handles support plate based on Kintex UltraScale.
Background
The high-speed data acquisition card based on PCI-Express has obvious advantages compared with the traditional computer bus interfaces such as PCI and USB2.0 interfaces, and the like, and the high data throughput rate and throughput bandwidth are the most outstanding ones, so that users with requirements on storage and processing of a large amount of data have new choices. The PCI-Express acquisition processing card is realized by FPGA (field programmable gate array), the existing PCI-Express acquisition processing card is of 1 FPGA chip architecture, and multi-channel acquisition is realized by adopting different interface circuits such as 2 channels, 4 channels, 8 channels and the like. However, the acquisition processing capability of 1 FPGA chip architecture is limited, and the performance of the PCI-Express acquisition processing card is difficult to be greatly improved through technical improvement on the basis of 1 FPGA chip architecture.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a: the PCI-Express signal acquisition and processing carrier plate based on the KintexUltraScale solves the problems that the acquisition and carding capacity of the PCI-Express acquisition and processing card based on 1 FPGA chip architecture is limited at present and the performance of the PCI-Express acquisition and processing card is difficult to greatly improve.
The utility model adopts the technical scheme as follows:
a PCI-Express signal acquisition and processing carrier plate based on KintexUltraScale comprises a first FPGA chip and a second FPGA chip which are connected, wherein the second FPGA chip is a Kintex-7 framework and is provided with a plurality of PCI-Express interfaces, the PCI-Express carrier plate is connected through the plurality of PCI-Express interfaces, and the PCI-Express signal acquisition and processing carrier plate is further connected with a DDR memory module, an SPIFlash module and a differential clock module, the first FPGA chip is a KintexUltraScale framework and is provided with two high-speed expansion card interfaces, and the DDR memory module, the SPIFlash module, the differential clock module and a TT L control module are further connected.
Furthermore, the first FPGA chip and the second FPGA chip are respectively connected with a status indicator lamp module.
Furthermore, the first FPGA chip and the second FPGA chip are respectively provided with a debugging JTAG interface.
Further, the first FPGA chip adopts an XCKU040-2FFVA1156I chip, the second FPGA chip adopts an XC7K325T-2FFG900I chip, and a data transmission mode of a GTXx8 or L VDS72 pair is adopted between the first FPGA chip and the second FPGA chip.
Furthermore, the PCI-Express carrier plate is provided with a battery module, the processing card is powered by the battery module connected with the PCI-Express carrier plate, and the battery module adopts IP L1-103-01-L-D-RE 1-K.
Further, the DDR memory modules of the first FPGA chip and the second FPGA chip are MT41J256M16 HA-125-IT.
Further, the first FPGA chip and the second FPGA chip are subjected to surface mount heat dissipation.
Furthermore, the PCI-Express interface of the second FPGA chip is connected with the PCI-Express carrier plate through ｃA high-speed connector QTH-040-01-L-D-DP-A.
To sum up, owing to adopted above-mentioned technical scheme, the beneficial effects of the utility model are that:
1. the utility model discloses in, adopt 2 FPGA chip frameworks, one of them is connected PCI-Express and is carried the card and accomplish the high-speed collection of multichannel, and another accomplishes the function that the high performance was handled, and 2 FPGA chips also can the high performance be handled when high-efficient the collection, breaks 1 FPGA chip framework's limitation, and the TT L control module who just adopts makes PCI-Express gather the card and accomplish the low-power consumption in the high performance.
2. The utility model discloses in, the battery module power supply of processing the card through being connected with PCI-Express carrier plate, battery module adopts IP L1-103-01-L-D-RE 1-K, makes the power supply safer.
3. The utility model discloses in, first FPGA chip and second FPGA chip still are connected with status indicator lamp module respectively, can include power indicator, the system indicator, and user-defined pilot lamp conveniently instructs collection card operating condition.
4. The utility model discloses in, first FPGA chip and second FPGA chip adopt the table to paste the heat dissipation, and low-power consumption and high performance are guaranteed to the heat dissipation function of reinforcing integrated circuit board.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a diagram of the architecture of a Kinex UltraScale-based PCI-Express signal acquisition and processing carrier plate of the present invention;
fig. 2, fig. 3 and fig. 4 are schematic circuit diagrams of XC7K325T-2FFG900I chip of the present invention;
fig. 5, 6, 7 and 8 are schematic circuit diagrams of the XCKU040-2FFVA1156I chip according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention, i.e., the described embodiments are merely some, but not all, embodiments of the invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiment of the present invention, all other embodiments obtained by the person skilled in the art without creative work belong to the protection scope of the present invention.
It is noted that relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The features and properties of the present invention are described in further detail below with reference to examples.
Example 1
The utility model discloses the PCI-Express signal acquisition handles support plate based on Kintex UltraScale that preferred embodiment provided, as shown in FIG. 1, including first FPGA chip and the second FPGA chip of connection, first FPGA chip is Kintex UltraScale framework, and this embodiment adopts XCKU040-2FFVA1156I chip, the second FPGA chip is Kintex XC-7 framework, and this embodiment adopts 7K325T-2FFG900I chip, adopts GTX x8 or L VDS72 right data transmission mode between first FPGA chip and the second FPGA chip.
The configuration mode of the first FPGA chip is as follows:
KintexUltraScale configuration mode
Configuration modes M[2:0] Bus bit width CCLK
Master serial 000 x1 Output
Main SPI 001 x1,x2,x4,x8 Output
Master BPI
010 x8,x16 Output
Master SelectMAP 100 x8,x16 Output
JTAG 101 x1 N/A
Heavy SelectMAP 110 x8,x16,x32 Input
Multiple serial connection 111 x1 Input
Master BPI mode x16 is used. Other undefined patterns are considered invalid.
The configuration mode of the second FPGA chip is as follows:
kintex-7 configuration mode
Configuration modes M[2:0] Bus bit width CCLK
Master serial 000 x1 Output
Main SPI 001 x1,x2,x4,x8 Output
Master BPI
010 x8,x16 Output
Master SelectMAP 100 x8,x16 Output
JTAG 101 x1 N/A
Heavy SelectMAP 110 x8,x16,x32 Input
Multiple serial connection 111 x1 Input
Master BPI mode x16 is used. Other undefined patterns are considered invalid.
The circuit diagram of the XC7K325T-2FFG900I chip is shown in FIGS. 2-4, and the voltage of Kintex-7 FPGABank is:
bank0 is configured with HR Bank voltage of 2.5V;
bank12, wherein Bank13 is HR Bank voltage of 3.3V;
bank14, wherein Bank15 is HR Bank voltage of 2.5V;
bank16, Bank17 and Bank18 are HR Bank voltage of 2.5V;
bank32 is HPBank voltage 1.8V;
bank33, and Bank34 shows that the HPBank voltage is 1.5V;
voltage not specified refer to Kintex-7 DS182 DC andAC data Manual.
The circuit diagram of the XCKU040-2FFVA1156I chip is shown in FIGS. 5-8, and the voltage of KintexUltraScale FPGABank:
bank0 is configured with HR Bank voltage of 3.3V;
bank44, and Bank45 shows that the HPBank voltage is 1.5V;
bank46, Bank47 and Bank48 are HPBank voltage VADJ adjustable;
bank64, HR Bank voltage of 2.5V in Bank 65;
bank66, Bank67 and Bank68 are HPBank voltage VADJ adjustable;
voltages not specifically described are referenced to the DS892 DC andAC data manual of kintex ultrascale.
The second FPGA chip Kintex-7 is provided with a plurality of paths of PCI-Express interfaces, is connected with a PCI-Express carrier plate through the plurality of paths of PCI-Express interfaces, and is further connected with a DDR memory module, an SPI Flash module and a differential clock module, the first FPGA chip KintexUltraScale is provided with two high-speed expansion card interfaces FMC-HPC, and is further connected with a DDR memory module, an SPIFlash module, a differential clock module and a TT L control module.
In this embodiment, SamTecASP-134486-01 is used as the two high-speed expansion card interfaces FMC-HPC.
In this embodiment, the SPI Flash module uses PC28F00AP30 TFA.
In the embodiment, the TT L control module is connected with a first FPGA chip KintexUltraScale by adopting a connector with a J30J 51 pin, each group provides GND, 3.3V and more than 40 signal interfaces, and the driving capability is more than 120 mA.
In this embodiment, the differential clock module connected to the first FPGA chip includes an SYS clock module, a DDR clock module, and a GTX clock module, and the differential clock module connected to the second FPGA chip includes an SYS clock module, a DDR clock module, a GTX clock module, and a DIFF programmable clock module.
In this embodiment, the DDR memory modules of the first FPGA chip and the second FPGA chip both adopt MT41J256M16 HA-125-IT. The memory of the first FPGA chip KintexUltraScale is as follows: MT41J256M16HA-125-IT, x4, total capacity of 2GB, bit width of 64bit, and maximum support of 1600 MT/s; the memory of the second FPGA chip Kintex-7 is as follows: MT41J256M16HA-125-IT, x2, total capacity of 1GB, bit width of 32 bits, and maximum support of 1600 MT/s.
Furthermore, the PCI-Express interface of the second FPGA chip adopts ｃA PCI-Express GEN2x8 interface and is connected with the PCI-Express carrier plate through ｃA high-speed connector QTH-040-01-L-D-DP-A.
Furthermore, the processing card supplies power to 12V/4A through a battery module connected with the PCI-Express carrier plate, and the battery module adopts IP L1-103-01-L-D-RE 1-K to ensure that the power supply is safer.
Furthermore, the first FPGA chip and the second FPGA chip are respectively provided with a standard 14Pin 2.0mm debugging JTAG interface.
The utility model discloses in, adopt 2 FPGA chip frameworks, one of them is connected PCI-Express and is carried the card and accomplish the high-speed collection of multichannel, and another accomplishes the function that the high performance was handled, and 2 FPGA chips also can the high performance be handled when high-efficient the collection, breaks 1 FPGA chip framework's limitation, and the TT L control module who just adopts makes PCI-Express gather the card and accomplish the low-power consumption in the high performance.
Example 2
The utility model discloses preferred embodiment is on embodiment one's basis, first FPGA chip and second FPGA chip still are connected with status indicator lamp module respectively. The system can comprise a power supply indicator light, a system indicator light and a user-defined indicator light, and the working state of the acquisition card can be conveniently indicated.
Further, the first FPGA chip and the second FPGA chip are subjected to surface mount heat dissipation. The heat dissipation function of the board card is enhanced, and low power consumption and high performance are guaranteed.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims (8)

1. A PCI-Express signal acquisition and processing carrier plate based on Kinex UltraScale is characterized by comprising a first FPGA chip and a second FPGA chip which are connected, wherein the second FPGA chip is of a Kinex-7 framework and provided with a plurality of PCI-Express interfaces, the PCI-Express carrier plate is connected through the plurality of PCI-Express interfaces, and the PCI-Express signal acquisition and processing carrier plate is further connected with a DDR memory module, an SPI Flash module and a differential clock module, the first FPGA chip is of the Kinex UltraScale framework and provided with two high-speed expansion card interfaces and is further connected with the DDR memory module, the SPI Flash module, the differential clock module and a TT L control module.
2. The Kinex UltraScale-based PCI-Express signal acquisition and processing carrier board of claim 1, wherein: the first FPGA chip and the second FPGA chip are further connected with a status indicator lamp module respectively.
3. The Kinex UltraScale-based PCI-Express signal acquisition and processing carrier board of claim 1, wherein: and the first FPGA chip and the second FPGA chip are also respectively provided with a debugging JTAG interface.
4. The Kintex UltraScale-based PCI-Express signal acquisition and processing carrier board as claimed in claim 1, wherein said first FPGA chip is XCKU040-2FFVA1156I chip, said second FPGA chip is XC7K325T-2FFG900I chip, and data transmission mode of GTX x8 or L VDS72 pair is adopted between the first FPGA chip and the second FPGA chip.
5. The Kinex UltraScale-based PCI-Express signal acquisition and processing carrier board as claimed in claim 1, wherein said PCI-Express carrier board is provided with a battery module, the processing card is powered by the battery module connected with the PCI-Express carrier board, and the battery module adopts IP L1-103-01-L-D-RE 1-K.
6. The Kinex UltraScale-based PCI-Express signal acquisition and processing carrier board of claim 1, wherein: the DDR memory modules of the first FPGA chip and the second FPGA chip are MT41J256M16 HA-125-IT.
7. The Kinex UltraScale-based PCI-Express signal acquisition and processing carrier board of claim 1, wherein: and the first FPGA chip and the second FPGA chip are subjected to surface mount heat dissipation.
8. The Kintex UltraScale-based PCI-Express signal acquisition and processing carrier board as claimed in claim 1, wherein the PCI-Express interface of said second FPGA chip is connected to the PCI-Express carrier board through high-speed connector QTH-040-01-L-D-DP-A.
CN201921624342.5U 2019-09-26 2019-09-26 PCI-Express signal acquisition handles carrier plate based on Kintex UltraScale Active CN211124030U (en)

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CN201921624342.5U CN211124030U (en) 2019-09-26 2019-09-26 PCI-Express signal acquisition handles carrier plate based on Kintex UltraScale

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Application Number Priority Date Filing Date Title
CN201921624342.5U CN211124030U (en) 2019-09-26 2019-09-26 PCI-Express signal acquisition handles carrier plate based on Kintex UltraScale

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