CN210351132U - CTX type bidirectional transmitting channel assembly - Google Patents
CTX type bidirectional transmitting channel assembly Download PDFInfo
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- CN210351132U CN210351132U CN201921623482.0U CN201921623482U CN210351132U CN 210351132 U CN210351132 U CN 210351132U CN 201921623482 U CN201921623482 U CN 201921623482U CN 210351132 U CN210351132 U CN 210351132U
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 34
- 238000004891 communication Methods 0.000 claims abstract description 22
- 230000005540 biological transmission Effects 0.000 claims abstract description 14
- 238000012545 processing Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 15
- 238000005070 sampling Methods 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 3
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- 230000000712 assembly Effects 0.000 description 1
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Abstract
The utility model discloses a two-way transmission channel subassembly of CTX type, its characterized in that: the bidirectional digital processing chip is integrated with a PL side and a PS side, the PL side is connected with an integrated bidirectional receiving and transmitting chip, a memory module, a gigabit Ethernet module, a system clock module, a JTAG interface, a communication interface module and a board-level management chip, the bidirectional receiving and transmitting chip is externally connected with a radio frequency board through an IO interface, and the PS side is connected with the memory module, the gigabit Ethernet module, a QSPI Flash module, an SD card module, an EMMC storage module and a communication interface module. The utility model discloses in, the frame of adoption realizes the two-way receiving and dispatching of the comparatively simple transmission passageway of structure, and solitary board level management chip carries out the board level management, guarantees real-time and high-efficient transmission. The whole circuit is designed by matching with other modules such as a memory, a clock, a communication interface and the like, so that the complexity of the whole circuit is reduced, the circuit is clear and simple, and the whole power consumption is reduced.
Description
Technical Field
The utility model belongs to the technical field of the transmission channel subassembly, concretely relates to two-way transmission channel subassembly of CTX type.
Background
The transmit channel assembly is an important component of the front end of many communication systems and requires real-time and efficient transmission of signals. Most of the existing transmitting channel assemblies adopt a general processing arithmetic unit, and an external connection transmitting module, a receiving module and the like are designed. The transmitting module, the receiving module and the like need to be designed with a plurality of external parts, the circuit is complex, the number of used devices is large, and the power consumption is not convenient to reduce. In addition, the design can only perform one-way transmission of data signals, the application range is limited, and the realization of two-way transmission on the basis of the architecture can further increase the circuit complexity and the power consumption. There is a need for an architecture that meets the requirements of bi-directional transmission and reduced power consumption for simplified circuits.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a: the CTX type bidirectional transmitting channel assembly aims to solve the problems that a plurality of external parts need to be designed, the circuit is complex, a plurality of used devices are needed, the power consumption is not convenient to reduce, data signals can be transmitted in one direction generally, and the application range is limited.
The utility model adopts the technical scheme as follows:
a CTX type bidirectional transmitting channel assembly comprises a bidirectional digital processing chip based on a ZYNQ platform structure, wherein the bidirectional digital processing chip is integrated with a PL side and a PS side, the PL side is connected with an integrated bidirectional transmitting and receiving chip, a memory module, a gigabit Ethernet module, a system clock module, a JTAG interface, a communication interface module and a board-level management chip, the bidirectional transmitting and receiving chip is externally connected with a radio frequency board through an IO interface, and the PS side is connected with a memory module, a gigabit Ethernet module, a QSPI Flash module, an SD card module, an EMMC storage module and a communication interface module.
Further, the communication interface module connected to the PL side includes an M-LVDS interface, a SATA interface, an SFP + interface, and an RS communication interface.
Further, the communication interface module connected to the PS side includes a USB interface, a UART interface, an RS interface, and a CAN interface.
Further, the memory modules connected to the PL side and the PS side adopt DDR3MT41K256M16 HA-125E.
Further, the integrated bidirectional transceiver chip connected on the PL side adopts AD9361, and the working mode is bidirectional RF2X 2.
Furthermore, the sampling clock input mode of the AD9361 is any one of the following two modes:
the first method is as follows: the method comprises the steps that external single-end input is conducted, an SMP-JHD4-F interface is adopted, and the external single-end input is conducted to an AD9361 chip;
the second method comprises the following steps: the 40MHz sampling clock is provided by an on-board crystal oscillator.
Furthermore, the bidirectional transceiver chip is externally connected with the radio frequency board through a level conversion isolation connector of the IO interface.
Further, the configuration mode of the emission channel assembly is any one of the following three types:
through PS terminal configuration: starting from QSPI Flash;
through PS terminal configuration: starting from the SD card;
configuration through the PL side: from JTAG.
To sum up, owing to adopted above-mentioned technical scheme, the beneficial effects of the utility model are that:
1. the utility model discloses in, the frame that adopts the external radio frequency module of two-way digital processing chip cooperation integrated two-way transceiver chip based on ZYNQ platform structure realizes the two-way transceiver of the comparatively simple transmission channel of structure, carries out the board level management through solitary board level management chip, guarantees real-time and high-efficient transmission. The complexity of the whole circuit is reduced by matching with the design of other modules such as a memory, a clock, a communication interface and the like, the complicated design of a transmitting module, a receiving module and a matching circuit is not needed, the circuit is clear and simple, and the whole power consumption is reduced.
2. The utility model discloses in, two-way transceiver chip AD 9361's sampling clock input mode can adopt outside or board to carry and provide, and the selectivity is more, and application scope is bigger.
3. The utility model discloses in, the configuration mode of launching the passageway subassembly sets up to three kinds, and the selectivity is more, and application scope is bigger.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a block diagram of the firing channel assembly of the present invention;
fig. 2 is a schematic structural diagram of a launch channel assembly in embodiment 1 of the present invention;
fig. 3 is an interface circuit diagram of the external radio frequency board of the bidirectional transceiver chip in embodiment 1 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention, i.e., the described embodiments are merely some, but not all, embodiments of the invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiment of the present invention, all other embodiments obtained by the person skilled in the art without creative work belong to the protection scope of the present invention.
It is noted that relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The features and properties of the present invention are described in further detail below with reference to examples.
Example 1
The utility model discloses preferred embodiment provides a two-way transmission channel subassembly of CTX type, as shown in FIG. 2, include the two-way digital processing chip based on ZYNQ platform structure, two-way digital processing chip integration has PL side and PS side, and the PL side is connected with integrated two-way transceiver chip, memory module, gigabit Ethernet module, system clock module, JTAG interface, communication interface module and board level management chip, two-way transceiver chip passes through the external radio frequency board of IO interface, and the PS side is connected with memory module, gigabit Ethernet module, QSPI Flash module, SD card module, EMMC storage module and communication interface module.
In this embodiment, the Zynq platform structure-based bidirectional digital processing chip adopts Zynq-7000XC7Z030-2FFG676, or other Zynq-7000 series chips. The QSPI Flash module can adopt MT25QL128ABA8ESF-0 SIT. The board level management chip may employ STM32F103, with STM32F103 communicating with the PL using Qspi. The JTAG interface adopts an IDC-142.54mm socket and is connected to a JTAG pin at a PL end of a Zynq-7000 chip. The SD card module adopts a TF SD card with the capacity of maximally supporting 32 GB. The system clock block provides a 200MHz differential clock input to the PL and an 33.333MHz single ended clock input to the PS. The gigabit ethernet module employs 88E 1116.
Further, in this embodiment, the communication interface module connected to the PL side includes an M-LVDS interface, a SATA2.0/3.0 interface, an SFP + interface, an RS232 communication interface, and an RS422/485 communication interface.
Further, in this embodiment, the communication interface module connected to the PS side includes a USB2.0 interface, a USB port, an RS232 interface, and a CAN interface.
Further, in this embodiment, the memory modules connected to the PL side and the PS side both use DDR3_ MT41K256M16 HA-125E. The total capacity is more than 1GB, the bit width is 32bit, the speed is more than 534MHz, and the highest 1333MHz of a-2 device is supported; the DDR3 clock comes from the system clock module.
Further, in this embodiment, the integrated bidirectional transceiver chip connected to the PL side employs AD9361, and the operation mode is bidirectional RF2X 2. The chip integrates a 12-bit DAC and ADC RF2x2 transceiver, the frequency band supports 70 MHz-6.0 GHz, TDD and FDD are supported, the dual-channel receiver, 6 paths of differential or 12 paths of single-end input, CBS _ BGA package, and AD9361 needs to provide a 40MHz clock.
Furthermore, the sampling clock input mode of the AD9361 is any one of the following two modes:
the first method is as follows: the method comprises the steps that external single-end input is conducted, an SMP-JHD4-F interface is adopted, and the external single-end input is conducted to an AD9361 chip;
the second method comprises the following steps: the 40MHz sampling clock is provided by an on-board crystal oscillator.
Can be provided externally or on board, has more selectivity and wider application range.
Further, the bidirectional transceiver chip is externally connected with the radio frequency board through a level conversion isolation connector of the IO interface, and an interface circuit diagram is shown in fig. 3.
Further, the configuration mode of the emission channel assembly is any one of the following three types:
1) through PS terminal configuration: starting from QSPI Flash;
2) through PS terminal configuration: starting from the SD card;
3) configuration through the PL side: from JTAG.
The configuration mode of the transmitting channel assembly is set to be three, the selectivity is more, and the application range is wider.
The above configuration mode is switched by a dial switch, and the default selection is mode 2). The specific configuration selection is completed by 5 groups of jumpers, each group of jumpers respectively corresponds to MIO2-MIO6(PS terminal), and the 5 configuration mode selection MIO pins are shown in the following table:
in this embodiment, the voltage is set as:
the bidirectional digital processing chip ZYNQ-7000 is configured with BANK use 1.8;
PL-DDR3, PS-DDR3 use 1.5V (adjustable according to actual DDR3 chips).
The utility model discloses well subassembly is a integrated circuit board at last, and the integrated circuit board can adopt battery Seiko TS518SE FL35E 1.5.5V power supply, and electric current < 150nA when the subassembly integrated circuit board falls the power failure, and charging voltage comes from VCCAUX 1.8V voltage rail when the subassembly integrated circuit board is electrified.
The utility model discloses in, the frame that adopts the external radio frequency module of two-way digital processing chip cooperation integrated two-way transceiver chip based on ZYNQ platform structure realizes the two-way transceiver of the comparatively simple transmission channel of structure, carries out the board level management through solitary board level management chip, guarantees real-time and high-efficient transmission. The complexity of the whole circuit is reduced by matching with the design of other modules such as a memory, a clock, a communication interface and the like, the complicated design of a transmitting module, a receiving module and a matching circuit is not needed, the circuit is clear and simple, and the whole power consumption is reduced.
Example 2
The utility model discloses preferred embodiment is on embodiment one's basis, and two-way digital processing chip still is provided with extensible IO interface to the user expands and uses.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (8)
1. A CTX-type bidirectional transmission channel assembly, characterized in that: the bidirectional digital processing chip is integrated with a PL side and a PS side, the PL side is connected with an integrated bidirectional receiving and transmitting chip, a memory module, a gigabit Ethernet module, a system clock module, a JTAG interface, a communication interface module and a board-level management chip, the bidirectional receiving and transmitting chip is externally connected with a radio frequency board through an IO interface, and the PS side is connected with the memory module, the gigabit Ethernet module, a QSPI Flash module, an SD card module, an EMMC storage module and a communication interface module.
2. A CTX-type bidirectional transmit channel assembly as recited in claim 1, wherein: and the communication interface module connected with the PL side comprises an M-LVDS interface, a SATA interface, an SFP + interface and an RS communication interface.
3. A CTX-type bidirectional transmit channel assembly as recited in claim 1, wherein: the communication interface module connected with the PS side comprises a USB interface, a UART interface, an RS interface and a CAN interface.
4. A CTX-type bidirectional transmit channel assembly as recited in claim 1, wherein: the memory modules connected to the PL side and the PS side both adopt DDR3MT41K256M16 HA-125E.
5. A CTX-type bidirectional transmit channel assembly as recited in claim 1, wherein: the integrated bidirectional transceiver chip connected on the PL side adopts AD9361, and the working mode is bidirectional RF2X 2.
6. A CTX-type bidirectional transmit channel assembly as defined in claim 5, wherein: the sampling clock input mode of the AD9361 is any one of the following two modes:
the first method is as follows: the method comprises the steps that external single-end input is conducted, an SMP-JHD4-F interface is adopted, and the external single-end input is conducted to an AD9361 chip;
the second method comprises the following steps: the 40MHz sampling clock is provided by an on-board crystal oscillator.
7. A CTX-type bidirectional transmit channel assembly as recited in claim 1, wherein: the bidirectional receiving and transmitting chip is externally connected with a radio frequency board through a level conversion isolation connector of the IO interface.
8. A CTX-type bidirectional transmit channel assembly as recited in claim 1, wherein: the configuration mode of the emission channel assembly is any one of the following three types:
through PS terminal configuration: starting from QSPI Flash;
through PS terminal configuration: starting from the SD card;
configuration through the PL side: from JTAG.
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CN201921623482.0U CN210351132U (en) | 2019-09-26 | 2019-09-26 | CTX type bidirectional transmitting channel assembly |
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CN201921623482.0U CN210351132U (en) | 2019-09-26 | 2019-09-26 | CTX type bidirectional transmitting channel assembly |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN113254377A (en) * | 2021-05-07 | 2021-08-13 | 哈尔滨工业大学 | Task management computer for unmanned aerial vehicle |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN113254377A (en) * | 2021-05-07 | 2021-08-13 | 哈尔滨工业大学 | Task management computer for unmanned aerial vehicle |
CN113254377B (en) * | 2021-05-07 | 2023-09-08 | 哈尔滨工业大学 | Task management computer for unmanned aerial vehicle |
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Granted publication date: 20200417 |