CN210837744U - 一种sod系列大功率超低容值静电防护芯片封装结构 - Google Patents

一种sod系列大功率超低容值静电防护芯片封装结构 Download PDF

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CN210837744U
CN210837744U CN202020036098.7U CN202020036098U CN210837744U CN 210837744 U CN210837744 U CN 210837744U CN 202020036098 U CN202020036098 U CN 202020036098U CN 210837744 U CN210837744 U CN 210837744U
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electrostatic protection
protection chip
lead frame
electrically connected
metal lead
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王海青
许贵铮
刘伟强
刘杰丰
李章夏
陈泽龙
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Shenzhen Gaote Microelectronics Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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Abstract

一种SOD系列大功率超低容值静电防护芯片封装结构,本实用新型涉及电子芯片技术领域,金属引线框架设置在环氧树脂塑料塑封内,金属引线框架的引脚露设在环氧树脂塑料塑封的外侧,一号静电防护芯片和三号静电防护芯片电性连接固定在金属引线框架左侧的焊盘上表面的上下两侧,二号静电防护芯片电性连接固定在金属引线框架右侧的焊盘上;三号静电防护芯片利用金属导线与位于右侧的金属引线框架的上表面下侧电性连接;一号静电防护芯片与二号静电防护芯片之间利用金属导线电性连接。有效降低器件的体积及成本,符合电子产品轻薄小巧的需求,通信集成电路免受电磁/静电干扰或损坏,且能通过雷击测试认证。

Description

一种SOD系列大功率超低容值静电防护芯片封装结构
技术领域
本实用新型涉及电子芯片技术领域,具体涉及一种SOD系列大功率超低容值静电防护芯片封装结构。
背景技术
电子产品中通信集成电路的集成度越来高,电磁或静电干扰对通信集成电路越为敏感,因此静电防护芯片成为了通信集成电路常见的搭配器件;考虑到电子产品需要使用大功率静电防护二极管来通过雷击测试认证及通信集成电路的通信速率越来越高,要求其通信线路上的寄生电容必须小于1pF,甚至更低;再者,现行电子产品轻薄小巧,对其零部件的体积要求越小越好。因此,有必要提出一种新的大功率超低容值静电防护芯片封装结构。
发明内容
本实用新型的目的在于针对现有技术的缺陷和不足,提供一种设计合理的SOD系列大功率超低容值静电防护芯片封装结构,有效降低器件的体积及成本,符合电子产品轻薄小巧的需求,通信集成电路免受电磁/静电干扰或损坏,且能通过雷击测试认证。
为达到上述目的,本实用新型采用了下列技术方案:它包含金属引线框架、一号静电防护芯片、二号静电防护芯片、三号静电防护芯片、金属导线、环氧树脂塑料塑封;金属引线框架设置在环氧树脂塑料塑封内,金属引线框架的引脚露设在环氧树脂塑料塑封的外侧,一号静电防护芯片和三号静电防护芯片电性连接固定在金属引线框架左侧的焊盘上表面的上下两侧,二号静电防护芯片电性连接固定在金属引线框架右侧的焊盘上;三号静电防护芯片利用金属导线与位于右侧的金属引线框架的上表面下侧电性连接;一号静电防护芯片与二号静电防护芯片之间利用金属导线电性连接。
进一步地,所述的一号静电防护芯片的正面开窗处均设有金属球,连接一号静电防护芯片和二号静电防护芯片的金属导线的一端与上述金属球电性连接,该金属导线的另一端与二号静电防护芯片电性连接。
进一步地,所述的封装结构的尺寸为长2.6×宽1.3×高1.0mm。
采用上述结构后,本实用新型的有益效果是:本实用新型提供了一种SOD系列大功率超低容值静电防护芯片封装结构,有效降低器件的体积及成本,符合电子产品轻薄小巧的需求,通信集成电路免受电磁/静电干扰或损坏,且能通过雷击测试认证。
附图说明:
图1是本实用新型的结构示意图。
附图标记说明:
金属引线框架1、一号静电防护芯片2、二号静电防护芯片3、三号静电防护芯片4、金属球5、金属导线6、环氧树脂塑料塑封7。
具体实施方式:
下面将结合本实用新型实施例中的附图,对本实用新型实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本实用新型一部分实施例,而不是全部的实施例。基于本实用新型中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本实用新型保护的范围。
如图1所示,本具体实施方式采用如下技术方案:它包含金属引线框架1、一号静电防护芯片2、二号静电防护芯片3、三号静电防护芯片4、金属导线6、环氧树脂塑料塑封7;一号静电防护芯片2和三号静电防护芯片4两者的背面通过超声波高温共晶焊接固定在金属引线框架1左侧的焊盘的上下两侧,二号静电防护芯片3的背面通过超声波高温共晶焊接固定在金属引线框架1右侧的焊盘上;一号静电防护芯片2的正面开窗处植上金属球5(该金属球5采用合金线烧制而成,作为后续金属导线6的连接点,用于缓解焊接压力的作用,以免一号静电防护芯片2的表面受损);三号静电防护芯片4利用金属导线6与位于右侧的金属引线框架1的上表面下侧电性连接;一号静电防护芯片2上的金属球5与金属导线6的一端电性连接,该金属导线6的另一端与二号静电防护芯片4电性连接;上述金属导线6为合金线,材质较软,容易焊接且不会因焊接压力过大损坏二号静电防护芯片3和三号静电防护芯片4表层;上述金属引线框架1、一号静电防护芯片2、二号静电防护芯片3、三号静电防护芯片4、金属导线6均塑封于环氧树脂塑料塑封7内,其中,金属引线框架1的引脚露设在环氧树脂塑料塑封7的外侧(环氧树脂塑料塑封7提供一定的结构支撑及绝缘层,保护上述三个芯片不受机械损伤,免受温度、潮气、污染物等环境影响)。
本具体实施方式的工作原理:将一号静电防护芯片2、二号静电防护芯片3和三号静电防护芯片4合封到了一个微型封装外形里,整体尺寸为长2.6×宽1.3×高1.0mm,通过一号静电防护芯片2达成了大功率的需求,通过二号静电防护芯片3和三号静电防护芯片4降低了总的电容值至1pF以内,有效的降低了器件的体积及成本,符合电子产品轻薄小巧需求及其通信集成电路免受电磁/静电干扰或损坏,且能通过雷击测试认证。
采用上述结构后,本具体实施方式的有益效果是:本具体实施方式提供了一种SOD系列大功率超低容值静电防护芯片封装结构,有效降低器件的体积及成本,符合电子产品轻薄小巧的需求,通信集成电路免受电磁/静电干扰或损坏,且能通过雷击测试认证。
尽管参照前述实施例对本实用新型进行了详细的说明,对于本领域的技术人员来说,其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换,凡在本实用新型的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本实用新型的保护范围之内。

Claims (3)

1.一种SOD系列大功率超低容值静电防护芯片封装结构,其特征在于:它包含金属引线框架(1)、一号静电防护芯片(2)、二号静电防护芯片(3)、三号静电防护芯片(4)、金属导线(6)、环氧树脂塑料塑封(7);金属引线框架(1)设置在环氧树脂塑料塑封(7)内,金属引线框架(1)的引脚露设在环氧树脂塑料塑封(7)的外侧,一号静电防护芯片(2)和三号静电防护芯片(4)电性连接固定在金属引线框架(1)左侧的焊盘上表面的上下两侧,二号静电防护芯片(3)电性连接固定在金属引线框架(1)右侧的焊盘上;三号静电防护芯片(4)利用金属导线(6)与位于右侧的金属引线框架(1)的上表面下侧电性连接;一号静电防护芯片(2)与二号静电防护芯片(3)之间利用金属导线(6)电性连接。
2.根据权利要求1所述的一种SOD系列大功率超低容值静电防护芯片封装结构,其特征在于:所述的一号静电防护芯片(2)的正面开窗处均设有金属球(5),连接一号静电防护芯片(2)和二号静电防护芯片(3)的金属导线(6)的一端与上述金属球(5)电性连接,该金属导线(6)的另一端与二号静电防护芯片(3)电性连接。
3.根据权利要求1所述的一种SOD系列大功率超低容值静电防护芯片封装结构,其特征在于:该封装结构的尺寸为长2.6×宽1.3×高1.0mm。
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Cited By (1)

* Cited by examiner, † Cited by third party
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CN114050149A (zh) * 2022-01-12 2022-02-15 深圳中科四合科技有限公司 一种可变性能参数的esd封装结构及其封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114050149A (zh) * 2022-01-12 2022-02-15 深圳中科四合科技有限公司 一种可变性能参数的esd封装结构及其封装方法

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