CN217588917U - 一种贴片式sot223半导体芯片的封装结构 - Google Patents

一种贴片式sot223半导体芯片的封装结构 Download PDF

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CN217588917U
CN217588917U CN202221795877.0U CN202221795877U CN217588917U CN 217588917 U CN217588917 U CN 217588917U CN 202221795877 U CN202221795877 U CN 202221795877U CN 217588917 U CN217588917 U CN 217588917U
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semiconductor chip
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李尚哲
李明芬
陈育峰
黄凯军
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Anhui Jixin Microelectronics Technology Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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Abstract

本实用新型公开了一种贴片式SOT223半导体芯片的封装结构,包括金属引线框基岛、通过粘结物料设置于金属引线框基岛上的半导体芯片、分别连接在金属引线框基岛两侧的两组金属引脚以及包裹在金属引线框基岛、半导体芯片以及两组金属引脚的外侧的塑封体,本实用新型的第一金属引脚和第二金属引脚的结构较之现有技术中的鸥翼型金属引脚,占用的空间更小,能够在原有线路板上扩大塑封体的体积,从而能够在塑封体内放置更大面积的金属引线框基岛,承载更大面积的半导体芯片,提高半导体芯片兼容性;金属引线框基岛部分伸出塑封体外且能够与线路板接触,能够通过金属引线框基岛将半导体芯片产生的热量传递至线路板上,提高散热效果。

Description

一种贴片式SOT223半导体芯片的封装结构
技术领域
本实用新型涉及半导体封装结构领域,特别涉及一种贴片式SOT223半导体芯片的封装结构。
背景技术
SOT223是一种常用的封装形式,其一般采用海鸥脚封装(如图1),其封装完毕后,一般需要安装在诸如PCB板的基板上,以进行后续的利用,SOT223封装体向外伸出“鸥翼”型态的金属引脚,却也造成了塑封体面积变小,又因为塑封体面积变小限制了半导体芯片能够承载更大面积及更高容量的半导体芯片尺寸能力,无形中降低了很多中大型半导体芯片的兼容性与不方便,从而又增加了需要承载更大半导体芯片更高容量半导体芯片的封装体,结果在制造成本以及使用PCB面积上,又无形的将成本提升上去,因此需要设计一种新的贴片式SOT223半导体芯片的封装结构,来解决“鸥翼”型态的金属引脚存在的上述问题。
实用新型内容
本实用新型提供一种贴片式SOT223半导体芯片的封装结构,可以解决背景技术中所指出的问题。
一种贴片式SOT223半导体芯片的封装结构,包括:
金属引线框基岛;
半导体芯片,通过粘结物料设置于所述金属引线框基岛上;
第一金属引脚和第二金属引脚,分别连接在所述金属引线框基岛相对的两侧;以及
塑封体,包裹在所述金属引线框基岛、所述半导体芯片以及两组金属引脚的外侧;
第一金属引脚包括引线部、金属引脚部A和金属引脚部B;
第二金属引脚包括金属引脚部A和金属引脚部B。
较佳的,所述金属引脚部A和所述金属引脚部B均为V型;
金属引脚部A具有一水平侧边和一竖直侧边;
金属引脚部B的开口朝上,且其中一个侧边与金属引脚部A的水平侧边连接;
第一金属引脚的金属引脚部A的水平侧边的端部与引线部连接,引线部与金属引线框基岛连接;
第二金属引脚的金属引脚部A的水平侧边的上部通过键合线与金属引线框基岛连接。
较佳的,所述金属引脚部A的水平侧边与半导体芯片的顶面齐平。
较佳的,所述塑封体上形成有分别与两组金属引脚配合的缺口槽。
较佳的,所述塑封体的下部形成有一通槽,以使得所述金属引线框基岛的下部伸出塑封体外。
较佳的,所述金属引线框基岛的底面与金属引脚的底面齐平。
与现有技术相比,本实用新型的有益效果是:本实用新型的第一金属引脚和第二金属引脚的结构较之现有技术中的鸥翼型金属引脚,占用的空间更小,能够在原有线路板上扩大塑封体的体积,从而能够在塑封体内放置更大面积的金属引线框基岛,承载更大面积的半导体芯片,提高半导体芯片兼容性,或者在相同的线路板上能够装有更多的封装结构,或者在封装结构数量相同的情况下,所用的线路板的面积可以做的更小,节约成本;
金属引线框基岛部分伸出塑封体外且能够与线路板接触,能够通过金属引线框基岛将半导体芯片产生的热量传递至线路板上,提高散热效果。
附图说明
图1为现有技术的贴片式SOT223半导体芯片的封装结构的结构示意图;
图2为本实用新型的结构示意图;
图3为本实用新型的金属引脚结构示意图;
图4为本实用新型底部的结构示意图;
图5为本实用新型的内部结构示意图;
图6为现有技术的贴片式SOT223半导体芯片的封装结构的尺寸图;
图7为本实用新型的贴片式SOT223半导体芯片的封装结构的尺寸图;
图8为本实用新型的贴片式SOT223半导体芯片的封装结构焊接在PCB板上的结构示意图。
附图标记说明:
1-金属引线框基岛,2-半导体芯片,3-塑封体,4-第一金属引脚,41-引线部,5-第二金属引脚,6-键合线,7-缺口槽,8-金属引脚部A,9-金属引脚部B,10-爬锡形状。
具体实施方式
下面结合附图,对本实用新型的一个具体实施方式进行详细描述,但应当理解本实用新型的保护范围并不受具体实施方式的限制。
实施例一
如图1-图3和图5-图8所示,本实用新型实施例提供的一种贴片式SOT223半导体芯片的封装结构,包括金属引线框基岛1、通过粘结物料设置于金属引线框基岛1上的半导体芯片2、分别连接在金属引线框基岛1两侧的两组金属引脚以及包裹在金属引线框基岛1、半导体芯片2以及两组金属引脚的外侧的塑封体,两组金属引脚分别为第一金属引脚4和第二金属引脚5,第一金属引脚4的数量为一个,第二金属引脚5的数量为三个,第一金属引脚4包括引线部41、金属引脚部A8和金属引脚部B9,第二金属引脚5包括金属引脚部A8和金属引脚部B9;
粘结物料为金属锡膏或导电胶;
金属引脚部A8和金属引脚部B9均为V型;金属引脚部A8具有一水平侧边和一竖直侧边;
金属引脚部B9的开口朝上,且其中一个侧边与金属引脚部A8的水平侧边连接,为便于爬锡,金属引脚B9底部的V型角处设置有圆滑倒角,在将其焊接在PCB上时的爬锡形状10如图8所示,使得金属锡膏与金属引脚之间的连接更加紧密;
第一金属引脚4的金属引脚部A8的水平侧边的端部与引线部41连接,引线部41与金属引线框基岛1连接;
第二金属引脚5的金属引脚部A8的水平侧边的上部通过键合线6与金属引线框基岛1连接;
为便于塑封体3的封装,所述金属引脚部A8的水平侧边与半导体芯片2的顶面齐平;
第一金属引脚4和第二金属引脚5的结构较之于现有技术中的贴片式SOT223半导体芯片的封装结构的“鸥翼”型结构,占用的面积更小,在封装结构的尺寸为6.85mm*6.3mm的情况下,采用现有的海鸥型金属引脚结构时,如图6所示,其金属引线框基岛1的尺寸为2.57mm*5.94mm,金属引脚伸出塑封体3外的尺寸为1.67mm,以上尺寸的误差均在±0.1mm内,采用本申请的金属引脚结构时,如图7所示,其金属引线框基岛1的尺寸为4.76mm*5.94mm,金属引脚伸出塑封体3外的尺寸为0.32mm,以上尺寸的误差均在±0.1mm内,综上所述,在封装结构的尺寸相同的情况下,本申请的金属引线框基岛1的面积比现有封装结构的金属引线框基岛1的面积大了2.19mm*5.94mm,即金属引线框基岛1的面积增大了85.2%,因此本申请封装结构的金属引线框基岛1能够承载更大面积以及更高容量的半导体芯片2,在面积变大的情况下能够进一步提高散热效果;
另外,采用第一金属引脚4和第二金属引脚5的贴片式SOT223半导体芯片的封装结构的尺寸小于现有技术中贴片式SOT223半导体芯片的封装结构,那么在相同的PCB板上可以安装更多的半导体芯片2,或者在封装结构数量相同的情况下所需的PCB板的面积更小,这样更加节约成本;
为了便于收纳金属引脚,塑封体3上形成有分别与两组金属引脚配合的缺口槽7。
实施例二
在实施例一的基础上,如图4所示,塑封体3的下部形成有一通槽,以使得金属引线框基岛1的下部伸出塑封体3外,从而让金属引线框基岛1与PCB板连接,这样可以借助PCB板本身带有的散热部分来进行散热。
为了让金属引线框基岛1和金属引脚与PCB板之间的连接互不干扰,金属引线框基岛1的底面最好与金属引脚的底面齐平。
对于本领域技术人员而言,显然本实用新型不限于上述示范性实施例的细节,而且在不背离本实用新型的精神和基本特征的情况下,能够以其他的具体形式实现本实用新型。因此,无论从哪一点来看,均应将实施例看作是示范性的,而且是非限制性的,本实用新型的范围由所附权利要求而不是上述说明限定,因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本实用新型内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外,应当理解,虽然本说明书按照实施方式加以描述,但并非每个实施方式仅包含一个独立的技术方案,说明书的这种叙述方式仅仅为清楚起见,本领域技术人员应当将说明书作为一个整体,各实施例中的技术方案也可以经适当组合,形成本领域技术人员可以理解的其他实施方式。

Claims (6)

1.一种贴片式SOT223半导体芯片的封装结构,其特征在于,包括:
金属引线框基岛;
半导体芯片,通过粘结物料设置于所述金属引线框基岛上;
第一金属引脚和第二金属引脚,分别连接在所述金属引线框基岛相对的两侧;以及
塑封体,包裹在所述金属引线框基岛、所述半导体芯片以及两组金属引脚的外侧;
第一金属引脚包括引线部、金属引脚部A和金属引脚部B;
第二金属引脚包括金属引脚部A和金属引脚部B。
2.如权利要求1所述的一种贴片式SOT223半导体芯片的封装结构,其特征在于,所述金属引脚部A和所述金属引脚部B均为V型;
金属引脚部A具有一水平侧边和一竖直侧边;
金属引脚部B的开口朝上,且其中一个侧边与金属引脚部A的水平侧边连接;
第一金属引脚的金属引脚部A的水平侧边的端部与引线部连接,引线部与金属引线框基岛连接;
第二金属引脚的金属引脚部A的水平侧边的上部通过键合线与金属引线框基岛连接。
3.如权利要求2所述的一种贴片式SOT223半导体芯片的封装结构,其特征在于,所述金属引脚部A的水平侧边与半导体芯片的顶面齐平。
4.如权利要求1所述的一种贴片式SOT223半导体芯片的封装结构,其特征在于,所述塑封体上形成有分别与两组金属引脚配合的缺口槽。
5.如权利要求1所述的一种贴片式SOT223半导体芯片的封装结构,其特征在于,所述塑封体的下部形成有一通槽,以使得所述金属引线框基岛的下部伸出塑封体外。
6.如权利要求5所述的一种贴片式SOT223半导体芯片的封装结构,其特征在于,所述金属引线框基岛的底面与金属引脚的底面齐平。
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