CN210723008U - 解决5G GaN芯片焊接高可靠性要求的封装焊接结构 - Google Patents
解决5G GaN芯片焊接高可靠性要求的封装焊接结构 Download PDFInfo
- Publication number
- CN210723008U CN210723008U CN201922009625.5U CN201922009625U CN210723008U CN 210723008 U CN210723008 U CN 210723008U CN 201922009625 U CN201922009625 U CN 201922009625U CN 210723008 U CN210723008 U CN 210723008U
- Authority
- CN
- China
- Prior art keywords
- welding
- chip
- lead frame
- brace table
- annular groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Die Bonding (AREA)
Abstract
本实用新型涉及一种解决5G GaN芯片焊接高可靠性要求的封装焊接结构,包括芯片和引线框基岛,所述引线框基岛上表面设有一环形凹槽,所述环形凹槽内侧形成焊接支撑台,所述焊接支撑台上表面低于引线框基岛的上表面,焊接支撑台上表面还阵列设有多个高度相同的支撑凸点,芯片通过烧结银胶焊接在焊接支撑台上。通过调整焊接支撑台上表面与引线框基岛的上表面之间的高度差,可以使外溢的烧结银胶即能反包芯片边缘,形成爬胶,同时又能避免烧结银胶爬胶过高;所述支撑凸点能有效的帮助将烧结银胶中的空气排挤出去,能使焊接层空洞率减少到2%以内,支撑凸点能保证芯片放置时的平整,避免出现芯片倾斜,能提升产品的焊接可靠性和产品的散热性。
Description
技术领域
本实用新型涉及芯片封装技术领域,尤其涉及一种解决5G GaN芯片焊接高可靠性要求的封装焊接结构。
背景技术
5G应用的氮化镓/碳化硅(GaN/SiC)产品在工作时电流大、功率高,工作温度会高达250度,这就要求芯片封装产品具有高散热性、高可靠性的特性,为了满足这些要求,尤其是高散热性要求,对产品的封装材料(塑封料、焊接料)也有较高要求,都需要具有高导热性的特性,尤其是芯片底部的焊接料,连接了芯片和引线框基岛,芯片产生的热先传递到引线框基岛上,再散失到空气中,是决定产品散热性能的非常关键性的材料。目前,为了满足产品的高散热要求,都选用热导率大于100W/(m.K)的焊接材料,既烧结银胶,但是此类材料也有一些缺点,在烘烤固化焊接后,芯片与引线框基岛之间的焊接料中会出现很多空洞,这严重的影响了产品的散热性。
不同界面散热性计算公式:Q=a(tw-to)F式中,Q为散热量,单位为w。其中,tw为热源的表面温度,单位为℃,如芯片底面;to为外界散热源温度,单位为℃,如引线框基岛;F为散热面的面积,单位为m2,近似焊接层的层面积;a为综合换热系数,w/(℃×m2),与热交换的材料热导率成正比,近似烧结银胶的热导率。通过上述散热性公式可以推导得出:当产品材料结构相同时,tw,to,a均为定值,而F直接受焊接空洞率的影响,30%焊接空洞率意味着,整体散热量Q会降低为70%,对产品散热性有着显著影响,会造成产品热量无法及时散出而累积,使产品自身的温度上升,影响产品的工作稳定性及可靠性。同时,有试验也证实表明,芯片与引线框基岛之间焊接空洞面积与产品散热性呈明显的反比关系,当产品工作一定的时间后,由于焊接空洞造成的散热性差会导致产品异常,降低产品寿命,甚至直接失效(Chiriac VA,Yu Y.Impacts of solder voids on PQFN packages‘thermal andmechanical performances[C].Thermal&Thermomechanical Phenomena in ElectronicSystems.IEEE,2010:1-7;郑钢涛,陈素鹏,胡俊,et al.焊料层空洞面积对功率器件电阻和热阻的影响[J].半导体技术,2010(11):16-20)。
如图1所示,为现有技术中的一种芯片封装结构,包括引线框5、引线框基岛2、芯片1、金线7、焊接料3和塑封料6,现有技术中焊接料3厚度一般采用15-20μm,在烘烤固化焊接后,芯片1与引线框基岛2之间的焊接料3中会出现很多空洞,芯片1与引线框基岛2之间焊接空洞面积与产品散热性呈明显的反比关系,这严重的影响了芯片封装产品的散热性,散热性差会导致产品异常,降低产品寿命,甚至直接失效。
当前产品一般对芯片焊接层空洞率要求小于25%(JEDEC J-STD-033),而此类GaN/SiC产品的特殊应用对其散热性要求很高,焊接层空洞率不大于5%,为了减少焊接空洞,通过高导热性烧结银胶DOE实验优化后发现,当焊接料的用量要达到一定要求,既厚度大于30μm时,焊接空洞会明显降低,可使焊接空洞会降低到2%以下,能满足散热要求。当焊接料的厚度大于30μm时,虽然解决了焊接空洞问题,但对后续封装工艺又产生了不利影响,由于焊接料厚度大,很容易在装片时出现芯片倾斜超标,严重影响焊接质量和产量,同时芯片倾斜也会造成芯片散热不均匀,影响散热稳定性;芯片边缘焊接料溢料超标,焊接料爬高控制困难,使产品的生产很不稳定,既造成了生产质量难以管控,又影响了产品的产能,并且随着焊接料的厚度继续增大,上述问题会更加突出严重,这就需要有好的方案来解决这些问题。
实用新型内容
本实用新型的目的在于提供一种解决5G GaN芯片焊接高可靠性要求的封装焊接结构,既能解决焊接空洞问题,又能解决芯片倾斜超标的问题。
本实用新型是这样实现的:一种解决5G GaN芯片焊接高可靠性要求的封装焊接结构,包括芯片和引线框基岛,所述引线框基岛上表面设有一环形凹槽,所述环形凹槽内侧形成焊接支撑台,所述焊接支撑台的形状和面积与芯片相适配,所述焊接支撑台上表面低于引线框基岛的上表面,所述焊接支撑台上表面还阵列设有多个高度相同的支撑凸点,所述支撑凸点的高度为30-50μm,所述芯片通过烧结银胶焊接在焊接支撑台上,烧结银胶的厚度等于或稍大于支撑凸点的高度。
其中,所述环形凹槽的深度为80-120μm,环形凹槽的宽度为100-200μm。
其中,所述焊接支撑台的高度为50-75μm。
其中,所述支撑凸点的直径尺寸为30-60μm。
其中,所述引线框基岛上表面还设有镀银层。
其中,所述封装焊接结构还包括引脚、金线和塑封体,所述金线用于连接芯片和引脚,所述塑封体用于封装整个产品。
本实用新型的有益效果为:本实用新型设计了一种新的封装焊接结构,在引线框基岛上表面设置了一环形凹槽,因为烧结银胶增加了厚度(原来厚度为15-20μm,现在至少为30μm),导致向芯片四周外溢比原来严重,所述环形凹槽用于围住烧结银胶,形成对烧结银胶的围坝结构,控制外溢范围;所述焊接支撑台的尺寸与芯片的尺寸相适配,而且所述焊接支撑台上表面低于引线框基岛的上表面,二者之间形成一定的高度差,通过调整该高度差,可以使外溢的烧结银胶即能反包芯片边缘,形成爬胶,同时又能避免烧结银胶爬胶过高,使芯片边缘四周及顶面受到沾污;所述支撑凸点为微型凸台,高度需依据实际要点胶的厚度来设计,一般大于30μm,支撑凸点的顶部形成一个平整的支撑面,能有效的帮助将烧结银胶中的空气排挤出去,能使焊接层空洞率减少到2%以内,支撑凸点能保证芯片放置时的平整,避免出现芯片倾斜,在固化焊接过程中还能校正芯片倾斜,最大程度减小芯片倾斜(只有烧结银胶厚度超过支撑凸点高度时,芯片才有可能出现倾斜,但倾斜很小),并且改善焊接料溢料超标的问题,另外,支撑凸点还能增加与烧结银胶的接触面积,提供更多的机械交叉结合面,增强烧结银胶层与引线框基岛的结合强度,提升产品的焊接可靠性,从而提升产品的质量和可靠性,支撑凸点和烧结银胶混合焊接层的导热性都要远远好于纯烧结银胶的焊接层(烧结银胶热导率100-200W/(m.K)铜的热导率400W/(m.K)),所以还能提高产品的散热性,所得产品甚至可以在400度的高温条件下长时工作,由于支撑凸点占据原焊接层一定的空间,新设计的结构烧结银胶的使用量会减少,降低成本。
附图说明
图1是本实用新型所述封装焊接结构实施例中引线框基岛的俯视图;
图2是图1中A-A向剖示图;
图3是在引线框基岛上点烧结银胶后的结构示意图;
图4是把芯片焊接到引线框基岛后的结构示意图;
图5是本实用新型所述引线框基岛未加工前的剖面示意图;
图6是本实用新型在引线框基岛上加工出环形凹槽的结构示意图;
图7是本实用新型在引线框基岛上加工出焊接支撑台的结构示意图;
图8是本实用新型在引线框基岛上加工出支撑凸点的结构示意图;
图9是本实用新型所述封装焊接结构实施例中金线将芯片和引脚连接起来的结构示意图;
图10是本实用新型所述封装焊接结构实施例中进行塑封后的结构示意图;
图11是本实用新型所述封装焊接结构应用在单基岛单区域焊接结构产品上的示意图;
图12是本实用新型所述封装焊接结构应用在单基岛多区域焊接结构产品上的示意图;
图13是本实用新型所述封装焊接结构应用在多基岛多区域焊接结构产品上的示意图。
其中,1、芯片;2、引线框基岛;21、环形凹槽;22、焊接支撑台;23、支撑凸点;3、烧结银胶;4、引脚;5、金线;6、塑封体。
具体实施方式
为了使本实用新型的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本实用新型进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本实用新型,并不用于限定本实用新型。
作为本实用新型所述解决5G GaN芯片焊接高可靠性要求的封装焊接结构的实施例,如图1至图10所示,包括芯片1和引线框基岛2,所述引线框基岛2上表面设有一环形凹槽21,所述环形凹槽21内侧形成焊接支撑台22,所述焊接支撑台22的形状和面积与芯片1相适配,所述焊接支撑台22上表面低于引线框基岛2的上表面,所述焊接支撑台22上表面还阵列设有多个高度相同的支撑凸点23,所述支撑凸点23的高度为30-50μm,所述芯片1通过烧结银胶3焊接在焊接支撑台22上,烧结银胶3的厚度等于或稍大于支撑凸点23的高度。
本实用新型设计了一种新的封装焊接结构,在引线框基岛2上表面设置了一环形凹槽21,因为烧结银胶3增加了厚度(原来厚度为15-20μm,现在至少为30μm),导致向芯片1四周外溢比原来严重,所述环形凹槽21用于围住烧结银胶3,形成对烧结银胶3的围坝结构,控制外溢范围;所述焊接支撑台22的尺寸与芯片1的尺寸相适配,而且所述焊接支撑台22上表面低于引线框基岛2的上表面,二者之间形成一定的高度差,通过调整该高度差,可以使外溢的烧结银胶3即能反包芯片1边缘,形成爬胶,同时又能避免烧结银胶3爬胶过高,使芯片1边缘四周及顶面受到沾污;所述支撑凸点23为微型凸台,高度需依据实际要点胶的厚度来设计,一般大于30μm,支撑凸点23的顶部形成一个平整的支撑面,能有效的帮助将烧结银胶4中的空气排挤出去,能使焊接层空洞率减少到2%以内,支撑凸点23能保证芯片1放置时的平整,避免出现芯片1倾斜,在固化焊接过程中还能校正芯片1倾斜,最大程度减小芯片1倾斜(只有烧结银胶厚度超过支撑凸点高度时,芯片才有可能出现倾斜,但倾斜很小),并且改善焊接料溢料超标的问题,另外,支撑凸点还能增加与烧结银胶的接触面积,提供更多的机械交叉结合面,增强烧结银胶层与引线框基岛的结合强度,提升产品的焊接可靠性,从而提升产品的质量和可靠性,支撑凸点23和烧结银胶3混合焊接层的导热性都要远远好于纯烧结银胶的焊接层(烧结银胶热导率100-200W/(m.K)铜的热导率400W/(m.K)),所以还能提高产品的散热性,所得产品甚至可以在400度的高温条件下长时工作,由于支撑凸点23占据原焊接层一定的空间,新设计的结构烧结银胶3的使用量会减少,降低成本。
本实用新型所述的封装焊接结构不仅可以应用在高散热要求的GaN/SiC类芯片的焊接,由于具有高的通用性,也可以广泛应用于普通芯片产品的封装焊接结构中。
本实用新型所述封装焊接结构需满足一定的结构高度设计原理方可达到最优化结果,其具体结构高度原理及关系如下:一般情况下,所述环形凹槽21的深度为引线框基岛1厚度的一半为宜,采用半蚀刻工艺,易于实现。根据现有的引线框基岛厚度常规选用范围,所述环形凹槽21的深度优选值为80-120μm,环形凹槽21的宽度优选值为100-200μm。
假设现有技术中的结构引线框基岛在点胶后的溢胶量V大约为100%(芯片爬胶)*H(芯片厚度)*W(溢胶宽度)*R(芯片外径)*1/2,V=1/2*100%*H*W*R。由于芯片外径R和芯片厚度H都不变,所以为保证新的封装焊接结构基岛的爬胶50%左右,环形凹槽宽度为控制的溢胶宽度,假设胶总量V1,(B环形凹槽深度+芯片爬胶率*H芯片厚度)*W环形凹槽宽度*R芯片外径*1/2,既V1=1/2(B+50%*H)*W*R。点胶总量不变情况下,V=V1,1/2x100%*H*R*W=1/2(B+50%*H)*R*W,故B=1/2H,由于焊接支撑台的支撑凸点占据焊接层空间,实际溢出的胶会多于原设计结构,为保证更多溢出胶也在控制范围内,B的优选值在1/3H-1/2H之间。
在本实施例中,所述焊接支撑台22的高度为环形凹槽21深度的1/2-2/3之间,为优选值,具体数值为50-75μm,不同的产品可能需要设置不同的参数,通过调整该高度差,可以使外溢的烧结银胶3即能反包芯片1边缘,形成爬胶,同时又能避免烧结银胶3爬胶过高,使芯片1边缘四周及顶面受到沾污。
在本实施例中,所述支撑凸点23的直径尺寸为30-60μm,(此处特指支撑凸点顶部的尺寸)尺寸较小,在制作时不会对引线框基岛2产生大的影响。下方的烧结银胶3厚度需要等于或超过支撑凸点23的高度,保证烧结银胶3厚度大于30μm,便于控制,能保证生产稳定,解决焊接空洞的问题,支撑凸点23上方的烧结银胶3非常少,正常情况下少于10μm,所以能减少芯片装贴时倾斜。
在本实施例中,所述封装焊接结构还包括引脚4、金线5和塑封体6,所述金线5用于连接芯片1和引脚4,所述塑封体6用于封装整个产品,以形成完整的封装产品。
由于引线框基岛2结构复杂,各结构精度要求高,制造工艺难度加大,需要同时使用多种工艺来加工,具体包括化学蚀刻、激光蚀刻和冲压成型,首先引线框需要预成型,加工出引线框基岛2和引脚4,然后再在引线框基岛2上加工细部结构,如图5至图8所示,需要先通过半蚀刻制作出环形凹槽21,蚀刻深度可通过控制化学时间来实现;然后利用激光蚀刻的方式制作出焊接支撑台22,蚀刻深度可通过控制激光的运行电流或者烧蚀速度来实现(激光蚀刻精度高,易于控制,可以弥补冲压成型或化学蚀刻工艺无法实现对焊接支撑台的精细加工);最后利用冲压成型或者背部冲击等方式加工出支撑凸点23。在涂覆烧结银胶3时,可以采用点胶或化胶模式,即使点胶量稍大,引线框基岛1上环形凹槽21形成的围坝结构也能有效地防止烧结银胶4外溢,支撑凸点23有助于排除烧结银胶3中的空气,焊接层区域的敞口设计更加利于固化时空气的排除。
在本实用新型中,本实用新型设计不仅仅适用于单基岛单区域焊接结构产品(如图11所示),也可用于单基岛多区域焊接结构(如图12所示)及多基岛多区域焊接结构产品(如图13所示),具体情况依据产品实际需求设计,但结果原理均相同。
在本实用新型中,还需要根据不同烧结银胶的特性来确定是否需要对焊接支撑台及支撑凸点进行表面镀膜处理,以实现最佳的焊接结合性能,比如在引线框基岛上表面设置镀银层,以增强焊接支撑台、支撑凸点与亲银型烧结银胶的结合强度。
以上所述仅为本实用新型的较佳实施例而已,并不用以限制本实用新型,凡在本实用新型的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本实用新型的保护范围之内。
Claims (6)
1.一种解决5G GaN芯片焊接高可靠性要求的封装焊接结构,其特征在于,包括芯片和引线框基岛,所述引线框基岛上表面设有一环形凹槽,所述环形凹槽内侧形成焊接支撑台,所述焊接支撑台的形状和面积与芯片相适配,所述焊接支撑台上表面低于引线框基岛的上表面,所述焊接支撑台上表面还阵列设有多个高度相同的支撑凸点,所述支撑凸点的高度为30-50μm,所述芯片通过烧结银胶焊接在焊接支撑台上,烧结银胶的厚度等于或稍大于支撑凸点的高度。
2.根据权利要求1所述的封装焊接结构,其特征在于,所述环形凹槽的深度为80-120μm,环形凹槽的宽度为100-200μm。
3.根据权利要求1所述的封装焊接结构,其特征在于,所述焊接支撑台的高度为50-75μm。
4.根据权利要求1所述的封装焊接结构,其特征在于,所述支撑凸点的直径尺寸为30-60μm。
5.根据权利要求1所述的封装焊接结构,其特征在于,所述引线框基岛上表面还设有镀银层。
6.根据权利要求1至5任一项所述的封装焊接结构,其特征在于,所述封装焊接结构还包括引脚、金线和塑封体,所述金线用于连接芯片和引脚,所述塑封体用于封装整个产品。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201922009625.5U CN210723008U (zh) | 2019-11-19 | 2019-11-19 | 解决5G GaN芯片焊接高可靠性要求的封装焊接结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201922009625.5U CN210723008U (zh) | 2019-11-19 | 2019-11-19 | 解决5G GaN芯片焊接高可靠性要求的封装焊接结构 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN210723008U true CN210723008U (zh) | 2020-06-09 |
Family
ID=70937858
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201922009625.5U Active CN210723008U (zh) | 2019-11-19 | 2019-11-19 | 解决5G GaN芯片焊接高可靠性要求的封装焊接结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN210723008U (zh) |
-
2019
- 2019-11-19 CN CN201922009625.5U patent/CN210723008U/zh active Active
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN110783304A (zh) | 解决5G GaN芯片焊接高可靠性要求的封装焊接结构 | |
US7119426B2 (en) | Semiconductor device and manufacturing method of same | |
CN100421251C (zh) | 半导体装置及其制造方法 | |
US7863731B2 (en) | Heat-dissipating structure and heat-dissipating semiconductor package having the same | |
JP6847266B2 (ja) | 半導体パッケージおよびその製造方法 | |
CN102386112B (zh) | 半导体器件的制造方法 | |
TW200522295A (en) | Semiconductor package with flip chip on leadframe | |
JPH11330313A (ja) | 半導体装置の製造方法及びその構造、該方法に用いるリードフレーム | |
KR101609495B1 (ko) | 반도체 장치 및 반도체 장치의 제조 방법 | |
JP2019012755A (ja) | 半導体装置の製造方法および半導体装置 | |
CN106158783B (zh) | 具有防溢胶结构的散热片装置 | |
CN210723008U (zh) | 解决5G GaN芯片焊接高可靠性要求的封装焊接结构 | |
US20130048351A1 (en) | Electronic package structure and method for manufacturing same | |
JP2014146645A (ja) | 半導体装置 | |
JP2008235859A (ja) | 半導体装置とその製造方法 | |
CN210167324U (zh) | 一种芯片封装产品 | |
JP2010147225A (ja) | 半導体装置及びその製造方法 | |
TWI296839B (en) | A package structure with enhancing layer and manufaturing the same | |
CN100394569C (zh) | 防止封装元件溢胶的方法 | |
JP2011222823A (ja) | 回路装置およびその製造方法 | |
CN106328611B (zh) | 半导体封装构造及其制造方法 | |
CN217444382U (zh) | 半导体封装框架及结构 | |
JP2021027211A (ja) | 電子装置 | |
CN111540725B (zh) | 引线框架、方形扁平无引脚封装结构及封装方法 | |
CN107845721A (zh) | 一种用于倒装或垂直led芯片的led支架 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |