CN210488287U - Voice simulator and output circuit thereof - Google Patents
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- CN210488287U CN210488287U CN201921931862.0U CN201921931862U CN210488287U CN 210488287 U CN210488287 U CN 210488287U CN 201921931862 U CN201921931862 U CN 201921931862U CN 210488287 U CN210488287 U CN 210488287U
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Abstract
The application discloses a voice simulator and an output circuit thereof, wherein the output circuit of the voice simulator comprises a buffer output module and an output indication module, and the buffer output module is connected with an interface conversion main chip of the voice simulator and is used for buffering and outputting simulation signals and debugging signals of the interface conversion main chip; and the output indicating module is connected with the interface conversion main chip and used for indicating the working state of the interface conversion main chip. The buffer output module arranged between the interface conversion main chip and the voice module is utilized, the driving capability of simulation signals and debugging signals can be enhanced on the basis of effective control on simulation verification and operation debugging of the voice module, the anti-interference capability is improved, normal work of the voice simulator is guaranteed, and therefore product research and development of the voice module are facilitated, and product promotion to the market is accelerated.
Description
Technical Field
The present application relates to the field of speech development technologies, and in particular, to a speech simulator and an output circuit thereof.
Background
In recent years, the application of the voice module in various intelligent prototypes is more and more extensive, and particularly, along with the development of technologies such as the internet of things, the voice module is widely integrated into various electronic devices so as to realize intelligent interaction between users and the devices. When a voice module is developed, a complete set of voice development kit is utilized to perform simulation verification and debugging operation, so that the voice module is more convenient for users to use, the research and development period is shortened, and the product is helped to be rapidly pushed to the market.
SUMMERY OF THE UTILITY MODEL
The application aims to provide a voice simulator and an output circuit thereof, so that simulation verification and operation debugging of a voice module can be effectively realized, and product development efficiency is improved.
To solve the above technical problem, in a first aspect, the present application discloses an output circuit of a speech simulator, comprising:
the buffer output module is connected with the interface conversion main chip of the voice simulator and is used for buffering and outputting the simulation signal and the debugging signal of the interface conversion main chip;
and the output indicating module is connected with the interface conversion main chip and used for indicating the working state of the interface conversion main chip.
Optionally, the buffer output module is compatible with a four-wire system simulation output standard and a two-wire system simulation output standard.
Optionally, the buffer output module includes:
and the control end and the input end of the buffer chip circuit are connected with the interface conversion main chip and are used for signal caching or signal output.
Optionally, the buffer output module further includes:
the first resistor bank is connected between the interface conversion main chip and the buffer chip circuit and used for transmitting the simulation signal;
the second resistor bank is connected with the simulation signal output port of the buffer chip circuit; the first resistor bank and the second resistor bank are used for impedance matching.
Optionally, the buffer output module further includes:
the third resistor bank is connected between the interface conversion main chip and the buffer chip circuit and used for transmitting the debugging signal;
the fourth resistor bank is connected with the debugging signal output port of the buffer chip circuit; the third resistor bank and the fourth resistor bank are used for impedance matching.
Optionally, the buffer output module further includes:
and the pull-up resistors are respectively connected between each control end of the buffer chip circuit and the power supply.
Optionally, the output indication module is an LED indication module.
Optionally, the LED indication module includes a power status LED indication unit, a simulation communication status LED indication unit, and a debugging communication status LED indication unit.
Optionally, the power status LED indication unit includes a first light emitting diode having an anode connected to a power supply, and a ground resistor connected to a cathode of the first light emitting diode;
the simulation communication state LED indicating unit comprises a second light-emitting diode with an anode connected with a power supply and a second current-limiting resistor connected with a cathode of the second light-emitting diode; the other end of the second current-limiting resistor is connected with the simulation signal output end of the interface conversion main chip;
the debugging communication state LED indicating unit comprises a third light-emitting diode with an anode connected with a power supply and a third current-limiting resistor connected with a cathode of the third light-emitting diode; the other end of the third current limiting resistor is connected with a debugging signal output end of the interface conversion main chip.
In a second aspect, the present application also discloses a speech simulator comprising any one of the output circuits described above.
The output circuit of the voice simulator provided by the embodiment of the application comprises a buffer output module and an output indication module, wherein the buffer output module is connected with an interface conversion main chip of the voice simulator and is used for buffering and outputting a simulation signal and a debugging signal of the interface conversion main chip; and the output indicating module is connected with the interface conversion main chip and used for indicating the working state of the interface conversion main chip.
Therefore, the buffer output module arranged between the interface conversion main chip and the voice module is utilized, the driving capability of simulation signals and debugging signals can be enhanced on the basis of effectively controlling simulation verification and operation debugging of the voice module, the anti-jamming capability is improved, the normal work of the voice simulator is guaranteed, the product research and development of the voice module are facilitated, and the product market promotion is accelerated. The voice simulator provided by the application also has the beneficial effects.
Drawings
In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the drawings that are needed to be used in the description of the prior art and the embodiments of the present application will be briefly described below. Of course, the following description of the drawings related to the embodiments of the present application is only a part of the embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any creative effort, and the obtained other drawings also belong to the protection scope of the present application.
Fig. 1 is a block diagram of an output circuit of a speech simulator disclosed in an embodiment of the present application;
FIG. 2 is a circuit diagram of a first portion of an output circuit of a speech emulator according to an embodiment of the present disclosure;
fig. 3 is a circuit connection diagram of a second part of an output circuit of a speech emulator according to an embodiment of the present application.
Detailed Description
The core of the application lies in providing a voice simulator and an output circuit thereof, so as to effectively realize simulation verification and operation debugging of a voice module and improve the product development efficiency.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, the application of voice module in all kinds of intelligent prototype machines is more and more extensive, especially along with the development of technologies such as thing networking, voice module is extensively integrated to all kinds of electronic equipment to realize the intelligent interaction between user and the equipment. When a voice module is developed, a complete set of voice development kit is utilized to perform simulation verification and debugging operation, so that the voice module is more convenient for users to use, the research and development period is shortened, and the product is helped to be rapidly pushed to the market. In view of the above, the present application provides a speech simulator and an output circuit thereof.
Referring to fig. 1, an embodiment of the present application discloses an output circuit of a speech simulator, which mainly includes:
the buffer output module 101 is connected with an interface conversion main chip of the voice simulator and is used for buffering and outputting simulation signals and debugging signals of the interface conversion main chip;
and the output indicating module 102 is connected with the interface conversion main chip and is used for indicating the working state of the interface conversion main chip.
Specifically, the voice simulator is in communication connection with the voice module, and can perform single-step trace debugging on an embedded program in the voice module, or adopt debugging means such as breakpoint and full speed, and the like, and can observe real-time data of various variables, RAM and registers, trace the execution condition of the program, and perform real-time debugging on a hardware circuit. The voice simulator is used for carrying out simulation verification and operation debugging on the voice module, so that the logic errors in the voice module program can be quickly positioned and eliminated, and the development cycle of the voice suite is greatly shortened.
It should be noted that the buffering output module 101 is arranged in the voice simulator disclosed in the embodiment of the present application, and the buffering output module 101 is specifically connected between the interface conversion main chip and the voice module as a part of an output circuit of the voice simulator, so as to enhance signal driving capability, ensure normal operation of the voice simulator, improve accuracy and fidelity of outputting simulation signals and debugging signals to the voice module, and enhance anti-interference capability.
The interface conversion main chip needs to communicate with a voice module in the voice development kit for transmission, so that the function simulation verification and fault debugging operation of the voice module are realized, and simulation signals and debugging signals are transmitted. Therefore, the speech simulator needs to have two functional interfaces: one is JTAG/SWD interface for simulation verification of voice module; the other is a UART interface used for debugging the operation of the voice module.
The buffer output module 101 can be designed and implemented by those skilled in the art based on the above application requirements. As a specific embodiment, in order to improve the compatibility and applicability of the voice simulator, in the embodiment of the present application, the buffer output module 101 may be compatible with a four-wire system simulation output standard and a two-wire system simulation output standard.
Specifically, when performing simulation verification on the voice module, the simulation signal output after being processed by the buffer output module 101 may specifically adopt a JTAG interface form, and may be compatible with two standards, namely a four-wire system standard and a two-wire system standard. In the four-wire system simulation output standard, the output simulation signals specifically include a TCK (clock) signal, a TMS (control) signal, a TDI (input data) signal, a TDO (output data) signal, and a RESET (RESET) signal. In the two-wire simulation output standard, the output simulation signals specifically include a SWCLK (clock) signal and a SWDIO (input/output data) signal.
In the output circuit of the voice simulator disclosed in the embodiment of the present application, the buffer output module 101 further performs logic conversion on the signal output by the interface conversion main chip on the basis of performing buffer output on the original signal, so as to generate a simulation signal compatible with a four-wire system and a two-wire system according to the actual application requirement, and output a debugging signal at the same time. The two-wire SWCLK signal and the SWDIO signal may be specifically multiplexed with the four-wire TCK signal and the TMS signal, respectively.
In order to distinguish the simulation signal before being processed by the buffer output module 101 from the simulation signal after being processed, the simulation signal before being processed may be sequentially referred to as an FCK (clock) signal, an FCS (control) signal, an FDI (input data) signal, an FDO (output data) signal, and a DRST (reset) signal.
On the other hand, when the voice module is subjected to run debugging, the debugging signals before being processed by the buffer output module 101 include a DGEN (debugging) signal, a DGMOD (command) signal, an FTX (data transmission) signal, and an FRX (data reception) signal. The debug signal processed by the buffer output module 101 may specifically adopt a UART interface form, and specifically include an RXD (data reception) signal and a TXD (data transmission) signal.
Referring to fig. 2 and 3, fig. 2 and 3 are partial circuit connection diagrams of an output circuit of a speech simulator disclosed in the embodiment of the present application. Because of the limitation of the size of the drawing, the output circuit provided by the embodiment of the present application is divided into two parts and respectively shown in fig. 2 and 3, and the same reference numerals in the two drawings refer to the same signal.
It should be noted that, in fig. 2, the interface conversion main chip of the speech emulator is specifically FT 2232H. FT2232H is compatible with the high-speed and full-speed modes of the USB2.0 interface standard, and has two multiprotocol synchronous serial engines (MPSSE) that allow simultaneous communication using both JTAG, I2C, and SPI channels, while also supporting a UART interface.
As shown in fig. 3, as a specific embodiment, the buffer output module 101 is specifically implemented based on a buffer chip circuit, and a control end and an input end of the buffer chip circuit are both connected to the interface conversion main chip for signal buffering or signal output. And P1 and P2 in fig. 3 are the JTAG interface connection socket and the UART interface connection socket for the voice module, respectively.
For each buffer chip in the buffer chip circuit, when the signal received by the control end is a low-level signal, the corresponding output channel in the chip is opened, and the data of the input end is output from the corresponding output end; when the signal received by the control end is a high level signal, the corresponding output channel in the chip is closed, and the data of the input end is latched. Furthermore, the output buffer module further comprises pull-up resistors respectively connected between each control end of the buffer chip circuit and the power supply.
In one embodiment, the buffer chip may be selected as the SN74LVC125, and the chip is a four-way buffer gate circuit, and each output channel has a corresponding control terminal and has independent single-line driving and tri-state output. In each SN74LVC125, the OE pin is a control terminal, the a pin is an input terminal, the Y pin is an output terminal, and the OE pin is used to control the Y pin with the same number to latch or output a signal received by the a pin with the same number.
Specifically, in the buffer chip circuit shown in fig. 3, four OE pins of the buffer chip U5 are all connected to the dge signal and are all connected to the power supply through a pull-up resistor R10; the four pins A are respectively connected to the FCK signal, the FDO signal, the DGMOD signal and the DGMOD signal; pin Y1 outputs the TCK signal and pin Y2 outputs the TDI signal.
The pin OE1 and the pin OE2 of the buffer chip U6 are both connected with the pin Y4 of the buffer chip U6 and are both connected to a power supply through a pull-up resistor R12; the OE3 pin is connected to the DRST signal and to the power supply through a pull-up resistor R11; pin OE4 is grounded; pin A1 is connected to the FCS signal; pin A3 is grounded through a pull-down resistor R13; pin a4 is connected to the FTX signal; the pin Y1 is connected to the pin OE1 of the buffer chip U7 and is grounded through a pull-down resistor R15; a pin Y3 is connected to a power supply through a pull-up resistor R16, is connected with a grounding capacitor C22, is connected with one end of a RESET key K1 and is used for outputting a RESET signal; the other end of the reset key K1 is grounded; pin Y4 is used to output the TXD signal.
The pin OE2 and the pin OE3 of the buffer chip U7 are both connected to the pin Y3 of the buffer chip U5 and are grounded through a pull-down resistor R14; pin OE4 is connected to a power supply; pin a1 is connected to the FDO signal; pin A3 is used for receiving TDO signals; pin A4 for receiving RXD signals; the Y1 pin is connected with the Y2 pin in parallel, is used for outputting a TMS signal and is connected with the A2 pin of the buffer chip U6; the Y3 pin is connected with the Y2 pin of the buffer chip U6 in parallel and used for outputting an FDI signal; the Y4 pin is used to output the FRX signal.
Further, as a specific embodiment, the buffer output module 101 disclosed in the present application further includes a first rejection RN1 connected between the interface conversion main chip and the buffer chip circuit for transmitting the simulation signal; the second resistor bank RN3 is connected with the simulation signal output port of the buffer chip circuit; the first bank RN1 and the second bank RN3 are used for impedance matching. The signal transmission quality can be improved through impedance matching, and the anti-interference capability is further enhanced.
Similarly, the buffer output module 101 further includes a third draining resistance RN2 connected between the interface conversion main chip and the buffer chip circuit for transmitting the debug signal; the fourth resistor bank RN4 is connected with the debugging signal output port of the buffer chip circuit; the third bank RN2 and the fourth bank RN4 are used for impedance matching.
Based on the above, the output indication module 102 may be embodied as an LED indication module. And further, the LED indication module may include a power status LED indication unit, an emulation communication status LED indication unit, and a debugging communication status LED indication unit.
As a specific example, as shown in fig. 2, the power status LED indicating unit includes a first light emitting diode D1 having an anode connected to a power source, and a ground resistor R8 connected to a cathode of the first light emitting diode D1.
The simulation communication state LED indicating unit comprises a second light emitting diode D2 with an anode connected with the power supply and a second current limiting resistor R7 connected with a cathode of the second light emitting diode D2; the other end of the second current limiting resistor R7 is connected with the simulation signal output end of the interface conversion main chip. The simulation signal output terminal is a port for outputting an FCS signal, and in fig. 2, the other end of R7 is connected to BCBUS3 and BCBUS4, depending on the configuration of the interface conversion chip by those skilled in the art.
The debugging communication state LED indicating unit comprises a third light-emitting diode D3 with the anode connected with the power supply and a third current-limiting resistor R9 connected with the cathode of the third light-emitting diode D3; the other end of the third current limiting resistor R9 is connected with a debugging signal output end of the interface conversion main chip. The debugging signal output end is specifically a port for outputting a DGEN signal.
It is easy to understand that the three LED indicating units can be selected from diodes emitting different colors, such as green, red, and blue diodes, respectively.
The output circuit of the voice simulator provided by the embodiment of the application comprises a buffer output module 101 and an output indication module 102, wherein the buffer output module 101 is connected with an interface conversion main chip of the voice simulator and is used for buffering and outputting simulation signals and debugging signals of the interface conversion main chip; and the output indicating module 102 is connected with the interface conversion main chip and is used for indicating the working state of the interface conversion main chip. Therefore, the buffer output module 101 arranged between the interface conversion main chip and the voice module is utilized, the driving capability of simulation signals and debugging signals can be enhanced on the basis of effectively controlling simulation verification and operation debugging of the voice module, the anti-jamming capability is improved, the normal work of the voice simulator is guaranteed, the product research and development of the voice module are facilitated, and the product market promotion is accelerated.
Further, the embodiment of the present application also discloses a voice simulator, which includes the output circuit of any one of the voice simulators described above.
For the details of the voice emulator, reference may be made to the foregoing detailed description of the output circuit of the voice emulator, and details thereof are not repeated here.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the equipment disclosed by the embodiment, the description is relatively simple because the equipment corresponds to the method disclosed by the embodiment, and the relevant parts can be referred to the method part for description.
It is further noted that, throughout this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The technical solutions provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall into the protection scope of the present application.
Claims (10)
1. An output circuit of a speech emulator, comprising:
the buffer output module is connected with the interface conversion main chip of the voice simulator and is used for buffering and outputting the simulation signal and the debugging signal of the interface conversion main chip;
and the output indicating module is connected with the interface conversion main chip and used for indicating the working state of the interface conversion main chip.
2. The output circuit of claim 1, wherein the buffered output module is compatible with a four-wire system emulated output standard and a two-wire system emulated output standard.
3. The output circuit of claim 1, wherein the buffered output module comprises:
and the control end and the input end of the buffer chip circuit are connected with the interface conversion main chip and are used for signal caching or signal output.
4. The output circuit of claim 3, wherein the buffered output module further comprises:
the first resistor bank is connected between the interface conversion main chip and the buffer chip circuit and used for transmitting the simulation signal;
the second resistor bank is connected with the simulation signal output port of the buffer chip circuit; the first resistor bank and the second resistor bank are used for impedance matching.
5. The output circuit of claim 3, wherein the buffered output module further comprises:
the third resistor bank is connected between the interface conversion main chip and the buffer chip circuit and used for transmitting the debugging signal;
the fourth resistor bank is connected with the debugging signal output port of the buffer chip circuit; the third resistor bank and the fourth resistor bank are used for impedance matching.
6. The output circuit of claim 3, wherein the buffered output module further comprises:
and the pull-up resistors are respectively connected between each control end of the buffer chip circuit and the power supply.
7. The output circuit of any of claims 1 to 6, wherein the output indication module is an LED indication module.
8. The output circuit of claim 7, wherein the LED indication module comprises a power status LED indication unit, a simulation communication status LED indication unit, and a debug communication status LED indication unit.
9. The output circuit of claim 8, wherein the power status LED indication unit comprises a first light emitting diode having an anode connected to a power supply, and a ground resistor connected to a cathode of the first light emitting diode;
the simulation communication state LED indicating unit comprises a second light-emitting diode with an anode connected with a power supply and a second current-limiting resistor connected with a cathode of the second light-emitting diode; the other end of the second current-limiting resistor is connected with the simulation signal output end of the interface conversion main chip;
the debugging communication state LED indicating unit comprises a third light-emitting diode with an anode connected with a power supply and a third current-limiting resistor connected with a cathode of the third light-emitting diode; the other end of the third current limiting resistor is connected with a debugging signal output end of the interface conversion main chip.
10. A speech simulator comprising an output circuit as claimed in any one of claims 1 to 9.
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| CN201921931862.0U CN210488287U (en) | 2019-11-07 | 2019-11-07 | Voice simulator and output circuit thereof |
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| CN201921931862.0U CN210488287U (en) | 2019-11-07 | 2019-11-07 | Voice simulator and output circuit thereof |
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| CN210488287U true CN210488287U (en) | 2020-05-08 |
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