CN204376929U - Based on many asynchronous datas mouth concurrent testing card of industry ethernet - Google Patents
Based on many asynchronous datas mouth concurrent testing card of industry ethernet Download PDFInfo
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Abstract
The utility model discloses a kind of many asynchronous datas based on industry ethernet mouth concurrent testing card.Its formation comprises ethernet controller, Ethernet transformer, FPGA, interface level conversion chip, power circuit.The utility model Advantageous Effects is: by the error code testing adopting fpga chip to achieve multi-path asynchronous data port; User can realize arranging while multi-path asynchronous data port test parameter by computer virtual instrument interface; Error code is inserted at any time, the line status in check test process in test process; Control mode adopts the control of computer virtual instrument interface, version adopts 3U standard C PCI board structure, is integrated in easily in computer testing system, realizes automatic test and remote testing.
Description
Technical field
The utility model belongs to asynchronous data communication field tests, is specifically related to a kind of many asynchronous datas based on industry ethernet mouth concurrent testing card.
Background technology
Many asynchronous datas mouth concurrent testing instrument is widely used in the test of the asynchronous data mouth of the equipment such as integrated digital switch, internet controller, K mouth boxcar, is particularly suitable for the research and development of the said equipment, test and maintenance.
Traditional asynchronous data mouth method of testing, as shown in Figure 1, comprises PC, serial interface cable, equipment under test.Wherein in PC 1 and PC 2, running hyperterminal software, use dial mode the asynchronous data port one of equipment under test and asynchronous data port 2 to be connected, then realizing test by transmitting file mode.
During above-mentioned traditional asynchronous data mouth test, mainly there is following defect:
Two PCs are needed when 1, testing two-way asynchronous data mouth, when user needs to test multi-path asynchronous data port, with regard to needs successively every road asynchronous data message number test, or be equipped with a considerable amount of PC and serial interface cable is tested simultaneously, instrument cost is high, complicated operation.
When 2, carrying out the test of asynchronous data mouth with multiple stage PC, tester needs by platform operation PC, the corresponding test parameter of hyper terminal in PC is successively set simultaneously, as test rate, tested word section format, transfer files content etc., then connect with dial mode, after test terminates, tester needs to collect test result by PC by platform is manual; Testing efficiency is low, and human resources expense is large.
3, because conventional test methodologies is realized by the hyper terminal transfer files in PC, when adding up tested asynchronous data mouth test result, substitute number of times and the number of retransmissions in viewing files transmitting procedure is needed; Result statistics is not directly perceived, cannot react tested asynchronous data port transmission performance parameter accurately, intuitively.
4, because conventional test methodologies needs when testing to set up test special line between the asynchronous data mouth manually to equipment under test, automatic test can not be realized.
5, when multi-path asynchronous data port tested by needs, adopt conventional test methodologies to need operation multiple stage PC to test, really cannot realize multidiameter delay test and remote testing.
Summary of the invention
Based on the problems referred to above, the utility model provides a kind of many asynchronous datas based on industry ethernet mouth concurrent testing card, solves the defect of existing asynchronous data mouth method of testing.
The technical solution adopted in the utility model is: a kind of mouth of many asynchronous datas based on industry ethernet concurrent testing card, it is formed as shown in Figure 2, includes ethernet controller 1, Ethernet transformer 2, fpga chip 3, interface level conversion chip 4, power circuit 5.
Ethernet controller 1 adopts LXT971ALE chip, supports 10Base5,10Base2,10BaseT, 100BASE-X, 100BASE-TX, 100BASE-FX, and can automatically detect connected medium.Ethernet transformer 2 adopts TRC1183NLE, main settling signal transmission, impedance matching, waveform reparation, signal noise suppression and high-voltage isolating etc.Fpga chip 3 adopts the XC4VFX family device of XILINX company, its embedded high-performance PPC405 stone and hardware logic resource.Interface level conversion chip 4 adopts MAX3232E, completes between Transistor-Transistor Logic level and RS232 level and changes.Power circuit 5 adopts dc-dc LTC3417, completes the conversion of+5V power supply and+3.3V ,+2.5V ,+1.2V power supply.
Fpga chip 3 internal logic block diagram as shown in Figure 3.Comprise ethernet interface module 3.1, test data sending module 3.2, test data receiver module 3.3, RAM block 3.4, PPC405 stone 3.5.
Ethernet interface module 3.1 comprises MII administration module 3.1.1, data transmission blocks 3.1.2, data reception module 3.1.3, control module 3.1.4, ethernet module interface 3.1.5.Wherein MII administration module 3.1.1 can provide a media independent interface, is used for connecting outside ethernet control chip LXT971ALE; Data transmission blocks 3.1.2 completes all operations relevant to sending data, comprises and produces header, interpolation CRC check sequence; Data reception module 3.1.3 completes all operations relevant to receiving data, comprises and takes out header, CRC check.
test data sending module 3.2 comprises pattern/Rate control module 3.2.1, pseudo noise code generation module 3.2.2, data format package module 3.2.3, sends control module 3.2.4, test data sending module interface 3.2.5.Pattern in pattern/Rate control module 3.2.1 comprises 2^4,2^5,2^6,2^9,2^11,2^15,2^18,2^20,2^21,2^23, and speed comprises 0.3K, 0.6K, 1.2K, 2.4K, 4.8K, 7.2K, 9.6K, 14.4K, 19.2K, 38.4K, 57.6K, 115.2K, 230.4K.Pseudo noise code generation module 3.2.2 adopts m sequence, and its implementation is that sequence exports and feedback stage mould two adds rear as sequence inputting.For realizing the flexible selection of test pattern, FPGA programming adopts CASE statement mode, and code selection input is controlled by PPC405 stone.Data format package module 3.2.3 mainly completes the assembling of asynchronous data mouth start bit, valid data position, asynchronous data mouth format check position, asynchronous data mouth position of rest, and asynchronous data mouth data format is as Fig. 6.Start bit is the low level of 1 bit data width, and valid data position comprises 6,7,8, and format check position comprises odd, even parity check, no parity check, and position of rest comprises 1,1.5,2.Asynchronous data after transmission control module 3.2.4 mainly completes encapsulation sends, and tranmitting data register is 16 times of asynchronous data mouth speed.
Test data receiver module 3.3 comprises pattern/Rate control module 3.3.1, local pseudo noise code generation module 3.3.2, synchronous detection/Bit Error Code Statistics module 3.3.3, data format deblocking module 3.3.4, receives control module 3.3.5, test data receiver module interface 3.3.6.Wherein pattern/Rate control module 3.3.1 is identical with pattern/Rate control module 3.2.1 method for designing.Local pseudo noise code generation module 3.3.2 is identical with pseudo noise code generation module 3.2.2 method for designing.Synchronous detection/Bit Error Code Statistics module 3.3.3 adopts Error Code Checking Instrument for Bit Comparision.As shown in Figure 7, comparator, bit synchronization module, clock delay module, sequence synchronization module is comprised.Data format decapsulation module 3.3.4 is the inverse process of data format package module 3.2.3.Receive control module 3.3.5 identical with transmission control module 3.2.4.
The PPC405 stone software of fpga chip 3 adopts real time operating system vxworks.
The utility model, can provide 8 passage asynchronous data mouth concurrent testings, each passage is separate simultaneously, and the PPC405 stone in fpga chip scans simultaneously and processes 8 passage peripheral hardware information.
The utility model adopts the Interface of Virtual Instruments control treatment in external computer, and Interface of Virtual Instruments as shown in Figure 4.Interface comprises channel number, start/stop state, synchronous/desynchronizing state, baud rate, pattern, byte format, number of bit errors, the error rate, byte error number, byte error rate, insertion error code.Wherein channel number, start/stop state, baud rate, pattern, byte format, insertion error code are input parameter, and synchronous/desynchronizing state, number of bit errors, the error rate, byte error number, byte error rate are Output rusults.
In above-mentioned computer virtual instrument interface, channel number comprises 1 ~ 8 passage, baud rate comprises 0.3K, 0.6K, 1.2K, 2.4K, 4.8K, 7.2K, 9.6K, 14.4K, 19.2K, 38.4K, 57.6K, 115.2K, 230.4K option, pattern comprises 2^4,2^5,2^6,2^9,2^11,2^15,2^18,2^20,2^21,2^23 option, and byte format comprises effective data bits, format check position, position of rest composition.Wherein the valid data figure place of byte format comprises 6,7,8 options, and format check comprises odd, even parity check, no parity check option, and position of rest comprises 1,1.5,2 options.
The utility model adopts 3U standard C PCI board structure.
The utility model Advantageous Effects is: by the error code testing adopting fpga chip to achieve multi-path asynchronous data port; User can realize arranging while multi-path asynchronous data port test parameter by computer virtual instrument interface; Error code is inserted at any time, the line status in check test process in test process; Control mode adopts the control of computer virtual instrument interface, version adopts 3U standard C PCI board structure, is integrated in easily in computer testing system, realizes automatic test and remote testing.
Accompanying drawing explanation
Fig. 1 is conventional asynchronous data port method of testing.
Fig. 2 is that the present invention connects block diagram.
Fig. 3 is fpga chip internal logic block diagram.
Fig. 4 is computer virtual instrument interface.
Fig. 5 is workflow diagram of the present utility model.
Fig. 6 is asynchronous data mouth data format figure.
Fig. 7 is Error Code Checking Instrument for Bit Comparision theory diagram.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in further detail.
Industry ethernet many asynchronous datas mouth concurrent testing card, as shown in Figure 2, comprises ethernet controller 1, Ethernet transformer 2, fpga chip 3, interface level conversion chip 4, power circuit 5.
Ethernet controller 1 chip model is LXT971ALE.
Ethernet transformer model 2 is TRC1183NLE.
Fpga chip 3 model is XC4VFX60-10FF672C.
Interface level conversion chip 4 comprises 4 altogether, and every sheet completes the independence transmitting-receiving of 2 passage asynchronous datas, and chip model is MAX3232E.
The dc-dc chip model of power circuit 5 is LTC3417.
Above-mentioned fpga chip 3 internal logic block diagram as shown in Figure 3.Comprise ethernet interface module 3.1, test data sending module 3.2, test data receiver module 3.3, RAM block 3.4, PPC405 stone 3.5.
RAM block 3.4 is standard FIFO, and data bit width is 32, and data depth is 1024.
PPC405 stone 3.5 software adopts real time operating system vxworks, mainly realizes the setting of board test parameter, the statistics of test result and computing.See Fig. 5, workflow of the present utility model:
Start, system initialization, arranges test parameter, test, inserts error code, and result exports, and test terminates.
In fpga chip internal logic block diagram, ethernet interface module 3.1 comprises again MII administration module 3.1.1, data transmission blocks 3.1.2, data reception module 3.1.3, control module 3.1.4, ethernet module interface 3.1.5.Wherein MII administration module 3.1.1 can provide a media independent interface, is used for connecting outside ethernet control chip LXT971ALE; Data transmission blocks 3.1.2 completes all operations relevant to sending data, comprises and produces header, interpolation CRC check sequence; Data reception module 3.1.3 completes all operations relevant to receiving data, comprises and takes out header, CRC check.
In fpga chip internal logic block diagram, test data sending module 3.2 comprises again pattern/Rate control module 3.2.1, pseudo noise code generation module 3.2.2, data format package module 3.2.3, sends control module 3.2.4, test data sending module interface 3.2.5.
Pattern in pattern/Rate control module 3.2.1 comprises 2^4,2^5,2^6,2^9,2^11,2^15,2^18,2^20,2^21,2^23, and speed comprises 0.3K, 0.6K, 1.2K, 2.4K, 4.8K, 7.2K, 9.6K, 14.4K, 19.2K, 38.4K, 57.6K, 115.2K, 230.4K.
Pseudo noise code generation module 3.2.2 adopts m sequence, and its implementation is that sequence exports and feedback stage mould two adds rear as sequence inputting.For realizing the flexible selection of test pattern, FPGA programming adopts CASE statement mode, and code selection input is controlled by PPC405 stone.
Data format package module 3.2.3 mainly completes the assembling of asynchronous data mouth start bit, valid data position, asynchronous data mouth format check position, asynchronous data mouth position of rest, and asynchronous data mouth data format is as Fig. 6.Start bit is the low level of 1 bit data width, and valid data position comprises 6,7,8, and format check position comprises odd, even parity check, no parity check, and position of rest comprises 1,1.5,2.
Asynchronous data after transmission control module 3.2.4 mainly completes encapsulation sends, and tranmitting data register is 16 times of asynchronous data mouth speed.
In fpga chip internal logic block diagram, test data receiver module 3.3 comprises again pattern/Rate control module 3.3.1, local pseudo noise code generation module 3.3.2, synchronous detection/Bit Error Code Statistics module 3.3.3, data format decapsulation module 3.3.4, receives control module 3.3.5, test data receiver module interface 3.3.6.Wherein pattern/Rate control module 3.3.1 is identical with pattern/Rate control module 3.2.1 method for designing.Local pseudo noise code generation module 3.3.2 is identical with pseudo noise code generation module 3.2.2 method for designing.Synchronous detection/Bit Error Code Statistics module 3.3.3 adopts Error Code Checking Instrument for Bit Comparision.As shown in Figure 7, comparator, bit synchronization module, clock delay module, sequence synchronization module is comprised.Data format decapsulation module 3.3.4 is the inverse process of data format package module 3.2.3.Receive control module 3.3.5 identical with transmission control module 3.2.4.
The utility model control inerface is external computer virtual instrument interface.Interface comprises channel number, start/stop state, synchronous/desynchronizing state, baud rate, pattern, byte format, number of bit errors, the error rate, byte error number, byte error rate, insertion error code.Wherein channel number, start/stop state, baud rate, pattern, byte format, insertion error code are input parameter; Synchronously/desynchronizing state, number of bit errors, the error rate, byte error number, byte error rate are Output rusults.
In above-mentioned computer virtual instrument interface, channel number comprises 1 ~ 8 passage, baud rate comprises 0.3K, 0.6K, 1.2K, 2.4K, 4.8K, 7.2K, 9.6K, 14.4K, 19.2K, 38.4K, 57.6K, 115.2K, 230.4K option, pattern comprises 2^4,2^5,2^6,2^9,2^11,2^15,2^18,2^20,2^21,2^23 option, and byte format is made up of valid data figure place, format check position, position of rest.Wherein the valid data figure place of byte format comprises 6,7,8 options, and format check position comprises odd, even parity check, no parity check option, and position of rest comprises 1,1.5,2 options.
The utility model adopts 3U standard C PCI board structure.
Claims (1)
1. based on many asynchronous datas mouth concurrent testing card of industry ethernet, it is characterized in that: it comprises: ethernet controller (1), Ethernet transformer (2), fpga chip (3), interface level conversion chip (4), power circuit (5);
Described ethernet controller (1) adopts LXT971ALE chip, supports 10Base5,10Base2,10BaseT, 100BASE-X, 100BASE-TX, 100BASE-FX, and can automatically detect connected medium;
Described Ethernet transformer (2) adopts TRC1183NLE, and main settling signal transmission, impedance matching, waveform reparation, signal noise suppress and high-voltage isolating;
Described fpga chip (3) comprises ethernet interface module (3.1), test data sending module (3.2), test data receiver module (3.3), RAM block (3.4), PPC405 stone (3.5);
Described ethernet interface module (3.1) comprises MII administration module (3.1.1), data transmission blocks (3.1.2), data reception module (3.1.3), control module (3.1.4), ethernet module interface (3.1.5); Described MII administration module (3.1.1) can provide a media independent interface, is used for connecting outside ethernet control chip LXT971ALE; Described data transmission blocks (3.1.2) completes all operations relevant to sending data, comprises and produces header, interpolation CRC check sequence; Described data reception module (3.1.3) completes all operations relevant to receiving data, comprises and takes out header, CRC check;
Described test data sending module (3.2) comprises pattern/Rate control module (3.2.1), pseudo noise code generation module (3.2.2), data format package module (3.2.3), sends control module (3.2.4), test data sending module interface (3.2.5); Described pseudo noise code generation module (3.2.2) adopts m sequence, and its implementation is that sequence exports and feedback stage mould two adds rear as sequence inputting; Described data format package module (3.2.3) mainly completes the assembling of asynchronous data mouth start bit, valid data position, asynchronous data mouth format check position, asynchronous data mouth position of rest, start bit is the low level of 1 bit data width, valid data position comprises 6,7,8, format check position comprises odd, even parity check, no parity check, and position of rest comprises 1,1.5,2; Described transmission control module (3.2.4) mainly completes the asynchronous data after encapsulation and sends, and tranmitting data register is 16 times of asynchronous data mouth speed;
Described test data receiver module (3.3) comprises pattern/Rate control module (3.3.1), local pseudo noise code generation module (3.3.2), synchronous detection/Bit Error Code Statistics module (3.3.3), data format deblocking module (3.3.4), receives control module (3.3.5), test data receiver module interface (3.3.6);
Described PPC405 stone (3.5) is scanned simultaneously and is processed 8 passage peripheral hardware information;
Described interface level conversion chip (4) adopts MAX3232E, completes between Transistor-Transistor Logic level and RS232 level and changes;
Described power circuit (5) adopts dc-dc LTC3417, completes the conversion of+5V power supply and+3.3V ,+2.5V ,+1.2V power supply.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106375161A (en) * | 2016-12-06 | 2017-02-01 | 中国电子科技集团公司第四十研究所 | 10-gigabit Ethernet tester |
| CN108242981A (en) * | 2016-12-27 | 2018-07-03 | 航天信息股份有限公司 | Device for detecting code error |
| CN114553369A (en) * | 2022-01-10 | 2022-05-27 | 合肥埃科光电科技股份有限公司 | System and method for detecting performance of digital signal cable based on FPGA |
-
2014
- 2014-07-08 CN CN201420373761.7U patent/CN204376929U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106375161A (en) * | 2016-12-06 | 2017-02-01 | 中国电子科技集团公司第四十研究所 | 10-gigabit Ethernet tester |
| CN106375161B (en) * | 2016-12-06 | 2019-12-20 | 中国电子科技集团公司第四十一研究所 | Ten-gigabit Ethernet testing device |
| CN108242981A (en) * | 2016-12-27 | 2018-07-03 | 航天信息股份有限公司 | Device for detecting code error |
| CN108242981B (en) * | 2016-12-27 | 2021-09-10 | 航天信息股份有限公司 | Error code detection device |
| CN114553369A (en) * | 2022-01-10 | 2022-05-27 | 合肥埃科光电科技股份有限公司 | System and method for detecting performance of digital signal cable based on FPGA |
| CN114553369B (en) * | 2022-01-10 | 2023-11-03 | 合肥埃科光电科技股份有限公司 | System and method for detecting digital signal cable performance based on FPGA |
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